- 08 Feb, 2014 1 commit
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Jeffrey Lee authored
Detail: This adds support for the *ShowVFPRegs command, which is basically VFP equivalent of *ShowFPRegs. However unlike *ShowFPRegs it allows for any arbitrary VFP context to be viewed, not just the last context that caused an exception: *ShowVFPRegs [E] for showing the exception context *ShowVFPRegs A <address> for showing a context at a specific address *ShowVFPRegs C for showing the current context File changes: - HelpSrc, Resources/UK/CmdHelp - Added *ShowVFPRegs help text - Resources/Germany/Messages, Resources/UK/Messages - New message tokens for *ShowVFPRegs output - s/Debugger - *ShowVFPRegs implementation - actions/ARMv7_VFP - VPUSH or VPOP of >16 singleword registers were incorrectly being flagged as unpredictable; it's only the doubleword version which should have that restriction. Admin: Tested on Raspberry Pi German messages are in need of translation Version 1.86. Tagged as 'Debugger-1_86'
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- 28 Nov, 2013 1 commit
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Jeffrey Lee authored
Detail: This change adds up-to-date VFP & NEON disassembly to the module, by way of a partially machine-generated disassembler written in C. It's also possible to build a standalone disassembler utility (dubbed 'dis2') which is 100% C and has support for all ARM instructions (including some obscure stuff the assembler disassembler currently lacks, e.g. XScale DSP instructions). One day this may completely replace the assembler disassembler, but at the moment it's a bit bulky and probably has a few bugs left to squash. The disassembler is also fairly flexible, supporting various output formatting options. Main changes: - Makefile - Rewritten to switch over to using the CModule makefile fragment instead of AAsmModule, to allow the C code to be included in the component. Also added 'dis2' as an alternative component to build as. - Resources/UK/Messages, Resources/Germany/Messages - Updated with new disassembler messages - s/Debugger - Add new UseCVFPNEON switch to allow control over whether the module builds with the C VFP/NEON disassembler or the original assembler VFP disassembler - s/CGlue - Glue code used with the C disassembler to bridge the gap between the assembler world and the C world - actions/* - A set of decgen action files describing what to do for each instruction the new disassembler supports. These are basically just blocks of C code - although they need to match up with the encoding names in Library/Misc/decgen/encodings - cache/* - Folder for decgen to cache decision trees in. Building the decision tree for the disassembler is currently a lengthy process, but caching the trees reduces the build time to a fraction of the full time. - c/head - Stub C file that decgen prepends to the code it generates - c/main - main frontend for the standalone version of the disassembler - c/support - Reimplementation of the standard C library functions required for the disassembler. This allows us to avoid a runtime dependency on the shared C library, and also allows us to deal with control-terminated strings from messagetrans where relevant. For convenience this file also has the main entry point that's called from assembler. - c/util - Utility code for outputting various forms of instruction, decoding immediate constants, etc. - h/dis2 - Header file for the C code - Test/c/testbed - Simple C testbed app to allow the output of dis2 to be compared against the Debugger module and decaof - !MkDis2,fd7 - Script to allow easy building of the standalone 'dis2' disassembler Bugfixes: - s/ARMv6 - Change 'ROR#' to 'ROR #' for UXTAB, etc. disassembly. Fix bitfield extract & clear instructions to detect unpredictable/invalid bitfield definitions Misc other changes: - s/* - Source files updated so s/Debugger contains a list of GETs instead of each source file LNK'ing to the next Admin: Tested in ROM form on BB-xM, and as softload on Iyonix German messages are in need of translation Requires Library-1_65 and BuildSys-6_34 Version 1.85. Tagged as 'Debugger-1_85'
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- 19 Oct, 2013 1 commit
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Robert Sprowson authored
The debugger had some embryonic ARMv6 knowhow, switched out due to being incomplete. Enabling and finishing off ARMv6, then adding ARMv6K, ARMv6T2, ARMv6 security extensions, and ARMv7. That just leaves - ARMv7MP (multiprocessor extensions: PLDW) - ARMv7VE (virtualisation extensions: ERET, MRS copro, MSR copro) - Advanced SIMD (probably worth thinking about) - Thumb2 (questionable why Thumb is supported at all as the tools & OS don't use it) The syntax follows the pre UAL spirit for the new instructions (cf. ADDCCS versus ADDSCC). Removed binary V6test binary, replaced with more comprehensive v6/v7 source. Tested softloaded inspecting the output in StrongEd. Version 1.84. Tagged as 'Debugger-1_84'
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- 24 Sep, 2011 1 commit
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Jeffrey Lee authored
Detail: s/Debugger - Tweaked a few LDM/STM instructions to fix some objasm 4 warnings. Disabled some 26bit code in 32bit configs to avoid more warnings. Fix BreakClr to work on 32bit systems if the breakpoint address is >=64M. Admin: Tested on rev A2 BB-xM Version 1.83. Tagged as 'Debugger-1_83'
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- 04 Aug, 2011 1 commit
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Jeffrey Lee authored
Detail: s/Debugger - Try reading DebuggerSpace location using OS_ReadSysInfo 6 before falling back on legacy address. Compute appropriate MOV PC,DebuggerSpace instruction instead of using hard-coded one. Admin: Tested on rev A2 BB-xM Version 1.82. Tagged as 'Debugger-1_82'
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- 22 Mar, 2010 1 commit
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Jeffrey Lee authored
Detail: s/Debugger - Reworked MemoryI_Code: * Avoid alignment faults when disassembling Thumb instructions by using LDRH or LDR-and-shift depending on compile-time architecture * Split ARM & Thumb disassembly into two seperate paths to (perhaps) increase readability * Cleaned up the code so it only reads each memory location once Admin: Tested on rev C2 beagleboard. Current thumb disassembler looks like it could do with a bit of an overhaul when full support for the 32bit encodings is added. *memoryi code could also be made a bit nicer if we don't mind thumb disassembly failing if attempted on a CPU that can't (reliably) LDRH. Version 1.81. Tagged as 'Debugger-1_81'
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- 30 Jan, 2010 1 commit
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Jeffrey Lee authored
Fix code to be fully aware of 64bit parameter flags, fix accidental alignment exceptions on ARMv6/v7 Detail: s/Debugger - All code which calls ReadOneParm, ReadParm, etc. now correctly sets r10 to the correct value depending on whether they want to parse 64bit numbers or not. This was the cause of *InitStore malfunctioning and (presumably) trashing whatever R11 pointed to (bug #232) Also fixed MemoryHeader causing an unintentional alignment exception when testing if rotated or unaligned loads are in use. The CP15 registers are now interrogated instead. Admin: Tested on rev C2 beagleoard. *Memory with unaligned addresses no longer aborts, and *InitStore <val> now uses the correct value, and seems to no longer trash memory Fixes bug #232 Version 1.80. Tagged as 'Debugger-1_80'
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- 26 Jun, 2009 1 commit
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Ben Avison authored
Detail: Debugger now handles registering and deregistering its messages file with ResourceFS when you build a RAM (standalone) variant. This obsoletes the DbgMess module. Admin: Tested briefly Version 1.79. Tagged as 'Debugger-1_79'
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- 16 Jun, 2009 1 commit
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Ben Avison authored
Detail: CPU version is no longer specified in the makefile - it's better to inherit it from the build environment now that we actually set it appropriately. Admin: Built but not tested. Binary should be unchanged - this only affects the warnings generated during assembly. Version 1.78. Not tagged
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- 17 May, 2009 1 commit
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Ben Avison authored
Detail: * Added knowledge of the ARMv5TEJ / ARMv6 CPSR flags J, GE[3:0], E and A, plus Monitor mode * *Memory, *Memory H, *MemoryA and *MemoryA H can now access unaligned addresses; the header line in unaligned cases adapts depending on whether the CPU natively rotates or does unaligned loads * Added *Memory D and *MemoryA D for accessing 64-bit words using LDRD / STRD * Removed check for 32-bit mode before doing LDRH - this is nonsensial now that there are 32-bit builds for IOMD-class machines. I've decided to let it attempt LDRH even on platforms where it might not work or might be an undefined instruction - this gets us "closer to the metal", and it's not like *Memory couldn't already throw exceptions in normal use * Removed redundant clauses of a few build options, it was getting impractical to maintain the alternate build variants Admin: Tested on rev B7 beagleboard. Requires an updated kernel in order to be able to specify 64-bit values on the command line or interactively (but even on older kernels you can enter a value less than 2^32 to *MemoryA D) Version 1.78. Tagged as 'Debugger-1_78'
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- 30 Jul, 2004 1 commit
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Kevin Bracey authored
Modified ASCII display in *Memory etc to read memory using the same access size as the main output. This helps with some hardware registers that only support, say, word-sized accesses. Note that the memory locations are still read a second time for the ASCII display, so it's still not ideal for read-sensitive hardware. Added some ARMv6 support to disassembly, but this is incomplete and switched out at the moment. Version 1.77. Tagged as 'Debugger-1_77'
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- 03 Dec, 2002 2 commits
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Ben Avison authored
Detail: * Added 'H' flag to *Memory and *MemoryA to allow half-word memory accesses. On 26-bit machines, this is emulated using 32-bit reads and read-modify- writes; on 32-bit machines, LDRH and STRH are used. Address header in *Memory byte mode changed to be only one digit per byte for consistency with word and half-word modes. *MemoryA H in interactive mode gives a Thumb disassembly. * STM Rn!,{reg_list_including_Rn} is actually allowed, provided Rn is the lowest register in the list. Warning code adjusted accordingly. Admin: Tested on Risc PC and Tungsten. Version 1.76. Tagged as 'Debugger-1_76'
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Ben Avison authored
Detail: * Added Q bit to *ShowRegs * Added FMSRR, FMRRS, FMDRR and FMRRD to VFP support * Shortened lots of VFP literals by treating common "F" prefix separately * Cirrus DSP support (switched out) * Piccolo support (not even linked in) * ARM/Thumb disassembly test programs added * Bugfix: code variable init code was trashing the flags that indicated whether zero page branch table (used for breakpoints in 32-bit mode) needs creating Admin: Builds identical binary to 5.00 release, repository changes were build- related only. Version 1.75. Tagged as 'Debugger-1_75'
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- 01 Jun, 2001 1 commit
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David Cotton authored
Detail: Build would not build with this version of the module as the last change to the makefile did not include the line needed to export the Debugger header. This line has now been added. Added an !MkExport to enable testing of the export. Converted the existing Mk... obey files to !Mk... files. Admin: Some basic testing. Version 1.74. Tagged as 'Debugger-1_74'
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- 10 May, 2001 1 commit
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Kevin Bracey authored
* Changes to message files to correct syntax errors. * *MemoryX P works on IOMD-based systems is OS_Memory 13 fails. * Changed to use ObjAsm and centralised Makefiles. Version 1.73. Tagged as 'Debugger-1_73'
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- 09 May, 2001 1 commit
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Kevin Bracey authored
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- 01 May, 2001 1 commit
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Mike Stephens authored
memory, memorya and memoryi commands support p option, which specifies physical rather than logical addresses only functional with kernel that support OS_Memory 14 and 15 Version 1.72. Not tagged
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- 30 Apr, 2001 1 commit
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Steve Revill authored
* Added the Disassemble$Options system variable. Detail: * MakeMess now does a CDir command (in case you run it before running MkRom). MkClean now includes a 'stripdepnd' call. * There is a new system (code) variable created on module init called Disassemble$Options. This controls (at the moment) register naming for disassembly. Admin: Tested on RiscOS 4 and 3.70. Version 1.72. Tagged as 'Debugger-1_72'
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- 18 Apr, 2001 1 commit
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Kevin Bracey authored
FPEmulators. Version 1.71. Tagged as 'Debugger-1_71'
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- 21 Mar, 2001 3 commits
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Steve Revill authored
Changed wacky immediate format. Detail: SWI number stuff now uses an internal routine rather than a call to SWI OS_ConvertHex... When someone disassembles a wacky immediate, it is represented as "<OP> Rd,Rn,#&xx,x" rather than the non-standard "<OP> Rd,Rn,#&xx,ROR #x" format. This can then be assembled and conforms to ARM's standards. Admin: Tested on RiscPC My editor blew-up in the middle of srccommit on Debugger-1_69 so don't use that version! Version 1.70. Tagged as 'Debugger-1_70'
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Steve Revill authored
Changed wacky immediate format. Detail: SWI number stuff now uses an internal routine rather than a call SWISWI Version 1.69. Tagged as 'Debugger-1_69'
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Steve Revill authored
SWI number stuff also implemented in Thumb mode. Detail: Unknown SWIs were dissasembled as an 8 nibble hexadecimal number. This has been reduced to a six nibble number (as the top byte is always zero). The unknown SWI disassembled as a number stuff has also been added to Thumb mode disassembly. Only two nibbles are displayed in this mode. Admin: Tested on a RiscPC. Version 1.68. Tagged as 'Debugger-1_68'
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- 15 Feb, 2001 1 commit
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Kevin Bracey authored
Version 1.67. Tagged as 'Debugger-1_67'
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- 14 Feb, 2001 1 commit
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Steve Revill authored
Detail: The routine was returning the length of the disassembled instruction *including* the terminator. Changed to exclude it as the others do Admin: Tested on RiscPC Version 1.66. Tagged as 'Debugger-1_66'
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- 08 Feb, 2001 1 commit
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Kevin Bracey authored
* *MemoryI T now disassembles 24 instructions by default rather than 48. Version 1.65. Tagged as 'Debugger-1_65'
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- 31 Jan, 2001 1 commit
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Kevin Bracey authored
* Fixed disassembly of Thumb high MOV/ADD/CMP instructions. Version 1.64. Tagged as 'Debugger-1_64'
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- 30 Jan, 2001 1 commit
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Steve Revill authored
Detail: ADDS Rd,PC,#.. and SUBS Rd,PC,#.. were being incorrectly disassembled as ADR pseudo-instructions. Fixed. Unknown SWIs (such as OS_Undefined and User) are disassembled in the form 'SWI &<num>' so that you can re-assemble the code (and it makes more sense if you don't have a module loaded which defined that SWI). Admin: Tested on RiscPC I also added some notes on ARM v5TE to the Doc directory. May be of some use when adding compatibility for that to Debugger. Version 1.63. Tagged as 'Debugger-1_63'
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- 08 Sep, 2000 1 commit
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Kevin Bracey authored
* Changed invalid instruction to &E7FFFFFF (as per ARM recommendation that &E7FxxxFx should be used) * Branch disassembly changed - when running on a 26-bit systems, branch instructions in the lower 64M will be wrapped within 64M, but branches above 64M will not. * PC-relative LDRH family instructions calculated target address incorrectly. Version 1.62. Tagged as 'Debugger-1_62'
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- 11 Jul, 2000 1 commit
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Kevin Bracey authored
Version 1.61. Tagged as 'Debugger-1_61'
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- 02 May, 2000 1 commit
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Kevin Bracey authored
* New *ShowFPRegs command. * Added ARMv5 instructions (BLX, CLZ, BKPT, CDP2 et al) * Handling of instruction extension space adjusted as per ARMv4. * Fixed some Thumb instructions. * Added "info" form of LDC and STC. * NV condition code is now undefined, except for the new instructions using it. Version 1.60. Tagged as 'Debugger-1_60'
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- 20 Apr, 1999 1 commit
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David Cotton authored
Version 1.59. Tagged as 'Debugger-1_59'
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- 19 Apr, 1999 1 commit
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David Cotton authored
Version 1.58. Tagged as 'Debugger-1_58'
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- 21 Sep, 1998 3 commits
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Kevin Bracey authored
Version 1.57. Not tagged
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Kevin Bracey authored
Makefile changed to use LocalRes$Path. Changed to use srccommit. Version 1.57. Tagged as 'Debugger-1_57'
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Kevin Bracey authored
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- 09 May, 1997 2 commits
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Kevin Bracey authored
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Kevin Bracey authored
Thumb disassembly added.
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- 21 Jan, 1997 1 commit
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Neil Turton authored
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- 21 Nov, 1996 1 commit
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Neil Turton authored
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- 05 Nov, 1996 1 commit
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Neil Turton authored
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