Commit e2274470 authored by Jeffrey Lee's avatar Jeffrey Lee

Add *ShowVFPRegs command

Detail:
  This adds support for the *ShowVFPRegs command, which is basically VFP equivalent of *ShowFPRegs. However unlike *ShowFPRegs it allows for any arbitrary VFP context to be viewed, not just the last context that caused an exception:
  *ShowVFPRegs [E] for showing the exception context
  *ShowVFPRegs A <address> for showing a context at a specific address
  *ShowVFPRegs C for showing the current context
  File changes:
  - HelpSrc, Resources/UK/CmdHelp - Added *ShowVFPRegs help text
  - Resources/Germany/Messages, Resources/UK/Messages - New message tokens for *ShowVFPRegs output
  - s/Debugger - *ShowVFPRegs implementation
  - actions/ARMv7_VFP - VPUSH or VPOP of >16 singleword registers were incorrectly being flagged as unpredictable; it's only the doubleword version which should have that restriction.
Admin:
  Tested on Raspberry Pi
  German messages are in need of translation


Version 1.86. Tagged as 'Debugger-1_86'
parent 027eaf81
......@@ -91,6 +91,16 @@ ShowFPRegs_Help
ShowFPRegs_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= "", 0
ShowVFPRegs_Help
= "*",TokenEscapeChar,Token0
= " displays the contents of a VFP/NEON context. The command can"
= " show the contents of a context at a specific address, the"
= " current context, or the exception context (default)."
= 13
ShowVFPRegs_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= " [A <addr>|C|E|]", 0
|
BreakClr_Help DCB "HDBGBCL", 0
BreakClr_Syntax DCB "SDBGBCL", 0
......@@ -124,6 +134,9 @@ ShowRegs_Syntax DCB "SDBGSHR", 0
ShowFPRegs_Help DCB "HDBGSFR", 0
ShowFPRegs_Syntax DCB "SDBGSFR", 0
ShowVFPRegs_Help DCB "HDBGSVR", 0
ShowVFPRegs_Syntax DCB "SDBGSVR", 0
]
ALIGN
......
No preview for this file type
......@@ -95,6 +95,23 @@ F06:Control:
F05: Enabled exceptions:
F07: Cumulative exceptions:
V00:VFP context &
V01:Context flags &
V02:invalid,
V03:FSTMX format word =
V04:Round to nearest,
V05:Round to +inf,
V06:Round to -inf,
V07:Round to zero,
V09:Vector length
V10: stride
V11: Remaining iterations:
V12: Flags:
V13: Options:
V14: Enabled exceptions:
V15: Cumulative exceptions:
V16: Pending/potential exceptions:
FS00:Old FPE
FS01:FPE 400
FS80:FPPC
......
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.85"
Module_Version SETA 185
Module_MajorVersion SETS "1.86"
Module_Version SETA 186
Module_MinorVersion SETS ""
Module_Date SETS "28 Nov 2013"
Module_ApplicationDate SETS "28-Nov-13"
Module_Date SETS "08 Feb 2014"
Module_ApplicationDate SETS "08-Feb-14"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "castle/RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.85"
Module_HelpVersion SETS "1.85 (28 Nov 2013)"
Module_FullVersion SETS "1.86"
Module_HelpVersion SETS "1.86 (08 Feb 2014)"
END
/* (1.85)
/* (1.86)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.85
#define Module_MajorVersion_CMHG 1.86
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 28 Nov 2013
#define Module_Date_CMHG 08 Feb 2014
#define Module_MajorVersion "1.85"
#define Module_Version 185
#define Module_MajorVersion "1.86"
#define Module_Version 186
#define Module_MinorVersion ""
#define Module_Date "28 Nov 2013"
#define Module_Date "08 Feb 2014"
#define Module_ApplicationDate "28-Nov-13"
#define Module_ApplicationDate "08-Feb-14"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.85"
#define Module_HelpVersion "1.85 (28 Nov 2013)"
#define Module_LibraryVersionInfo "1:85"
#define Module_FullVersion "1.86"
#define Module_HelpVersion "1.86 (08 Feb 2014)"
#define Module_LibraryVersionInfo "1:86"
......@@ -436,7 +436,7 @@ VPOP_A2(cond,Vd:D,imm8,nonstandard)
COMMON
ONLY1(VFP_ASIMD_common);
uint32_t regs = imm8;
_UNPREDICTABLE(!regs || (regs > 16) || ((Vd_D+regs) > 32));
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
sprintf(params->buf,(params->opt->vfpual?"VPOP%s\t{":"FLDMIAS%s\t%s!,{"),condition(JUSTPARAMS,cond),REG(13));
if(regs > 1)
scatf(params->buf,"S%d%cS%d}",Vd_D,(regs>2?'-':','),Vd_D+regs-1);
......@@ -474,7 +474,7 @@ VPUSH_A2(cond,Vd:D,imm8,nonstandard)
COMMON
ONLY1(VFP_ASIMD_common);
uint32_t regs = imm8;
_UNPREDICTABLE(!regs || (regs > 16) || ((Vd_D+regs) > 32));
_UNPREDICTABLE(!regs || ((Vd_D+regs) > 32));
sprintf(params->buf,(params->opt->vfpual?"VPUSH%s\t{":"FSTMDBS%s\t%s!,{"),condition(JUSTPARAMS,cond),REG(13));
if(regs > 1)
scatf(params->buf,"S%d%cS%d}",Vd_D,(regs>2?'-':','),Vd_D+regs-1);
......
......@@ -246,6 +246,7 @@
GET Hdr:CPU.FPA
GET Hdr:CPU.Arch
GET Hdr:OSRSI6
GET Hdr:VFPSupport
GET Hdr:Debugger
......@@ -762,7 +763,7 @@ Debug_ServiceBody
serviceresourcefsstarting
Push "R0,LR"
ADRL R0,resourcefsfiles
BL Resources
MOV LR,PC ; LR -> return address
MOV PC,R2 ; R2 -> address to call
Pull "R0,PC"
......@@ -796,7 +797,7 @@ Debug_Die Entry
BL destroy_codevar
[ standalone
ADRL R0,resourcefsfiles
BL Resources
SWI XResourceFS_DeregisterFiles ; ignore errors
]
......@@ -823,6 +824,7 @@ ihflag * 0
Command MemoryI, 7, 1, ihflag ; P T A +/- B + C
Command ShowRegs, 0, 0, ihflag
Command ShowFPRegs, 0, 0, ihflag
Command ShowVFPRegs, 2, 0, ihflag
DCB 0 ; end of table
GET TokHelpSrc
......@@ -5924,6 +5926,425 @@ open_messagefile Entry r0-r2
STR r0, MessageFile_Open
EXIT
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ShowVFPRegs_Code ROUT
Entry
LDR wp, [r12]
; Check arguments
MOV r1, r0
BL SkipSpaces
BLO %FT50
ADD r1, r1, #1
LDRB r2, [r1], #1
BIC r0, r0, #32
CMP r2, #32
BGT %FT99
TEQ r0, #"A" ; A -> at
BEQ %FT10
TEQ r0, #"E" ; E -> exception
BEQ %FT50
TEQ r0, #"C" ; C -> current
BNE %FT99
SWI XVFPSupport_ActiveContext
MOVVC r1, r0
BLVC ShowThisVFPContext
EXIT
10
; Show context at specific address
BL SkipSpaces
BLO %FT99
MOV r0, #16
SWI XOS_ReadUnsigned
MOVVC r0, r2
MOVVC r1, r2
BLVC ShowThisVFPContext
EXIT
50
; Show exception context
MOV r0, #VFPSupport_ExceptionDump_GetDump+VFPSupport_ExceptionDump_GetContext
SWI XVFPSupport_ExceptionDump
EXIT VS
MOV r2, r0 ; Remember in case of error
BL ShowThisVFPContext
; Preseve any error over free call
SavePSR r3
MOV r4, r0
MOV r0, #ModHandReason_Free
SWI XOS_Module
RestPSR r3
MOV r0, r4
EXIT
99 ADR r0, ShowVFPRegs_Error
BL CopyError
EXIT
ShowVFPRegs_Error
DCD ErrorNumber_Syntax
DCB "SDBGSVR", 0
ALIGN
ShowThisVFPContext ROUT
; r0 = context
; r1 = address to say it came from
Entry "r6-r11"
MOV r6, r0
BL message_writes
DCB "V00", 0 ; "VFP context &"
ALIGN
MOVVC r10, r1
BLVC DisplayHexWord
SWIVC XOS_NewLine
MOVVC r1, #VFPSupport_ExamineContext_Serialise
SWIVC XVFPSupport_ExamineContext
EXIT VS
MOV r11, r1
BL message_writes
DCB "V01", 0 ; "Context flags &"
ALIGN
MOVVC r10, r0
BLVC DisplayHexWord
SWIVC XOS_NewLine
EXIT VS
; Parse the dump descriptor block
10
LDR r0, [r3], #4
CMP r0, #-1
EXIT EQ
MOV r4, r0, LSR #16
BIC r0, r0, r4, LSL #16
CMP r0, #VFPSupport_Field_FPSCR
BEQ %FT20
CMP r0, #VFPSupport_Field_FPEXC
BEQ %FT30
CMP r0, #VFPSupport_Field_FPINST
ADREQ r0, fpinst
BEQ %FT40
CMP r0, #VFPSupport_Field_FPINST2
ADREQ r0, fpinst2
BEQ %FT40
CMP r0, #VFPSupport_Field_FSTMX
BEQ %FT50
CMP r0, #VFPSupport_Field_RegDump
BEQ %FT60
; Some unknown field - skip it
B %BT10
20
; FPSCR display
ADREQ r0, FPSCRList
SWI XOS_Write0
LDRVC r10, [r6, r4]
BLVC DisplayHexWord
EXIT VS
MOV r4, r0
BL ShowVFPFlags
EXIT VS
; Show rounding mode
ANDVC r0, r10, #FPSCR_RMODE_MASK
ADRVC r1, RMODEList
ADDVC r0, r1, r0, LSR #FPSCR_RMODE_SHIFT-2
BLVC message_write0
EXIT VS
; Show vector length & stride
BL message_writes
DCB "V09", 0 ; "Vector length "
ALIGN
EXIT VS
[ NoARMT2
AND r0, r10, #FPSCR_LEN_MASK
MOV r0, r0, LSR #FPSCR_LEN_SHIFT
|
ASSERT FPSCR_LEN_MASK = (7<<FPSCR_LEN_SHIFT)
UBFX r0, r10, #FPSCR_LEN_SHIFT, #3
]
AND r1, r10, #FPSCR_STRIDE_MASK
; The only valid encodings are 0 and 3, corresponding to stride 1 and 2
MOVS r1, r1, LSR #FPSCR_STRIDE_SHIFT
TEQNE r1, #3
BNE %FT25
; Nonzero stride with nonzero length is invalid
TEQ r1, #0
TEQNE r0, #0
BNE %FT25
; Nonzero stride with length field > 3 is invalid
CMP r1, #0
CMPHI r0, #3
BHI %FT25
; For double precision operations a nonzero stride with length field > 1 is invalid, but we can't check for that as we don't know what the user's doing
ADD r0, r0, #"1" ; Convert to actual length
SWI XOS_WriteC
EXIT VS
BL message_writes
DCB "V10", 0 ; " stride "
ALIGN
EORVC r0, r1, #1+"0" ; 0 -> "1", 3 -> "2"
SWIVC XOS_WriteC
SWIVC XOS_WriteI+","
24
; Remainder can be handled by ShowVFPFlags
BLVC ShowVFPFlags
BVC %BT10
EXIT
25
BL message_writes
DCB "V02", 0
ALIGN
B %BT24
30
; FPEXC display
ADREQ r0, FPEXCList
SWI XOS_Write0
LDRVC r10, [r6, r4]
BLVC DisplayHexWord
EXIT VS
MOV r4, r0
BL ShowVFPFlags
EXIT VS
; Show remaining iterations, but only if field is valid
; DEX+VV set or EX set
TST r10, #FPEXC_DEX
TSTNE r10, #FPEXC_VV
TSTEQ r10, #FPEXC_EX
BEQ %FT35
BL message_writes
DCB "V11", 0 ; "Remaining iterations: "
ALIGN
[ NoARMT2
AND r0, r10, #FPEXC_VECITR_MASK
MOV r0, r0, LSR #FPEXC_VECITR_SHIFT
|
ASSERT FPEXC_VECITR_MASK = 7<<FPEXC_VECITR_SHIFT
UBFX r0, r10, #FPEXC_VECITR_SHIFT, #3
]
ADD r0, r0, #"1"
ASSERT ("0" :AND: 8)=0
BIC r0, r0, #8
SWI XOS_WriteC
SWIVC XOS_NewLine
EXIT VS
35
BL ShowVFPFlags
BVC %BT10
EXIT
40
SWI XOS_Write0
LDRVC r10, [r6, r4]
BLVC DisplayHexWord
SWIVC XOS_WriteI+32
; The contents of the FPINST registers should be instructions, so let's
; be useful and show the disassembly
MOVVC r0, r10
MOVVC r1, #0
SWIVC XDebugger_Disassemble
MOVVC r0, r1
SWIVC XOS_Write0
SWIVC XOS_NewLine
BVC %BT10
EXIT
50
BL message_writes
DCB "V03", 0 ; "FSTMX format word = "
ALIGN
LDRVC r10, [r6, r4]
BLVC DisplayHexWord
SWIVC XOS_NewLine
BVC %BT10
EXIT
60
BL message_writes
DCB "M17", 0
ALIGN
ADDVC r10, r6, r4
BLVC DisplayHexWord
EXIT VS
BL message_writes
DCB "M18", 0
ALIGN
EXIT VS
; Display register dump as doubleword registers, two columns
MOV r0, #0
MOV r1, r10
61
SWI XOS_NewLine
62
EXIT VS
CMP r0, r11
BNE %FT63
TST r0, #1
SWINE XOS_NewLine
EXIT VS
B %BT10
63
SWI XOS_WriteI+"D"
MOVVC r8, r0
BLVC DisplayDecimalNumber
EXIT VS
CMP r0, #10
SWILT XOS_WriteI+32
EXIT VS
SWI XOS_WriteS
DCB " = &", 0
ALIGN
LDR r10, [r1, #4]
BL DisplayHexWord
LDR r10, [r1], #8
BLVC DisplayHexWord
EXIT VS
ADD r0, r0, #1
TST r0, #1
BEQ %BT61
SWI XOS_WriteI+32
B %BT62
ShowVFPFlags ROUT
; In: R4 -> flags list
; R10 = value
; Out: R0 = corrupt or error
; R4 updated
Entry "r1,r2,r8"
MOV r1, #1
10
LDRB r2, [r4], #1
TEQ r2, #255
EXIT EQ
TEQ r2, #254
BEQ %FT30
TEQ r2, #253
BEQ %FT40
20
LDRB r0, [r4], #1
TEQ r0, #0
BEQ %BT10
TST r10, r1, LSL r2
ORREQ r0, r0, #32
SWI XOS_WriteC
BVC %BT20
EXIT
30
MOV r0, r4
BL message_write0
ADDVC r4, r4, #4
BVC %BT10
EXIT
40
SWI XOS_NewLine
BVC %BT10
EXIT
MACRO
VFPRegBit $bits, $name
LCLA bit
LCLA mask
mask SETA $bits
count SETA 0
WHILE (mask :AND: 1)=0 :LAND: (mask > 0)
mask SETA mask :SHR: 1
count SETA count + 1
WEND
DCB count
DCB "$name"
DCB 0
MEND
FPSCRList
DCB "FPSCR = ", 0
DCB 254, "V12", 0 ; "Flags:"
VFPRegBit FPSCR_N, " N"
VFPRegBit FPSCR_Z, "Z"
VFPRegBit FPSCR_C, "C"
VFPRegBit FPSCR_V, "V"
VFPRegBit FPSCR_QC, "Q"
DCB 253
DCB 254, "V13", 0 ; "Options: "
DCB 255
VFPRegBit FPSCR_AHP, " AHP"
VFPRegBit FPSCR_DN, " DN"
VFPRegBit FPSCR_FZ, " FZ"
DCB 253
DCB 254, "V14", 0 ; "Enabled exceptions:"
VFPRegBit FPSCR_IDE, " ID"
VFPRegBit FPSCR_IXE, " IX"
VFPRegBit FPSCR_UFE, " UF"
VFPRegBit FPSCR_OFE, " OF"
VFPRegBit FPSCR_DZE, " DZ"
VFPRegBit FPSCR_IOE, " IO"
DCB 253
DCB 254, "V15", 0 ; "Cumulative exceptions:"
VFPRegBit FPSCR_IDC, " ID"
VFPRegBit FPSCR_IXC, " IX"
VFPRegBit FPSCR_UFC, " UF"
VFPRegBit FPSCR_OFC, " OF"
VFPRegBit FPSCR_DZC, " DZ"
VFPRegBit FPSCR_IOC, " IO"
DCB 253
DCB 255
ALIGN
FPEXCList
DCB "FPEXC = ", 0
DCB 254, "V12", 0 ; "Flags:"
VFPRegBit FPEXC_EX, " EX"
VFPRegBit FPEXC_EN, " EN"
VFPRegBit FPEXC_DEX, " DEX"
VFPRegBit FPEXC_FP2V, " FP2V"
VFPRegBit FPEXC_VV, " VV"
VFPRegBit FPEXC_TFV, " TFV"
DCB 253
DCB 255
DCB 254, "V16", 0 ; "Pending/potential exceptions:"
VFPRegBit FPEXC_IDF, " ID"
VFPRegBit FPEXC_IXF, " IX"
VFPRegBit FPEXC_UFF, " UF"
VFPRegBit FPEXC_OFF, " OF"
VFPRegBit FPEXC_DZF, " DZ"
VFPRegBit FPEXC_IOF, " IO"
DCB 253
DCB 255
ALIGN
RMODEList
DCB "V04", 0
DCB "V05", 0
DCB "V06", 0
DCB "V07", 0
ALIGN
fpinst DCB "FPINST = ", 0
ALIGN
fpinst2 DCB "FPINST2 = ", 0
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -5933,14 +6354,12 @@ open_messagefile Entry r0-r2
declareresourcefsfiles
Entry "r0"
ADR R0,resourcefsfiles
BL Resources
SWI XResourceFS_RegisterFiles ; ignore errors
CLRV
EXIT
resourcefsfiles
ResourceFile $MergedMsgs, Resources.Debugger.Messages
DCD 0
IMPORT Resources
]
[ debug
......
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