Commit b364ec48 authored by Robert Sprowson's avatar Robert Sprowson

Add in disassembly of ARMv6 and ARMv7 instruction sets

The debugger had some embryonic ARMv6 knowhow, switched out due to being incomplete.
Enabling and finishing off ARMv6, then adding ARMv6K, ARMv6T2, ARMv6 security extensions, and ARMv7.
That just leaves
 - ARMv7MP (multiprocessor extensions: PLDW)
 - ARMv7VE (virtualisation extensions: ERET, MRS copro, MSR copro)
 - Advanced SIMD (probably worth thinking about)
 - Thumb2 (questionable why Thumb is supported at all as the tools & OS don't use it)
The syntax follows the pre UAL spirit for the new instructions (cf. ADDCCS versus ADDSCC).
Removed binary V6test binary, replaced with more comprehensive v6/v7 source.
Tested softloaded inspecting the output in StrongEd.

Version 1.84. Tagged as 'Debugger-1_84'
parent cc5b363d
; arrive here with cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
; SMLAD/SMUAD etc cccc 0111 0xxx xxxx xxxx xxxx xxx1 xxxx
; USAD8/USADA8 cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx
; SMUAD/SMUSD cccc 0111 0000 dddd nnnn 1111 0sx1 ssss
; SMMUL cccc 0111 0101 dddd nnnn 1111 00r1 ssss
; SMMLA cccc 0111 0101 dddd ssss nnnn 00r1 ssss
; SMLALD cccc 0111 0100 dddd nnnn 1111 0001 ssss
; various cccc 0110 0xxx xooo xxxx xxxx xxx1 xxxx
; ADD/UNPK cccc 0110 1xxx xxxx xxxx xxxx 0111 xxxx
; PKH cccc 0110 1000 xxxx xxxx xxxx xx01 xxxx
; USAT/SSAT cccc 0110 1x1x xxxx xxxx xxxx xx01 xxxx
; USAT16/SSAT16 cccc 0110 1x10 xxxx xxxx xxxx xx11 xxxx
; SEL16/SEL8 cccc 0110 1000 xxxx xxxx xxxx x011 xxxx
; REVxx cccc 0110 1x11 xxxx xxxx xxxx x011 xxxx
; various cccc 0110 0xxx xooo xxxx xxxx xxx1 xxxx
; 0100
; ADD8 1001
; ADD16 0001
; ADDSUBX 0011
; SUB8 1111
; SUB16 0111
; SUBADDX 0101
; undefined 1101
; undefined 1011
; UH 0111
; UQ 0110
; U 0101
; SH 0011
; Q 0010
; S 0001
; REV cccc 0110 1011 1111 dddd 1111 0011 mmmm
; REV16 cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx
; REVSH cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx
; LDREX cccc 0001 1001 nnnn dddd 1111 1001 1111
; STREX cccc 0001 1000 nnnn dddd 1111 1001 mmmm
; SRS 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx
; RFE 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx
; SETEND 1111 0001 0000 xxx1 xxxx xxxx xxxx xxxx
; CPS 1111 0001 0000 xxxx xxxx xxxx xx0x xxxx
From ARMARMv7AR chapter L and A5.
Introduced in
v6 v6K v6T2 v7
; STREX cccc 0001 1000 nnnn dddd 1111 1001 mmmm *
; LDREX 1001 nnnn dddd 1111 1001 1111 *
; STREXD 1010 *
; LDREXD 1011 *
; STREXB 1100 *
; LDREXB 1101 *
; STREXH 1110 *
; LDREXH 1111 *
; NOP cccc 0011 0010 0000 1111 0000 0000 0000 *
; YIELD 0001 *
; WFE 0010 *
; WFI 0011 *
; SEV 0100 *
; DBG 1111 hhhh *
; MOVT cccc 0011 0100 iiii dddd iiii iiii iiii *
; MOVW cccc 0011 0000 iiii dddd iiii iiii iiii *
; STRHT cccc 0000 ur10 1011 *
; LDRHT cccc 0000 ur11 1011 *
; LDRSBT cccc 0000 ur11 1101 *
; LDRSHT cccc 0000 ur11 1111 *
; SMI cccc 0001 0110 0000 0000 0000 0111 iiii *
; UMAAL cccc 0000 0100 hhhh llll ssss 1001 mmmm *
; MLS cccc 0000 0100 dddd aaaa mmmm 1001 nnnn *
; MCRR2 1111
; MRRC2 1111
; SRS 1111 100p u1w0 1101 0000 0101 000m mmmm *
; RFE 1111 100p u0w1 nnnn 0000 1010 0000 0000 *
; CPS 1111 0001 0000 ssc0 0000 000a if0m mmmm *
; SETEND 1111 0001 0000 0001 0000 00e0 0000 0000
; CLREX 1111 0101 0111 1111 1111 0000 0001 1111 *
; DSB 1111 0101 0111 1111 1111 0000 0100 tttt *
; DMB 0101 tttt *
; ISB 0110 tttt *
; PLI(imm) 1111 011h u101 nnnn 1111 rrrr rtt0 mmmm *
; PLI(reg) 1111 010h u101 nnnn 1111 iiii iiii iiii *
; REV/REV16/REVSH cccc 0110 1s11 1111 dddd 1111 h011 mmmm *
; RBIT 1 0 *
; PKH cccc 0110 1000 nnnn dddd iiii it01 mmmm
; SEL cccc 0110 1000 nnnn dddd 1111 1011 mmmm *
; cccc 0110 0xxx nnnn dddd 1111 xxx1 mmmm *
; ADD8 100 *
; ADD16 000 *
; ASX 001 *
; SUB8 111 *
; SUB16 011 *
; SAX 010 *
; UH 111 *
; UQ 110 *
; U 101 *
; SH 011 *
; Q 010 *
; S 001 *
; SMLAD *
; SMUAD *
; SMLSD *
; SMUSD *
; SDIV/UDIV cccc 0111 00u1 dddd 1111 mmmm 0001 nnnn *
; SMLALD cccc 0111 0100 dddd nnnn 1111 0001 ssss *
; SMLSLD *
; SMMLA cccc 0111 0101 dddd ssss nnnn 00r1 ssss *
; SMMLA *
; SMMUL *
; SMMLS *
; USAD8,USADA8 cccc 0111 1000 dddd nnnn ssss 0001 mmmm *
; BFI cccc 0111 110m mmmm dddd llll l001 nnnn *
; BFC 1111 *
; SBFX cccc 0111 101w wwww dddd llll l101 nnnn *
; UBFX 1 *
; USAT cccc 0110 1u1b bbbb dddd iiii ith1 nnnn *
; USAT16 1111 00 *
; SSAT cccc 0110 1u1b bbbb dddd iiii ith1 nnnn *
; SSAT16 1111 00 *
; UXTB16,UXTAB16 cccc 0110 11ww nnnn dddd rr00 0111 mmmm *
; UXTB,UXTAB 1 *
; UXTH,UXTAH 1 *
; SXTB16,SXTAB16 0 *
; SXTB,SXTAB 0 *
; SXTH,SXTAH 0 *
......@@ -28,9 +28,13 @@ M63:*** RdHi=Rm
M64:*** Rn in list
M66:*** Rd=Rm
M67:*** Only 1 reg on SA-1 rev 2
M49:*** Odd base of pair
M68:ARMv5 or later
M69:ARMv5TE or later
M70:ARMv6 or later
M71:ARMv6K or later
M72:ARMv6T2 or later
M73:ARMv7 or later
M16:Store initialised to &
M17:Register dump (stored at &
M18:) is:
......
; Copyright 2013 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Services
AREA test,CODE,READONLY
; Synchronisation primitives
LDREXB r0, [r1]
LDREXH r0, [r1]
LDREX r0, [r1]
LDREXD r0, r1, [r2]
LDREXBNE r0, [r1]
LDREXHNE r0, [r1]
LDREXNE r0, [r1]
LDREXDNE r0, r1, [r2]
DCI &E1B25F9F ; LDREXD odd reg, unpredictable
STREX r0, r1, [r2]
STREX r0, r0, [r2] ; Unpredictable
STREX r0, r1, [r0] ; Unpredictable
STREX pc, r1, [r2] ; Unpredictable
DCI &E1A20F95 ; STREXD odd reg, unpredictable
STREXD r0, r14, r15, [r2] ; Target PC, unpredictable
; Hints
DCI &E320F000 ; NOP
DCI &2320F000 ; NOPCS
YIELD
YIELDCS
WFE
WFECS
WFI
WFICS
SEV
SEVCS
DBG 7
DBGCS 7
DCI &E320F900 ; NOP but with nonzero SBZ, undefined
DCI &E320F0EE ; Unallocated hint, unpredictable NOP
; Move immediate 16b
MOVW r5, #&DEAD
MOVT r5, #&BEEF
; Multiply extensions
UMAAL r0, r1, r2, r3
UMAALHI r0, r1, r2, r3
UMAAL r0, r1, pc, r3 ; Unpredictable
UMAAL r1, r1, r2, r3 ; Clash RdLo RdHi
MLS r0, r1, r2, r3
MLSHI r0, r1, r2, r3
MLS r0, r1, pc, r3 ; Unpredictable
; User mode load/store
LDRCCT r1, [r2], r3
LDRT r1, [r2], #-4
LDRHTCC r1, [r2], r3 ; UAL only, cond last
LDRHT r1, [r2], #-2
LDRCCBT r1, [r2], r3
LDRBT r1, [r2], #-1
LDRSHTCC r1, [r2], r3 ; UAL only, cond last
LDRSHT r1, [r2], #-2
LDRSBTCC r1, [r2], r3 ; UAL only, cond last
LDRSBT r1, [r2], #1
STRT r1, [r2]
STRHT r1, [r2]
STRBT r1, [r2]
; Secure extensions
SMC 7
SMCHI 7
MCRR p7, 0, r3, r4, c5
MCRRNV p7, 0, r3, r4, c5 ; MCRR2
MRRC p7, 0, r3, r4, c5
MRRCNV p7, 0, r3, r4, c5 ; MRRC2
; Exception entry and exit
SRSDA SP!, #3
SRSDB SP, #3
SRSIA SP!, #3
SRSIB SP, #3
DCI &F9CE0503 ; Not SP, undefined
RFEDA R15! ; Not PC
RFEDB R0
RFEIA R0!
RFEIB R0
; Misc instructions
CPSID i
CPSIE f
CPSID aif,#12
CPS 12
DCI &F100000C ; Mode != 0, no mode change bit, unpredictable
SETEND BE
CLREX
DSB ISHST
DMB OSH
DMB ST
ISB SY
DCI &F57FF050 ; DMB 0, as SY but unpredictable
DCI &F57FF063 ; ISB OSH, as SY but unpredictable
DCI &F57FF000 ; Unallocated, unpredictable
10
PLD %BT10
PLD [R1, #-1000]
PLD [R1, R2]
DCI &F45FF014 ; Objasm 4.01 bug, this is "PLI %BT10"
PLI [R1, #-1000]
PLI [R1, R2]
; Parallel add/sub signed/unsigned
SADD16CC r0, r1, r2 ; Check for spill into next column
SADD8CC r0, r1, r2
SASXCC r0, r1, r2
SADD16 r0, r1, r2
SADD8 r0, r1, r2
SASX r0, r1, r2
SSUB16 r0, r1, r2
SSUB8 r0, r1, r2
SSAX r0, r1, r2
QADD16 r0, r1, r2
QADD8 r0, r1, r2
QASX r0, r1, r2
QSUB16 r0, r1, r2
QSUB8 r0, r1, r2
QSAX r0, r1, r2
SHADD16 r0, r1, r2
SHADD8 r0, r1, r2
SHASX r0, r1, r2
SHSUB16 r0, r1, r2
SHSUB8 r0, r1, r2
SHSAX r0, r1, r2
UADD16 r0, r1, r2
UADD8 r0, r1, r2
UASX r0, r1, r2
USUB16 r0, r1, r2
USUB8 r0, r1, r2
USAX r0, r1, r2
UQADD16 r0, r1, r2
UQADD8 r0, r1, r2
UQASX r0, r1, r2
UQSUB16 r0, r1, r2
UQSUB8 r0, r1, r2
UQSAX r0, r1, r2
UHADD16 r0, r1, r2
UHADD8 r0, r1, r2
UHASX r0, r1, r2
UHSUB16 r0, r1, r2
UHSUB8 r0, r1, r2
UHSAX r0, r1, r2
; Signed multiply and divide
SMLAD r0, r1, r2, r3
SMLADXCS r0, r1, r2, r3
SMUAD r0, r1, r2
SMUADXCS r0, r1, r2
SMLSD r0, r1, r2, r3
SMLSDXCS r0, r1, r2, r3
SMUSD r0, r1, r2
SMUSDXCS r0, r1, r2
DCI &E715F716 ; SDIV r5, r6, r7
DCI &E735F716 ; UDIV r5, r6, r7
SMLALD r0, r1, r2, r3
SMLALDCS r0, r1, r2, r3
SMLSLD r0, r1, r2, r3
SMLSLDCS r0, r1, r2, r3
SMMLA r0, r1, r2, r3
SMMLARCS r0, r1, r2, r3
SMMUL r0, r1, r2
SMMULRCS r0, r1, r2
SMMLS r0, r1, r2, r3
SMMLSRCS r0, r1, r2, r3
; Sum abs diffs
USAD8 r2, r3, r4
USADA8 r2, r3, r4, r5
USADA8CC r2, r3, r4, r5
; Media extensions
SEL r5, r6, r7
SELCC r5, PC, r7 ; Not PC
REV r0, r1
REV16 r0, r1
REVSH r0, r1
REVSHCC r0, pc ; Not PC
UBFX r5, r6, #12, #19
UBFXCS r5, r6, #0, #32
SBFX r5, PC, #12, #19 ; Not PC
SBFXCS r5, r6, #19, #9
BFI r5, r6, #9, #19
BFI pc, r6, #9, #19 ; PC target unpredictable
BFCCS r5, #9, #21
REV r1,r2
REV16 r1,r2
REVSHCC r1,r2
RBIT r1,r2
RBIT r1,PC ; Not PC
PKHBT r0, r1, r2
PKHBTCC r0, r1, r2, LSL #31
PKHTB r0, r2, r1 ; Maps to PKHBT r0, r1, r2
PKHTB r0, r1, PC, ASR #1 ; Not PC
PKHTBCC r0, r1, r2, ASR #32
USAT r6, #7, r8
SSAT r6, #7, r8, ASR #32
USAT r6, #7, PC, LSL #5 ; Not PC
USAT16NE r6, #7, r8
UXTB r0, r1
UXTAB r0, r1, r2
SXTBCC r0, r1, ROR #8
SXTABCC r0, r1, r2, ROR #16
UXTH r0, r1
UXTAH r0, r1, r2
UXTB16 r0, PC ; Not PC
UXTAB16CC r0, r1, r2, ROR #24
END
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.83"
Module_Version SETA 183
Module_MajorVersion SETS "1.84"
Module_Version SETA 184
Module_MinorVersion SETS ""
Module_Date SETS "24 Sep 2011"
Module_ApplicationDate SETS "24-Sep-11"
Module_Date SETS "19 Oct 2013"
Module_ApplicationDate SETS "19-Oct-13"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "castle/RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.83"
Module_HelpVersion SETS "1.83 (24 Sep 2011)"
Module_FullVersion SETS "1.84"
Module_HelpVersion SETS "1.84 (19 Oct 2013)"
END
/* (1.83)
/* (1.84)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.83
#define Module_MajorVersion_CMHG 1.84
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 24 Sep 2011
#define Module_Date_CMHG 19 Oct 2013
#define Module_MajorVersion "1.83"
#define Module_Version 183
#define Module_MajorVersion "1.84"
#define Module_Version 184
#define Module_MinorVersion ""
#define Module_Date "24 Sep 2011"
#define Module_Date "19 Oct 2013"
#define Module_ApplicationDate "24-Sep-11"
#define Module_ApplicationDate "19-Oct-13"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.83"
#define Module_HelpVersion "1.83 (24 Sep 2011)"
#define Module_LibraryVersionInfo "1:83"
#define Module_FullVersion "1.84"
#define Module_HelpVersion "1.84 (19 Oct 2013)"
#define Module_LibraryVersionInfo "1:84"
This diff is collapsed.
......@@ -242,6 +242,7 @@
GET Hdr:MsgTrans
GET Hdr:FPEmulator
GET Hdr:ResourceFS
GET Hdr:OsBytes
GET Hdr:CPU.FPA
GET Hdr:CPU.Arch
GET Hdr:OSRSI6
......@@ -253,35 +254,46 @@
GET Hdr:Debug
GBLL debug
debug SETL False
GBLL national
national SETL False
debug SETL {FALSE}
GBLL StrongARM
StrongARM SETL True
StrongARM SETL {TRUE}
GBLL WarnSArev2
WarnSArev2 SETL False ; Warn about hitting the SA revision 2 STM^ bug
WarnSArev2 SETL {FALSE} ; Warn about hitting the SA revision 2 STM^ bug
GBLL WarnARMv5
WarnARMv5 SETL True ; Indicate ARMv5 or later instructions
WarnARMv5 SETL {TRUE} ; Indicate ARMv5 or later instructions
GBLL WarnARMv5E
WarnARMv5E SETL True
WarnARMv5E SETL {TRUE} ; Indicate ARMv5E or later instructions
GBLL WarnARMv6
WarnARMv6 SETL True ; Indicate ARMv6 or later instructions
WarnARMv6 SETL {TRUE} ; Indicate ARMv6 or later instructions
GBLL WarnARMv6K
WarnARMv6K SETL {TRUE} ; Indicate ARMv6K or later instructions
GBLL WarnARMv6T2
WarnARMv6T2 SETL {TRUE} ; Indicate ARMv6T2 or later instructions
GBLL ARMv6
ARMv6 SETL False ; Don't do ARMv6 yet until complete
GBLL WarnARMv7
WarnARMv7 SETL {TRUE} ; Indicate ARMv7 or later instructions
GBLL Thumbv6
Thumbv6 SETL {TRUE} ; Don't do Thumbv6 yet until complete
GBLL CirrusDSP
CirrusDSP SETL False
CirrusDSP SETL {FALSE}
[ :LNOT: :DEF: international_help
GBLL international_help
international_help SETL {TRUE} ; Default to RISC OS 3.60+ internationalisation
]
[ :LNOT: :DEF: standalone
GBLL standalone
standalone SETL False
standalone SETL {FALSE}
]
......@@ -392,6 +404,10 @@ Mistake_STMHat # 1
Mistake_ARMv5 # 1
Mistake_ARMv5E # 1
Mistake_ARMv6 # 1
Mistake_ARMv6K # 1
Mistake_ARMv6T2 # 1
Mistake_ARMv7 # 1
Mistake_BaseOdd # 1
^ -1
Potential_SWICDP # -1
......@@ -512,7 +528,7 @@ Module_BaseAddr
DCD Debug_SWI_Code - Module_BaseAddr
DCD Debug_SWI_Name - Module_BaseAddr
DCD 0
[ International_Help <> 0
[ international_help
DCD message_filename - Module_BaseAddr
|
DCD 0
......@@ -769,35 +785,24 @@ Debug_Die Entry
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; (No. of Parameters)
Debug_HC_Table ; Name Max Min Flags
Debug_HC_Table ; Name Max Min
[ national
Command BreakClr, 1, 0,
Command BreakList, 0, 0,
Command BreakSet, 1, 1,
Command Continue, 0, 0,
Command Debug, 0, 0,
Command InitStore, 1, 0,
Command Memory, 5, 1,; P B R + R
Command MemoryA, 4, 1,; P B R V
Command MemoryI, 7, 1,; P T A +/- B + C
Command ShowRegs, 0, 0,
Command ShowFPRegs, 0, 0,
|
Command BreakClr, 1, 0, International_Help
Command BreakList, 0, 0, International_Help
Command BreakSet, 1, 1, International_Help
Command Continue, 0, 0, International_Help
Command Debug, 0, 0, International_Help
Command InitStore, 1, 0, International_Help
Command Memory, 5, 1, International_Help ; P B R + R
Command MemoryA, 4, 1, International_Help ; P B R V
Command MemoryI, 7, 1, International_Help ; P T A +/- B + C
Command ShowRegs, 0, 0, International_Help
Command ShowFPRegs, 0, 0, International_Help
]
[ international_help
ihflag * International_Help
|
ihflag * 0
]
Command BreakClr, 1, 0, ihflag
Command BreakList, 0, 0, ihflag
Command BreakSet, 1, 1, ihflag
Command Continue, 0, 0, ihflag
Command Debug, 0, 0, ihflag
Command InitStore, 1, 0, ihflag
Command Memory, 5, 1, ihflag ; P B R + R
Command MemoryA, 4, 1, ihflag ; P B R V
Command MemoryI, 7, 1, ihflag ; P T A +/- B + C
Command ShowRegs, 0, 0, ihflag
Command ShowFPRegs, 0, 0, ihflag
DCB 0 ; end of table
GET TokHelpSrc
......@@ -888,7 +893,7 @@ Instruction Entry "r0, r3-r9"
ADR r0, StringBuffer ; Always build into temp buffer
[ debug :LAND: True
[ debug
MOV r14, #0 ; zap buffer
MOV r3, #?StringBuffer-4
00 STR r14, [r0, r3]
......@@ -1147,29 +1152,32 @@ W_Back DCB "!,{", 0
; rrrr = register list
LdmStm ROUT
CMP R4, #2_1111:SHL:28 ; 'NV' condition code
BCS Srs_Or_Rfe ; means something else
ANDS R5, R4, #&7F00
BLNE checkreg ;error if R8-R14 in list
BLNE checkreg ; error if R8-R14 in list
;test for silly conditions - ldm/stm ! and ^ with R15 not in list is bad,
;and LDM ^ with R15 not in the list is a deferred bank error
TestBit 15
BNE notbad ;R15 in list
BNE notbad ; R15 in list
TestBit 22
BEQ notbad ;not forcing user
BEQ notbad ; not forcing user
;case 1 - ! too
TestBit 21
MOVNE r10, #Mistake_PlingHat
STRNE r10, Mistake
BNE notbad2 ;don't bother with next test
BNE notbad2 ; don't bother with next test
;case 2 - LDM
TestBit 20
MOVNE r10,#Potential_Banked_Next
STRNE r10,Mistake
BNE notbad2 ; don't bother with next test
BNE notbad2 ; don't bother with next test
notbad
;case 3 - Rn in list with writeback
......@@ -1181,9 +1189,9 @@ notbad
MOV r14, r14, LSL r10
TSTS r4, r14
BEQ notbad3
TestBit 20 ; If it's an STM
TestBit 20 ; If it's an STM
SUBEQ r14, r14, #1
TSTEQS r4, r14 ; and Rn is lowest in list, then it's okay
TSTEQS r4, r14 ; and Rn is lowest in list, then it's okay
MOVNE r10,#Mistake_Rninlist
STRNE r10,Mistake
BNE notbad2
......@@ -1328,11 +1336,7 @@ LdrStr ROUT
; both LDR and PLD.
TST r4, #1 :SHL: 25 ; If Rm and shift and trying Rs
TSTNE r4, #1 :SHL: 4 ; then that was xxR Rd,[Rn,Rm,SHF Rs]
[ ARMv6
BNE UndefinedExtension ; but ARM2 doesn't do that anymore
|
BNE Undefined ; but ARM2 doesn't do that anymore
]
MOV r14, r4, LSR #28
TEQ r14, #15
......@@ -1488,37 +1492,62 @@ CPDT_info
B %BT80
Ldr DCB "LDR", 0
Str DCB "STR", 0
Open_B DCB ",[", 0
Close_B DCB "],", 0
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Preload ROUT
; Preload
; arrive here with 1111 01xx xxxx xxxx xxxx xxxx xxxx xxxx
; format is 1111 0101 u101 nnnn 1111 iiii iiii iiii
; or 1111 0111 u101 nnnn 1111 rrrr rtt0 mmmm
; format is 1111 010h u101 nnnn 1111 iiii iiii iiii
; or 1111 011h u101 nnnn 1111 rrrr rtt0 mmmm
;
; PLD [Rn,#offset]
; [Rn,{+|-}Rm{,shift}]
; PL<D|I> [Rn,#offset]
; [Rn,{+|-}Rm{,shift}]
;
; where u = Up/~Down
; where h = PLD/~PLI hint
; u = Up/~Down
; nnnn = Rn
; rrrrr = shift amount
; tt = shift type (LSL, LSR, ASR or ROR)
; mmmm = Rm
; iiii = 12-bit unsigned immediate offset
LDR r14, =&F57FF0 ; Bits 8-31 of a group of 16 unconditionals
TEQ r14, r4, LSR #8
BEQ Maintenance_uncond
[ WarnARMv5E :LOR: WarnARMv7
TestBit 24
[ WarnARMv5E
MOV r14, #Mistake_ARMv5E
STR r14, Mistake
MOVNE r14, #Mistake_ARMv5E
|
MOVNE r14, #0
]
[ WarnARMv7
MOVEQ r14, #Mistake_ARMv7
|
MOVEQ r14, #0
]
STR r14, Mistake
]
AddStr Pld
AddStr Pload
TestBit 24, "D", "I"
BL Tab
AND r5, r4, #2_10111:SHL:20
TEQ r5, #2_10101:SHL:20
TEQNE r5, #2_00101:SHL:20 ; PLI
ORREQ r4, r4, #1:SHL:24 ; Sidestep PC writeback warning
ANDEQ r5, r4, #2_1111:SHL:12
TEQEQ r5, #2_1111:SHL:12
BEQ DataTransfer_Common_NoComma
B Undefined
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Mull DCB "MULL",0
......@@ -1528,11 +1557,7 @@ Mlal DCB "MLAL",0
Mul DCB "MUL", 0
Mla DCB "MLA", 0
aswp DCB "SWP", 0
Ldr DCB "LDR", 0
Str DCB "STR", 0
Open_B DCB ",[", 0
Close_B DCB "],", 0
Pld DCB "PLD", 0
Pload DCB "PL", 0
UndefinedDataProcessing ROUT
; Arrive here with cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx
......@@ -1547,13 +1572,13 @@ ArithmeticExtension
CMP R5,#2_1000:SHL:20
BHS mul_long ; opcode 8-15 = long multiply
CMP R5,#2_0110:SHL:20