Commit 2a735e83 authored by Steve Revill's avatar Steve Revill
Browse files

* Added a couple of tweaks to the MakeMess and MkClean files.

  * Added the Disassemble$Options system variable.
Detail:
  * MakeMess now does a CDir command (in case you run it before
    running MkRom). MkClean now includes a 'stripdepnd' call.

  * There is a new system (code) variable created on module init
    called Disassemble$Options. This controls (at the moment)
    register naming for disassembly.
Admin:
  Tested on RiscOS 4 and 3.70.

Version 1.72. Tagged as 'Debugger-1_72'
parent 5f87c9e2
......@@ -15,5 +15,6 @@
Dir <Obey$Dir>
Copy LocalRes:Messages Resources.<Locale>.CombMsgs ~C~V
Print LocalRes:CmdHelp { >> Resources.<Locale>.CombMsgs }
CDir rm
ModGen rm.DbgMess DebuggerMessages "Debugger Msgs" 0.01 Resources.<Locale>.CombMsgs Resources.Debugger.Messages
Remove Resources.<Locale>.CombMsgs
......@@ -14,3 +14,4 @@
|
Dir <Obey$Dir>
amu_machine clean
stripdepnd
......@@ -11,14 +11,14 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.71"
Module_Version SETA 171
Module_MajorVersion SETS "1.72"
Module_Version SETA 172
Module_MinorVersion SETS ""
Module_Date SETS "18 Apr 2001"
Module_ApplicationDate2 SETS "18-Apr-01"
Module_ApplicationDate4 SETS "18-Apr-2001"
Module_Date SETS "30 Apr 2001"
Module_ApplicationDate2 SETS "30-Apr-01"
Module_ApplicationDate4 SETS "30-Apr-2001"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.71"
Module_HelpVersion SETS "1.71 (18 Apr 2001)"
Module_FullVersion SETS "1.72"
Module_HelpVersion SETS "1.72 (30 Apr 2001)"
END
/* (1.71)
/* (1.72)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 1.71
#define Module_MajorVersion_CMHG 1.72
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 18 Apr 2001
#define Module_Date_CMHG 30 Apr 2001
#define Module_MajorVersion "1.71"
#define Module_Version 171
#define Module_MajorVersion "1.72"
#define Module_Version 172
#define Module_MinorVersion ""
#define Module_Date "18 Apr 2001"
#define Module_Date "30 Apr 2001"
#define Module_ApplicationDate2 "18-Apr-01"
#define Module_ApplicationDate4 "18-Apr-2001"
#define Module_ApplicationDate2 "30-Apr-01"
#define Module_ApplicationDate4 "30-Apr-2001"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.71"
#define Module_HelpVersion "1.71 (18 Apr 2001)"
#define Module_FullVersion "1.72"
#define Module_HelpVersion "1.72 (30 Apr 2001)"
; Copyright 2001 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; File: CodeVar.s
; Purpose: Manage a code variable for providing different disassembly modes.
; Author: S A Revill
; History: 28-Apr-2001: SAR: created
;
; Routine to create our 'Disassemble$Options' code variable. This would only
; normally be called from module initialisation.
;
; In...
; R12 = private word *value*
; Out...
; R11 = corrupted
; R12 = preserved
;
create_codevar
Entry "R0-R4"
; Copy our code variable handler code into an RMA block
MOV R0, #ModHandReason_Claim
LDR R3, codesize
SWI XOS_Module
BVS %FT01
MOV R11, R2 ; Preserve claimed block in R11
ADR R0, codevar_code
ADRL R1, codevar_end
00 LDR R14, [R0], #4
STR R14, [R2], #4
CMP R0, R1
BLO %BT00
; Patch our workspace pointer into the appropriate word of the copied code
STR R12, [R11, #wkspc - codevar_code]
; Patch a pointer to the register name string table
ADR R0, reg_labels
STR R0, [R11, #lblptr - codevar_code]
; Create the code variable
ADR R0, sysvar
MOV R1, R11
LDR R2, codesize
MOV R3, #0
MOV R4, #&10
SWI XOS_SetVarVal ; Copies our code (copy) into the system heap
; Free the RMA block
MOV R2, R11
MOVVC R11, #0 ; If OS_SetVarVal returned an error, record
MOVVS R11, R0 ; the error block pointer in R11.
MOV R0, #ModHandReason_Free
SWI XOS_Module
TEQ R11, #0
MOVNE R0, R11
SETV NE
01 ; Can't put EXIT macro on a 'nn' format label!
EXIT
;
; Routine to destroy our 'Disassemble$Options' code variable. This would only
; normally be called from module finalisation.
;
; In...
; Don't care
; Out...
; All preserved (except LR of course!)
;
destroy_codevar
Entry "R0-R4"
ADR R0, sysvar
MOV R1, #0
MOV R2, #-1
MOV R3, #0
MOV R4, #&10
SWI XOS_SetVarVal
CLRV
EXIT
sysvar DCB "Disassemble$Options", 0
ALIGN
codesize
DCD codevar_end - codevar_code
;
; The simplest way to initialise the register label pointers is to set the
; system variable for the debugger options to some default value.
;
init_codevar
Entry "R0-R4"
ADR R0, initstr
SWI XOS_CLI
EXIT
initstr DCB "Set Disassemble$Options -arm", 0
ALIGN
; Standard ARM register labels...
reg_labels
reg_R0 DCB "R0", 0, 0
reg_R1 DCB "R1", 0, 0
reg_R2 DCB "R2", 0, 0
reg_R3 DCB "R3", 0, 0
reg_R4 DCB "R4", 0, 0
reg_R5 DCB "R5", 0, 0
reg_R6 DCB "R6", 0, 0
reg_R7 DCB "R7", 0, 0
reg_R8 DCB "R8", 0, 0
reg_R9 DCB "R9", 0, 0
reg_R10 DCB "R10", 0
reg_R11 DCB "R11", 0
reg_R12 DCB "R12", 0
reg_R13 DCB "R13", 0
reg_R14 DCB "R14", 0
reg_PC DCB "PC", 0, 0
; Alternative ARM register labels...
reg_SP DCB "SP", 0, 0
reg_LR DCB "LR", 0, 0
; Standard APCS register labels...
reg_a1 DCB "a1", 0, 0
reg_a2 DCB "a2", 0, 0
reg_a3 DCB "a3", 0, 0
reg_a4 DCB "a4", 0, 0
reg_v1 DCB "v1", 0, 0
reg_v2 DCB "v2", 0, 0
reg_v3 DCB "v3", 0, 0
reg_v4 DCB "v4", 0, 0
reg_v5 DCB "v5", 0, 0
reg_v6 DCB "v6", 0, 0
reg_v7 DCB "v7", 0, 0
reg_v8 DCB "v8", 0, 0
reg_ip DCB "ip", 0, 0
reg_sp DCB "sp", 0, 0
reg_lr DCB "lr", 0, 0
reg_pc DCB "pc", 0, 0
; Alternative APCS register labels...
reg_sb DCB "sb", 0, 0
reg_sl DCB "sl", 0, 0
reg_fp DCB "fp", 0, 0
; ****************************************************************************************
; *
; * This code implements the OS_ReadVarVal and OS_SetVarVal functionality for
; * our 'Disassemble$Options' system variable. It also contains some writable
; * buffers. It is designed to be relocatable.
; *
codevar_code
B codevar_write
;
; Entry point for a read from our code variable (i.e. *Show or OS_ReadVarVal).
;
; In...
; Don't care
; Out...
; R0 - value
; R1 - corrupted
; R2 - length
; R10 - corrupted
; R11 - corrupted
; R12 - corrupted
;
codevar_read
Entry
LDR R12, wkspc
; Convert the flags into a string
ADR R0, codevar_value
LDR R12, DisOpts
TST R12, #DisOpt_APCS
BNE %FT00
; Write "-arm"...
MOV R1, #"-"
ORR R1, R1, #"a" :SHL: 8
ORR R1, R1, #"r" :SHL: 16
ORR R1, R1, #"m" :SHL: 24
STR R1, [R0], #4
; Write " -SP" or " -R13"...
TST R12, #DisOpt_sp
AddChar " "
AddChar "-"
AddChar "S", NE
AddChar "P", NE
AddChar "R", EQ
AddChar "1", EQ
AddChar "3", EQ
; Write " -LR" or " -R14"...
TST R12, #DisOpt_lr
AddChar " "
AddChar "-"
AddChar "L", NE
AddChar "R"
AddChar "1", EQ
AddChar "4", EQ
MOV R1, #0
STRB R1, [R0]
ADR R1, codevar_value
SUB R2, R0, R1 ; String length (exclude terminator)
MOV R0, R1 ; String pointer
EXIT
00 ; Write "-apcs"...
MOV R10, #"-"
ORR R10, R10, #"a" :SHL: 8
ORR R10, R10, #"p" :SHL: 16
ORR R10, R10, #"c" :SHL: 24
STR R10, [R0], #4
AddChar "s"
; Write " -v6" or " -sb"...
TST R12, #DisOpt_v6
AddChar " "
AddChar "-"
AddChar "v", NE
AddChar "6", NE
AddChar "s", EQ
AddChar "b", EQ
; Write " -v7" or " -sl"...
TST R12, #DisOpt_v7
AddChar " "
AddChar "-"
AddChar "v", NE
AddChar "7", NE
AddChar "s", EQ
AddChar "l", EQ
; Write " -v8" or " -fp"...
TST R12, #DisOpt_v8
AddChar " "
AddChar "-"
AddChar "v", NE
AddChar "8", NE
AddChar "f", EQ
AddChar "p", EQ
; Write " -sp -lr"...
AddChar " "
AddChar "-"
AddChar "s"
AddChar "p"
AddChar " "
AddChar "-"
AddChar "l"
AddChar "r"
MOV R1, #0
STRB R1, [R0]
ADR R1, codevar_value
SUB R2, R0, R1 ; String length (exclude terminator)
MOV R0, R1 ; String pointer
EXIT
;
; Debugger module's workspace pointer (NOT private word pointer!)
;
wkspc DCD &1BFFFB0 ; <- a value which is likely to abort if we've screwed-up
;
; A pointer to the base of the register label name table
;
lblptr DCD &1BFFFB0
;
; A buffer for the output string. MUST be as long as the longest possible!
;
codevar_value
DCB "-apcs -v6 -v7 -v8 -sp -lr", 0
ALIGN
;
; Entry point for a write to our code variable (i.e. *Set or OS_SetVarVal).
;
; In...
; R1 - value (string pointer)
; R2 - length
; Out...
; R1 - corrupted
; R2 - corrupted
; R4 - corrupted
; Side-effects...
; The label name string pointers, and the disassembly flags word in our
; workspace may be altered by this routine.
;
codevar_write
Entry "R0, R3, R9, R10-R12"
LDR R12, wkspc
LDR R9, lblptr
ADR R0, syn_str
ADR R2, sw_arm
MOV R3, #argbufend - argbuf
SWI XOS_ReadArgs
BVS %FT04
; APCS or ARM mode?
LDR R1, sw_apcs
LDR R11, [R12, #:INDEX: DisOpts]
TEQ R1, #0
BNE %FT02
; Prefix register numbers with an upper-case character...
MOV R10, #"F"
STRB R10, [R12, #:INDEX: DisReg_F]
MOV R10, #"C"
STRB R10, [R12, #:INDEX: DisReg_C]
; ARM mode - doesn't allow v6, v7 or v8
BIC R11, R11, #DisOpt_APCS :OR: DisOpt_v6 :OR: DisOpt_v7 :OR: DisOpt_v8
; Initialise the constant ARM mode register labels (R0-R12, PC)...
ADD R10, R9, #reg_R0 - reg_labels
ADD R3, R12, #:INDEX: DisRegLabels
ADD R0, R3, #13*4
00 STR R10, [R3], #4
ADD R10, R10, #4
CMP R3, R0
BLO %BT00
ADD R10, R9, #reg_PC - reg_labels
STR R10, [R12, #:INDEX: DisReg_R15]
; SP or R13?
LDR R1, sw_sp
TEQ R1, #0
ADDNE R10, R9, #reg_SP - reg_labels
ADDEQ R10, R9, #reg_R13 - reg_labels
STR R10, [R12, #:INDEX: DisReg_R13]
ORRNE R11, R11, #DisOpt_sp
BICEQ R11, R11, #DisOpt_sp
; LR or R14?
LDR R1, sw_lr
TEQ R1, #0
ADDNE R10, R9, #reg_LR - reg_labels
ADDEQ R10, R9, #reg_R14 - reg_labels
STR R10, [R12, #:INDEX: DisReg_R14]
ORRNE R11, R11, #DisOpt_lr
BICEQ R11, R11, #DisOpt_lr
; Store the flags word back into the module workspace
STR R11, [R12, #:INDEX: DisOpts]
EXIT
02 ; APCS mode - doesn't allow R13 or R14...
ORR R11, R11, #DisOpt_APCS :OR: DisOpt_sp :OR: DisOpt_lr
; Prefix register numbers with a lower-case character...
MOV R10, #"f"
STRB R10, [R12, #:INDEX: DisReg_F]
MOV R10, #"c"
STRB R10, [R12, #:INDEX: DisReg_C]
; Initialise the constant APCS mode register labels (a1-v5, ip, sp, lr, pc)...
ADD R10, R9, #reg_a1 - reg_labels
ADD R3, R12, #:INDEX: DisRegLabels
ADD R0, R3, #9*4
03 STR R10, [R3], #4
ADD R10, R10, #4
CMP R3, R0
BLO %BT03
ADD R10, R9, #reg_ip - reg_labels
STR R10, [R12, #:INDEX: DisReg_R12]
ADD R10, R9, #reg_sp - reg_labels
STR R10, [R12, #:INDEX: DisReg_R13]
ADD R10, R9, #reg_lr - reg_labels
STR R10, [R12, #:INDEX: DisReg_R14]
ADD R10, R9, #reg_pc - reg_labels
STR R10, [R12, #:INDEX: DisReg_R15]
; v6 or sb?
LDR R1, sw_v6
TEQ R1, #0
ADDNE R10, R9, #reg_v6 - reg_labels
ADDEQ R10, R9, #reg_sb - reg_labels
STR R10, [R12, #:INDEX: DisReg_R9]
ORRNE R11, R11, #DisOpt_v6
LDR R1, sw_v7
BICEQ R11, R11, #DisOpt_v6
; v7 or sl?
TEQ R1, #0
ADDNE R10, R9, #reg_v7 - reg_labels
ADDEQ R10, R9, #reg_sl - reg_labels
STR R10, [R12, #:INDEX: DisReg_R10]
ORRNE R11, R11, #DisOpt_v7
LDR R1, sw_v8
BICEQ R11, R11, #DisOpt_v7
; v8 or fp?
TEQ R1, #0
ADDNE R10, R9, #reg_v8 - reg_labels
ADDEQ R10, R9, #reg_fp - reg_labels
STR R10, [R12, #:INDEX: DisReg_R11]
ORRNE R11, R11, #DisOpt_v8
BICEQ R11, R11, #DisOpt_v8
; Store the flags word back into the module workspace
STR R11, [R12, #:INDEX: DisOpts]
EXIT
04 LDMFD SP !, {R0, R3, R9, R10-R12, LR}
ADR R0, syn_err
MOV PC, LR
;
; Syntax string OS_ReadArgs. Note: we only expect switches to be
; passed into the write code. Anything not in this string will
; generate an error (i.e. *Set will return an error).
;
syn_str DCB "arm/S,apcs/S,sb/S,v6/S,sl/S,v7/S,fp/S,v8/S,r13/S,sp/S,r14/S,lr/S", 0
ALIGN
syn_err DCD &1EA
DCB "Valid options are: [-arm | -apcs] [-sb | -v6] "
DCB "[-sl | -v7] [-fp | -v8] [-r13 | -sp] [-r14 | -lr]", 0
;
; Buffer for OS_ReadArgs. Any given word will be non-zero if the
; corresponding switch was present in the value on entry to the
; write code.
;
argbuf
sw_arm DCD 0 ; -arm \__ DisOpt_APCS
sw_apcs DCD 0 ; -apcs /
sw_sb DCD 0 ; -sb \__ DisOpt_v6
sw_v6 DCD 0 ; -v6 /
sw_sl DCD 0 ; -sl \__ DisOpt_v7
sw_v7 DCD 0 ; -v7 /
sw_fp DCD 0 ; -fp \__ DisOpt_v8
sw_v8 DCD 0 ; -v8 /
sw_r13 DCD 0 ; -r13 \__ DisOpt_sp
sw_sp DCD 0 ; -sp /
sw_r14 DCD 0 ; -r14 \__ DisOpt_lr
sw_lr DCD 0 ; -lr /
argbufend
codevar_end
; *
; * This is the end of the 'Disassemble$Options' code variable stuff.
; *
; ****************************************************************************************
END
......@@ -211,6 +211,9 @@
; ARM documentation.
; 1.71 KJB 18-Apr-01 Fixed and tidied *ShowFPRegs - in particular will work
; correctly with 26-bit FPEmulators.
; 1.72 SAR 28-Apr-01 Introduced the Disassemble$Options code variable to control
; various alternatives for disassembly. In particular, the
; register name output can now be in APCS mode(s).
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -307,6 +310,36 @@ MessageFile_Open # 4 ; Opened message file flag
SysIs32bit # 1 ; non-zero if on a 32-bit system
# 3
; SAR
DisOpts # 4 ; Disassembler options
DisOpt_APCS * 2_1 ; Use APCS register names (when set)
DisOpt_v6 * 2_10 ; Use 'v6' rather than 'sb'
DisOpt_v7 * 2_100 ; Use 'v7' rather than 'sl'
DisOpt_v8 * 2_1000 ; Use 'v8' rather than 'fp'
DisOpt_sp * 2_10000 ; Use 'SP' rather than 'R13'
DisOpt_lr * 2_100000 ; Use 'LR' rather than 'R14'
DisRegLabels * @ ; Pointers to register name strings
DisReg_R0 # 4
DisReg_R1 # 4
DisReg_R2 # 4
DisReg_R3 # 4
DisReg_R4 # 4
DisReg_R5 # 4
DisReg_R6 # 4
DisReg_R7 # 4
DisReg_R8 # 4
DisReg_R9 # 4
DisReg_R10 # 4
DisReg_R11 # 4
DisReg_R12 # 4
DisReg_R13 # 4
DisReg_R14 # 4
DisReg_R15 # 4
DisReg_F # 1 ; Prefix char for FP registers
DisReg_C # 1 ; Prefix char for Co-pro registers
# 1
# 1
StringBuffer # 160 ; Temp string buffer. Big enough to
; hold a disassembled instruction
; and a full register set + three instrs
......@@ -556,6 +589,11 @@ Debug_Init ENTRY
ANDS R3, R3, #2_11100 ; non-zero if in a 32-bit mode
STRB R3, SysIs32bit
; SAR
MOV R3, #0
STR R3, DisOpts
BL create_codevar
BL init_codevar
EXIT EQ
; Fill in the zero page branch table
......@@ -628,6 +666,9 @@ Debug_Die ENTRY
MOV r0, #0
STR r0, MessageFile_Open
; SAR
BL destroy_codevar
CLRV
EXIT ; Don't refuse to die
......@@ -637,37 +678,37 @@ Debug_Die ENTRY
Debug_HC_Table ; Name Max Min
[ national
Command BreakClr, 1, 0,
Command BreakList, 0, 0,
Command BreakSet, 1, 1,
Command Continue, 0, 0,
Command Debug, 0, 0,
Command InitStore, 1, 0,
Command Memory, 4, 1,; B R + R
Command MemoryA, 3, 1,; B R V
Command BreakClr, 1, 0,
Command BreakList, 0, 0,
Command BreakSet, 1, 1,
Command Continue, 0, 0,
Command Debug, 0, 0,
Command InitStore, 1, 0,
Command Memory, 4, 1,; B R + R
Command MemoryA, 3, 1,; B R V
[ Thumb
Command MemoryI, 6, 1,; T A +/- B + C
Command MemoryI, 6, 1,; T A +/- B + C
|
Command MemoryI, 5, 1,; A +/- B + C
Command MemoryI, 5, 1,; A +/- B + C
]
Command ShowRegs, 0, 0,
Command ShowFPRegs, 0, 0,
Command ShowRegs, 0, 0,
Command ShowFPRegs, 0, 0,
|
Command BreakClr, 1, 0, International_Help
Command BreakList, 0, 0, International_Help
Command BreakSet, 1, 1, International_Help
Command Continue, 0, 0, International_Help
Command Debug, 0, 0, International_Help
Command InitStore, 1, 0, International_Help
Command Memory, 4, 1, International_Help ; B R + R
Command MemoryA, 3, 1, International_Help ; B R V
Command BreakClr, 1, 0, International_Help
Command BreakList, 0, 0, International_Help
Command BreakSet, 1, 1, International_Help
Command Continue, 0, 0, International_Help
Command Debug, 0, 0, International_Help
Command InitStore, 1, 0, International_Help
Command Memory, 4, 1, International_Help ; B R + R
Command MemoryA, 3, 1, International_Help ; B R V
[ Thumb
Command MemoryI, 6, 1, International_Help ; T A +/- B + C
Command MemoryI, 6, 1, International_Help ; T A +/- B + C
|