Commit 9f3e2d5e authored by Kevin Bracey's avatar Kevin Bracey
Browse files

* Disassembly of VFP instruction set added.

* Changed invalid instruction to &E7FFFFFF (as per ARM
  recommendation that &E7FxxxFx should be used)
* Branch disassembly changed - when running on a
  26-bit systems, branch instructions in the lower
  64M will be wrapped within 64M, but branches
  above 64M will not.
* PC-relative LDRH family instructions calculated
  target address incorrectly.

Version 1.62. Tagged as 'Debugger-1_62'
parent 4feae63b
......@@ -45,7 +45,7 @@ Debug_Syntax
InitStore_Help
= "*",TokenEscapeChar,Token0
= " fills user memory with the specified data,"
= " or the value &E6000010 (an illegal ARM instruction) if no"
= " or the value &E7FFFFFF (an illegal ARM instruction) if no"
= " parameter is given."
= 13
InitStore_Syntax
......
......@@ -13,4 +13,7 @@
| limitations under the License.
|
Dir <Obey$Dir>
ModGen rm.DbgMess DebuggerMessages "Debugger Msgs" 0.01 LocalRes:Messages Resources.Debugger.Messages
Copy LocalRes:Messages Resources.<Locale>.CombMsgs ~C~V
Print LocalRes:CmdHelp { >> Resources.<Locale>.CombMsgs }
ModGen rm.DbgMess DebuggerMessages "Debugger Msgs" 0.01 Resources.<Locale>.CombMsgs Resources.Debugger.Messages
Remove Resources.<Locale>.CombMsgs
No preview for this file type
......@@ -8,11 +8,11 @@
GBLS Module_FullVersion
GBLS Module_ApplicationDate2
GBLS Module_ApplicationDate4
Module_MajorVersion SETS "1.61"
Module_Version SETA 161
Module_MajorVersion SETS "1.62"
Module_Version SETA 162
Module_MinorVersion SETS ""
Module_Date SETS "11 Jul 2000"
Module_ApplicationDate2 SETS "11-Jul-00"
Module_ApplicationDate4 SETS "11-Jul-2000"
Module_FullVersion SETS "1.61"
Module_Date SETS "08 Sep 2000"
Module_ApplicationDate2 SETS "08-Sep-00"
Module_ApplicationDate4 SETS "08-Sep-2000"
Module_FullVersion SETS "1.62"
END
/* (1.61)
/* (1.62)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 1.61
#define Module_MajorVersion_CMHG 1.62
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 11 Jul 2000
#define Module_Date_CMHG 08 Sep 2000
#define Module_MajorVersion "1.61"
#define Module_Version 161
#define Module_MajorVersion "1.62"
#define Module_Version 162
#define Module_MinorVersion ""
#define Module_Date "11 Jul 2000"
#define Module_Date "08 Sep 2000"
#define Module_ApplicationDate2 "11-Jul-00"
#define Module_ApplicationDate4 "11-Jul-2000"
#define Module_ApplicationDate2 "08-Sep-00"
#define Module_ApplicationDate4 "08-Sep-2000"
#define Module_FullVersion "1.61"
#define Module_FullVersion "1.62"
......@@ -186,6 +186,15 @@
; NV condition code is now undefined, except for the
; new instructions using it.
; 1.61 KJB 11-Jul-00 ARMv5 warning now shown reliably.
; 1.62 KJB 08-Sep-00 Changed invalid instruction to &E7FFFFFF (as per ARM
; recommendation that &E7FxxxFx should be used)
; Branch disassembly changed - when running on a
; 26-bit systems, branch instructions in the lower
; 64M will be wrapped within 64M, but branches
; above 64M will not.
; Disassembly of VFP instruction set added.
; PC-relative LDRH family instructions calculated
; target address incorrectly.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -852,12 +861,13 @@ Branch ROUT
MOV r4, r4, ASL #8 ; shift offset up to top
BranchCommon
LDRB r2, SysIs32bit
ADD r8, r9, r4, ASR #6
ADD r8, r8, #8 ; pc + 8
LDRB r2, SysIs32bit
TEQ r2, #0
TST r9, #ARM_Addr_Mask ; if in bottom 64M, and system is 26 bit
TEQEQ r2, #0 ; then...
BICEQ r8, r8, #ARM_Addr_Mask ; Wrap in 64MByte space for 26-bit
BEQ BranchLdrStrCommon
......@@ -1333,11 +1343,7 @@ mul_long
; This stupid opcode can be too long. Will hardly ever happen
; so don't increase the tab width (might break some programs).
; Instead, just push the registers over one space.
ADR r1, StringBuffer
SUB r1, r0, r1
TEQS r1, #8
AddChar " ",EQ
BLNE Tab
BL TabOrPushOver
MOV r5, r4, LSR #12 ; RdLo
AND r6, r5, #2_1111
......@@ -1540,6 +1546,7 @@ LdrStrH ; Load and Store Halfword or Load Signed Byte
TSTS r4, #1:SHL:23 ; Up/~Down bit
SUBEQ r8, r9, r8
ADDNE r8, r9, r8
ADD r8, r8, #8
B BranchLdrStrCommon
......@@ -2040,6 +2047,10 @@ Coprocessor
TEQS r2, #2 :SHL: 8
BEQ New_FPA ;new FPA
TEQS r2, #10 :SHL: 8
TEQNES r2, #11 :SHL: 8
BEQ VFP
[ CirrusDSP
CMPS r2, #4 :SHL: 8
BLO Coprocessor_NotFP
......@@ -2464,7 +2475,7 @@ Tab ENTRY
10 ADR r1, StringBuffer
SUB r1, r0, r1
MOV r14, #space
15 MOV r14, #space
STRB r14, [r0], #1
TEQS r1, #7
EXIT EQ
......@@ -2475,6 +2486,18 @@ Tab ENTRY
BL SaveString
EXIT
TabOrPushOver
ALTENTRY
ADR r1, StringBuffer
SUB r1, r0, r1
CMPS r1, #8
BLO %BT15
AddChar " "
EXIT
Rem DCB " ; ", 0
ALIGN
......@@ -2734,7 +2757,7 @@ InitStore_Code ENTRY "r6-r11"
EXIT VS
TST r8, #hasparm
LDREQ r7, =&E6000010 ; A nice invalid instruction
LDREQ r7, =&E7FFFFFF ; A nice invalid instruction
SWI XOS_GetEnv ; r1 -> end of user memory
MOV r14, #UserMemStart
......
......@@ -674,4 +674,4 @@ FPExceptList
FSxx DCB "FSxx", 0
ALIGN
LNK s.Thumb
LNK s.VFP
; Copyright 2000 Pace Micro Technology plc
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; File: VFP.s
; Purpose: Disassembly of the Vector Floating Point instruction set
; Author: K Bracey
; History: 13-Aug-00: KJB: created
VFP
CMP r3, #&E
BEQ VFP_processing
; VFP Load and Store instructions
; arrive here with cccc 110x xxxx xxxx xxxx 101x xxxx xxxx
; format is cccc 110p udwl nnnn dddd 101# iiii iiii
;
; <FLD|FST><S|D>{cond} Fd,[Rn,#imm]
; <FLDM|FSTM><IA|DB><S|D|X>{cond} Rn{!},{reglist}
;
; where cccc = condition
; puw = addressing mode
; # = Double or Mixed/~Single
; dddd(d) = Fd
; l = Load/~Store
; nnnn = Rn
; iiii = 8-bit immediate offset
AND r14, r4, #2_1101:SHL:21 ; isolate PUW
CMP r14, #2_0001:SHL:21
BLS VFP_undefined
TEQ r14, #2_1101:SHL:21
BEQ VFP_undefined
TestStr 20,Fld,Fst
AND r10, r4, #2_1001:SHL:21
TEQ r10, #2_1000:SHL:21 ; P + ~W?
BNE VFP_LdStMultiple
TestBit 8,"D","S"
BL Conditions
BL Tab
BL Dis_VFP_Fd
B CPDT_Common
VFP_LdStMultiple
TestStr 23,Mia,Mdb ; increment/offset or decrement?
TestBit 8,,"S" ; single, or
BEQ %FT20
TestBit 0,"X","D" ; double/unspecified
20 BL Conditions
BL TabOrPushOver ; can be 9 characters!
MOV r5, r4, LSR #16
BL Dis_Register
TEQ r5, #15
BNE %FT22
TestBit 21
MOVNE r10, #Mistake_PCwriteback
STRNE r10, Mistake
22
TestBit 21,"!"
AddStr CmBrc
AND r5, r4, #2_1111:SHL:12 ; start register
MOV r5, r5, LSR #11
TestBit 22
ORRNE r5, r5, #1
BL Dis_VFP_Register
AND r14, r4, #2_11111111 ; offset (number of words to transfer)
MOV r1, r14
TestBit 8
BICNE r14, r14, #1 ; ignore extra word of X form
SUB r14, r14, #1
BICNE r14, r14, #1 ; make it an inclusive end register offset
MOVNE r1, r1, LSR #1 ; r1 = number of registers
TEQ r1, #0
BEQ VFP_unpredictable ; must be > 0
ADD r5, r5, r14 ; end register
CMP r5, #32 ; don't run off end
BHS VFP_unpredictable
TEQ r1, #1 ; if 1 register, that's it
BEQ %FT40
TEQ r1, #2 ; comma for 2 registers
MOVEQ r10, #","
MOVNE r10, #"-"
STRB r10, [r0], #1
BL Dis_VFP_Register ; print the final register
40
AddChar "}"
B InstructionEnd
Fld = "FLD", 0
Fst = "FST", 0
Mia = "MIA", 0
Mdb = "MDB", 0
CmBrc = ",{", 0
ALIGN
VFP_processing
; arrive here with cccc 1110 xxxx xxxx xxxx 101x xxxx xxxx
TestBit 4
BNE VFP_register_transfer
; arrive here with cccc 1110 xxxx xxxx xxxx 101x xxx0 xxxx
; format is cccc 1110 pdqr nnnn dddd 101# nsm0 mmmm
;
; <Primary op><S|D>{cond} Fd,Fn,Fm
; ...
;
; where cccc = condition
; pqrs = primary opcode
; # = Double/~Single
; nnnn(n) = Fn (secondary opcode if pqrs = 1111)
; dddd(d) = Fd
; mmmm(m) = Fm
MOV r6, #0 ; piece together the opcode
TestBit 23
ORRNE r6, r6, #2_1000
AND r14, r4, #2_11:SHL:20
ORR r6, r6, r14, LSR #19
TestBit 6
ORRNE r6, r6, #1
TEQ r6, #15
BEQ VFP_secondary_data_processing
CMP r6, #9
BHS VFP_undefined
ADR r10, VFP_dp_opc1_table
ADD r10, r10, r6, LSL #2
ADD r10, r10, r6, LSL #1
BL SaveString
TestBit 8,"D","S"
BL Conditions
BL TabOrPushOver
BL Dis_VFP_Fd
BL Comma_Dis_VFP_Fn
BL Comma_Dis_VFP_Fm
B InstructionEnd
VFP_dp_opc1_table
= "FMAC",0,0
= "FNMAC",0
= "FMSC",0,0
= "FNMSC",0
= "FMUL",0,0
= "FNMUL",0
= "FADD",0,0
= "FSUB",0,0
= "FDIV",0;,0
VFP_monadic_table
= "FCPY",0,0
= "FABS",0,0
= "FNEG",0,0
= "FSQRT",0
ALIGN
VFP_secondary_data_processing
; arrive here with cccc 1110 1x11 xxxx xxxx 101x x1x0 xxxx
; format is cccc 1110 1d11 nnnn dddd 101# n1m0 mmmm
;
; <Secondary op><S|D>{cond} Fd,Fm
; ...
;
; where cccc = condition
; # = Double/~Single
; nnnn(n) = secondary opcode
; dddd(d) = Fd
; mmmm(m) = Fm
AND r6, r4, #2_1111:SHL:16
MOV r6, r6, LSR #15
TestBit 7
ORRNE r6, r6, #1 ; r6 = opcode
CMP r6, #2_00011 ; 000xx = monadic
BLS VFP_monadic
CMP r6, #2_01000
BLO VFP_undefined
CMP r6, #2_01011 ; 010xx = compare
BLS VFP_compare
CMP r6, #2_01111
BLO VFP_undefined
BEQ VFP_convert_precision ; 01111 = convert S<->D
CMP r6, #2_10001
BLS VFP_convert_to_fp ; 1000x = convert to FP
CMP r6, #2_11000
BLO VFP_undefined
CMP r6, #2_11011
BLS VFP_convert_to_int ; 110xx = convert to int
B VFP_undefined
VFP_monadic
; arrive here with cccc 1110 1x11 000x xxxx 101x x1x0 xxxx
; format is cccc 1110 1d11 000n dddd 101# n1m0 mmmm
;
; <FCPY|FABS|FNEG|FSQRT><S|D>{cond} Fd,Fm
ADR r10, VFP_monadic_table
ADD r10, r10, r6, LSL #2
ADD r10, r10, r6, LSL #1
BL SaveString
TestBit 8,"D","S"
BL Conditions
BL TabOrPushOver
BL Dis_VFP_Fd
BL Comma_Dis_VFP_Fm
B InstructionEnd
VFP_compare
; arrive here with cccc 1110 1x11 010x xxxx 101x x1x0 xxxx
; format is cccc 1110 1d11 010z dddd 101# e1m0 mmmm
;
; FCMP{E}<S|D>{cond} Fd,Fm
; FCMP{E}Z<S|D>{cond} Fd
AddStr Fcmp
TestBit 7,"E"
TestBit 16,"Z"
TestBit 8,"D","S"
BL Conditions
BL TabOrPushOver
BL Dis_VFP_Fd
TestBit 16
BNE %FT20
BL Comma_Dis_VFP_Fm
B InstructionEnd
20
TST r4, #2_101111
BEQ InstructionEnd ; I'm following the ARM ARM
TestBit 5 ; to the letter here - bit 5
BNE VFP_undefined ; IS 0, bits 0-3 SHOULD BE
B VFP_unpredictable ; zero
VFP_convert_precision
; arrive here with cccc 1110 1x11 0111 xxxx 101x 11x0 xxxx
; format is cccc 1110 1d11 0111 dddd 101# 11m0 mmmm
;
; FCVTDS{cond} Dd,Sm
; FCVTSD{cond} Sd,Dm
AddStr Fcvt
TestBit 8
MOVEQ r10, #"D"
MOVNE r10, #"S" ; First letter is inverse
STRB r10, [r0], #1 ; of precision
EOR r10, r10, #"D":EOR:"S" ; Second is opposite
STRB r10, [r0], #1
BL Conditions
BL TabOrPushOver
EOR r4, r4, #1:SHL:8 ; Sneakily invert D/S
BL Dis_VFP_Fd
EOR r4, r4, #1:SHL:8 ; Put it back
BL Comma_Dis_VFP_Fm
B InstructionEnd
VFP_convert_to_fp
; arrive here with cccc 1110 1x11 1000 xxxx 101x x1x0 xxxx
; format is cccc 1110 1d11 1000 dddd 101# s1m0 mmmm
;
; F<S|U>ITO<S|D>{cond} Fd,Sm
TestStr 7,Fsito,Fuito
TestBit 8,"D","S"
BL Conditions
BL TabOrPushOver
BL Dis_VFP_Fd
BL Comma_Dis_VFP_Sm
B InstructionEnd
VFP_convert_to_int
; arrive here with cccc 1110 1x11 110x xxxx 101x x1x0 xxxx
; format is cccc 1110 1d11 110s dddd 101# z1m0 mmmm
;
; FTO<U|S>I{Z}<S|D>{cond} Sd,Fm
AddStr Fto
TestBit 16,"S","U"
AddChar "I"
TestBit 7,"Z"
TestBit 8,"D","S"
BL Conditions
BL TabOrPushOver
BL Dis_VFP_Sd
BL Comma_Dis_VFP_Fm
B InstructionEnd
Fcmp = "FCMP",0
Fcvt = "FCVT",0
Fsito = "FSITO",0
Fuito = "FUITO",0
Fto = "FTO",0
ALIGN
ROUT
VFP_register_transfer
; arrive here with cccc 1110 xxxx xxxx xxxx 101x xxx1 xxxx
; format is cccc 1110 oool nnnn dddd 101# n001 0000
TST r4, #2_11:SHL:5
BNE VFP_undefined
TST r4, #2_1111
BNE VFP_unpredictable
AND r6, r4, #2_111:SHL:21
TestBit 23
BNE VFP_system_register_transfer
CMP r6, #2_010:SHL:21
BHS VFP_undefined
; arrive here with cccc 1110 00xx xxxx xxxx 101x x001 0000
; format is cccc 1110 00hl nnnn dddd 101# n001 0000
;
; FMSR{cond} Sn,Rd
; FMRS{cond} Rd,Sn
; FMD<L|H>R{cond} Dn,Rd
; FMRD<L|H>{cond} Rd,Dn
AddStr Fm
ADR r10, VFPRT_table
AND r6, r4, #2_11:SHL:20
TestBit 8
ORRNE r6, r6, #1:SHL:19 ; hl#
LDRB r14, [r10, r6, LSR #19-2]!
TEQ r14, #0
BEQ VFP_undefined
BL SaveStringConditions
BL Tab
TestBit 20
BNE %FT20
BL Dis_VFP_Fn
MOV r5, r4, LSR #12
BL Comma_Dis_Register
B InstructionEnd
20 MOV r5, r4, LSR #12
BL Dis_Register
BL Comma_Dis_VFP_Fn
B InstructionEnd
Fm = "FM",0
VFPRT_table
= "SR",0,0
= "DLR",0
= "RS",0,0
= "RDL",0
= 0,0,0,0
= "DHR",0
= 0,0,0,0
= "RDH",0
Fmrx = "FMRX",0
Fmxr = "FMXR",0
Fpsid = "FPSID",0
Fpscr = "FPSCR",0
Fpexc = "FPEXC",0
Fmstat = "FMSTAT",0
ALIGN
ROUT
VFP_system_register_transfer
; arrive here with cccc 1110 1xxx xxxx xxxx 101x x001 0000
; format is cccc 1110 111l nnnn dddd 1010 n001 0000
;
; FMXR{cond} <FPSID|FPSCR|FPEXC>,Rd
; FMRX{cond} Rd,<FPSID|FPSCR|FPEXC>
TEQ r6, #2_111:SHL:21
TSTEQ r4, #1:SHL:8
BNE VFP_undefined
TestStr 20,Fmrx,Fmxr,conds
TestBit 20
BNE %FT20
BL Tab
BL Dis_VFP_Sys_Fn
MOV r5, r4, LSR #12
BL Comma_Dis_Register
B InstructionEnd
20 AND r14, r4, #&FF:SHL:12 ; check for FMSTAT (FMRX PC,FPSCR)
TEQ r14, #&1F:SHL:12
TSTEQ r4, #1:SHL:7
BNE %FT25
TST r4, #1:SHL:20
BEQ %FT25
ADR r0, StringBuffer
AddStr Fmstat,,conds
B InstructionEnd
25 MOV r5, r4, LSR #12
BL Tab_Dis_Register
BL AddComma
BL Dis_VFP_Sys_Fn
B InstructionEnd
Dis_VFP_Sys_Fn
TestBit 7
BNE VFP_undefined
AND r5, r4, #2_1111:SHL:16
MOV r10, #0
CMP r5, #2_0001:SHL:16
ADRLO r10, Fpsid
ADREQ r10, Fpscr
TEQ r5, #2_1000:SHL:16
ADREQ r10, Fpexc
TEQ r10, #0
BNE SaveString
B VFP_undefined
Comma_Dis_VFP_Register
AddChar ","
Dis_VFP_Register
CLC
AND r8, r5, #2_11111
TestBit 8,"D","S"
MOVNES r8, r8, LSR #1
BCC StoreDecimal
B VFP_undefined
Dis_VFP_Fd
AND r5, r4, #2_1111:SHL:12
MOV r5, r5, LSR #11
TestBit 22
ORRNE r5, r5, #1
B Dis_VFP_Register
Comma_Dis_VFP_Fn
AddChar ","
Dis_VFP_Fn
AND r5, r4, #2_1111:SHL:16
MOV r5, r5, LSR #15
TestBit 7
ORRNE r5, r5, #1
B Dis_VFP_Register
Comma_Dis_VFP_Fm
AddChar ","
Dis_VFP_Fm
MOV r5, r4, LSL #1
TestBit 5
ORRNE r5, r5, #1
B Dis_VFP_Register
Dis_VFP_S_Register
AddChar "S"
AND r8, r5, #2_11111
B StoreDecimal
Dis_VFP_Sd
AND r5, r4, #2_1111:SHL:12
MOV r5, r5, LSR #11
TestBit 22
ORRNE r5, r5, #1
B Dis_VFP_S_Register
Comma_Dis_VFP_Sm
AddChar ","
Dis_VFP_Sm
MOV r5, r4, LSL #1
TestBit 5
ORRNE r5, r5, #1
B Dis_VFP_S_Register