Commit 34e34203 authored by Kevin Bracey's avatar Kevin Bracey
Browse files

* Added ARMv5TE instructions.

* Fixed disassembly of Thumb high MOV/ADD/CMP instructions.

Version 1.64. Tagged as 'Debugger-1_64'
parent 9371049f
......@@ -29,6 +29,7 @@ M64:*** Rn in list
M66:*** Rd=Rm
M67:*** Only 1 reg on SA-1 rev 2
M68:ARMv5 or later
M69:ARMv5TE or later
M16:Store initialised to &
M17:Register dump (stored at &
M18:) is:
......
......@@ -11,14 +11,14 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.63"
Module_Version SETA 163
Module_MajorVersion SETS "1.64"
Module_Version SETA 164
Module_MinorVersion SETS ""
Module_Date SETS "30 Jan 2001"
Module_ApplicationDate2 SETS "30-Jan-01"
Module_ApplicationDate4 SETS "30-Jan-2001"
Module_Date SETS "31 Jan 2001"
Module_ApplicationDate2 SETS "31-Jan-01"
Module_ApplicationDate4 SETS "31-Jan-2001"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.63"
Module_HelpVersion SETS "1.63 (30 Jan 2001)"
Module_FullVersion SETS "1.64"
Module_HelpVersion SETS "1.64 (31 Jan 2001)"
END
/* (1.63)
/* (1.64)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 1.63
#define Module_MajorVersion_CMHG 1.64
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 30 Jan 2001
#define Module_Date_CMHG 31 Jan 2001
#define Module_MajorVersion "1.63"
#define Module_Version 163
#define Module_MajorVersion "1.64"
#define Module_Version 164
#define Module_MinorVersion ""
#define Module_Date "30 Jan 2001"
#define Module_Date "31 Jan 2001"
#define Module_ApplicationDate2 "30-Jan-01"
#define Module_ApplicationDate4 "30-Jan-2001"
#define Module_ApplicationDate2 "31-Jan-01"
#define Module_ApplicationDate4 "31-Jan-2001"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.63"
#define Module_HelpVersion "1.63 (30 Jan 2001)"
#define Module_FullVersion "1.64"
#define Module_HelpVersion "1.64 (31 Jan 2001)"
......@@ -199,6 +199,8 @@
; 1.63 SAR 30-Jan-01 ADDS Rd,PC,#imm (and SUBS) no longer map to ADR.
; Unknown SWIs, such as 'User' and 'OS_Undefind' are now
; disassembled as 'SWI &num'.
; 1.64 KJB 31-Jan-01 Added ARMv5TE instructions.
; Corrected Thumb high ADD/CMP/MOV.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -240,6 +242,9 @@ WarnSArev2 SETL False ; Warn about hitting the SA revision 2 S
GBLL WarnARMv5
WarnARMv5 SETL True ; Indicate ARMv5 or later instructions
GBLL WarnARMv5E
WarnARMv5E SETL True
GBLL Thumb
Thumb SETL True
......@@ -320,6 +325,7 @@ Mistake_Rninlist # 1
Mistake_RdRm # 1
Mistake_STMHat # 1
Mistake_ARMv5 # 1
Mistake_ARMv5E # 1
^ -1
Potential_SWICDP # -1
......@@ -778,6 +784,9 @@ Instruction ENTRY "r0, r3-r9"
; .............................................................................
Undefined
MOV r14, #0 ; Undefined can't have a mistake :)
STR r14, Mistake
ADR r0, StringBuffer ; Reset pointer
ADR r10, Unknown
BL lookup_r10
......@@ -1176,10 +1185,17 @@ LdrStr ROUT
; mmmm = Rm
; iiii = 12-bit unsigned immediate offset
; Not totally clear which order these tests should be in, but it
; doesn't matter for the time being - this restriction applies to
; both LDR and PLD.
TST r4, #1 :SHL: 25 ; If Rm and shift and trying Rs
TSTNE r4, #1 :SHL: 4 ; then that was xxR Rd,[Rn,Rm,SHF Rs]
BNE Undefined ; but ARM2 doesn't do that anymore
MOV r14, r4, LSR #28
TEQ r14, #15
BEQ Preload
TestStr 20,Ldr,Str,conds ; Load/~Store bit
MOV r5, r4, LSR #12 ; Rd
......@@ -1210,10 +1226,12 @@ LdrStr ROUT
TEQS r10, #2_1000 :SHL: 21
BEQ %FT10 ; if not writeback, okay
TestBit 25
BNE %FT05
[ {FALSE} ; ARM ARM says nothing about zero
TestBit 25 ; offset OK, and it isn't entirely
BNE %FT05 ; logical - KJB
MOVS r14, r4, LSL #32-12
BEQ %FT10 ; zero offset, so okay
]
5 AND r14, r4, #2_1111 :SHL: 12
AND r10, r4, #2_1111 :SHL: 16
......@@ -1233,6 +1251,9 @@ LdrStr ROUT
20
DataTransfer_Common ; for CPDT - address part similar to LDR/STR (no reg index)
AddChar ","
DataTransfer_Common_NoComma
;from 1.23, show resultant LDR/STR Rx,[R15,#nnn] address directly
......@@ -1253,7 +1274,6 @@ DataTransfer_Common ; for CPDT - address part similar to LDR/STR (no reg index)
TEQS r14,#2_01000 :SHL: 21
BNE not_rel
AddChar ","
MOV R8,R4,LSL #32-12
MOV R8,R8,LSR #32-12
......@@ -1270,7 +1290,7 @@ DataTransfer_Common ; for CPDT - address part similar to LDR/STR (no reg index)
B BranchLdrStrCommon
not_rel
AddStr Open_B ; ',['
AddChar "["
MOV r5, r4, LSR #16 ; Rn
BL Dis_Register
......@@ -1330,11 +1350,44 @@ Ldr DCB "LDR", 0
Str DCB "STR", 0
Open_B DCB ",[", 0
Close_B DCB "],", 0
Pld DCB "PLD", 0
Preload ROUT
; Preload
; arrive here with 1111 01xx xxxx xxxx xxxx xxxx xxxx xxxx
; format is 1111 0101 u101 nnnn 1111 iiii iiii iiii
; or 1111 0111 u101 nnnn 1111 rrrr rtt0 mmmm
;
; PLD [Rn,#offset]
; [Rn,{+|-}Rm{,shift}]
;
; where u = Up/~Down
; nnnn = Rn
; rrrrr = shift amount
; tt = shift type (LSL, LSR, ASR or ROR)
; mmmm = Rm
; iiii = 12-bit unsigned immediate offset
[ WarnARMv5E
MOV r14, #Mistake_ARMv5E
STR r14, Mistake
]
AddStr Pld
BL Tab
AND r5, r4, #2_10111:SHL:20
TEQ r5, #2_10101:SHL:20
ANDEQ r5, r4, #2_1111:SHL:12
TEQEQ r5, #2_1111:SHL:12
BEQ DataTransfer_Common_NoComma
B Undefined
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Mull DCB "MULL",0
Mlal DCB "MLAL",0
ALIGN
Mul DCB "MUL", 0
Mla DCB "MLA", 0
aswp DCB "SWP", 0
......@@ -1381,10 +1434,21 @@ ArithmeticExtension
AND R5,R4,#15 ; Rm
MOV R10, R4, LSR #16
AND R10,R10,#15
TEQS R10,R5
TEQNES R10,#15
MOVEQ R14,#Mistake_MUL
STREQ R14,Mistake
MOV R8, R4, LSR #12
AND R8, R8, #15
MOV R9, R4, LSR #8
AND R9, R9, #15
TEQS R5, R10
MOVEQ R14, #Mistake_RdRm
STREQ R14, Mistake
TEQS R10, #15
TEQNES R8, #15
TEQNES R9, #15
TEQNES R5, #15
MOVEQ R14, #Mistake_R15
STREQ R14, Mistake
BL Comma_Dis_Register
......@@ -1540,15 +1604,15 @@ LoadStoreExtension
TSTS r4, #2_11:SHL:5
BEQ Undefined
LdrStrH ; Load and Store Halfword or Load Signed Byte
LdrStrH ; Load and Store Halfword/Doubleword or Load Signed Byte
; arrive here with cccc 000x xxxx xxxx xxxx xxxx 1nn1 xxxx
; (nn != 00)
; format is cccc 000p uiwl nnnn dddd aaaa 1sh1 bbbb
;
; LDR{cond}<H|SH|SB> Rd,[Rn,<#offset|Rm>]{!}
; Rd,[Rn],<#offset|Rm>
; STR{cond}H Rd,[Rn,<#offset|Rm>]{!}
; Rd,[Rn],<#offset|Rm>
; LDR{cond}<H|SH|SB|D> Rd,[Rn,<#offset|Rm>]{!}
; Rd,[Rn],<#offset|Rm>
; STR{cond}<H|D> Rd,[Rn,<#offset|Rm>]{!}
; Rd,[Rn],<#offset|Rm>
; where cccc = condition
; p = Pre-indexed/~Post-indexed
; u = Up/~Down
......@@ -1568,21 +1632,61 @@ LdrStrH ; Load and Store Halfword or Load Signed Byte
BNE %F5
TSTS r4, #&00000F00
BNE Undefined
; Can only have STRH, not STRSH or STRSB
5 TSTS r4, #1:SHL:20 ; Load/~Store
5 AND r5, r4, #1:SHL:24 :OR: 1:SHL:21
TEQS r5, #1:SHL:21 ; Check for post-indexed with W set (illegal)
BEQ Undefined
TSTS r4, #1:SHL:20 ; Load/~Store
BNE %F20
AND r5, r4, #&000000F0
TEQS r5, #&000000B0
BNE Undefined
20 AND r5, r4, #1:SHL:24 :OR: 1:SHL:21
TEQS r5, #1:SHL:21 ; Check for post-indexed with W set (illegal)
BEQ Undefined
BEQ %F20
; STRSB or STRSH - actually LDRD+STRD
TestStr 5,Str,Ldr,conds
AddChar "D"
TestBit 12 ; Must be even-numbered register
BNE Undefined
TestStr 20,Ldr,Str,conds
[ WarnARMv5E
MOV r14, #Mistake_ARMv5E
STR r14, Mistake
]
AND r10, r4, #15:SHL:12 ; r10 = Rd << 12
; Check for Rd/Rd+1=Rn with writeback
AND r14, r4, #2_10010:SHL:20
TEQS r14, #2_10000:SHL:20
BEQ %F15
AND r14, r4, #14:SHL:16
TEQ r14, r10, LSL #4
MOVEQ r14, #Mistake_RdRn
STREQ r14, Mistake
15 ; Check for LDRD with Rd/Rd+1=Rm
TSTS r4, #1:SHL:5 ; H clear => LDRD
TSTEQS r4, #1:SHL:22 ; I clear => [Rd,Rm]
ANDEQ r14, r4, #14
TEQEQS r14, r10, LSR #12
MOVEQ r14, #Mistake_RdRm
STREQ r14, Mistake
; Check for LDRD/STRD of R14+PC
TEQ r10, #14:SHL:12
MOVEQ r14, #Mistake_R15
STREQ r14, Mistake
B %F22
20
TestStr 20,Ldr,Str,conds
TestBit 6,"S"
TestBit 5,"H","B"
MOV r5, r4, LSR #12
22 MOV r5, r4, LSR #12
BL Tab_Dis_Register
; Check we're not storing/loading PC
......@@ -1600,11 +1704,13 @@ LdrStrH ; Load and Store Halfword or Load Signed Byte
AND r10, r4, #&F:SHL:16 ; If Rd <> Rn then OK
TEQS r5, r10, LSR #16
BNE %FT30
[ {FALSE}
TSTS r4, #1:SHL:22 ; If a register offset, then fail
BEQ %FT25
TSTS r4, #&F
TSTEQS r4, #&F00
BEQ %FT30 ; If an immediate offset of 0, then OK
]
25 MOV r10, #Mistake_RdRn
STR r10, Mistake
......@@ -1888,10 +1994,19 @@ ControlExtension
TEQNE r5, #2_0011 :SHL: 4
BEQ CLZ_BX_type ; 1,3 = CLZ/BX
TEQ r5, #2_0101 :SHL: 4 ; 5 = QADD etc
BEQ SaturatingArithmetic
TEQ r5, #2_0111 :SHL: 4 ; 7 = BKPT
BEQ is_BKPT
B Undefined
CMP r5, #2_1000 :SHL: 4 ; 2,4,6 undefined
BLO Undefined
TST r5, #2_0001 :SHL: 4 ; 8,10,12,14 = SMUL etc
BEQ Mul16
B Undefined ; 9,11,13,15 undefined
ControlExtension_immediate
; arrive here with cccc 0011 0xx0 xxxx xxxx xxxx xxxx xxxx
......@@ -1926,8 +2041,29 @@ is_MRS ; arrive here with cccc 0001 0x00 xxxx xxxx xxxx 0000 xxxx
BL CPSR_or_SPSR
B InstructionEnd
OpcTAB DCB "AND",0
DCB "EOR",0
SubTAB DCB "SUB",0
DCB "RSB",0
AddTAB DCB "ADD",0
DCB "ADC",0
DCB "SBC",0
DCB "RSC",0
DCB "TST",0
DCB "TEQ",0
DCB "CMP",0
DCB "CMN",0
DCB "ORR",0
DCB "MOV",0
DCB "BIC",0
DCB "MVN",0
cpsr_tab DCB "CPSR",0
spsr_tab DCB "SPSR",0
BxTAB DCB "BX", 0
ALIGN
BkptTAB DCB "BKPT",0
ALIGN
......@@ -1976,15 +2112,14 @@ CLZ_BX_type
BNE is_CLZ
is_BX ; arrive here with cccc 0001 00x0 xxxx xxxx xxxx 00x1 xxxx
; (oo != 00)
;
; format is cccc 0001 0010 1111 1111 1111 00l1 nnnn
; format is cccc 0001 0010 1111 1111 1111 00l1 mmmm
;
; B{L}X{cond} Rn
; B{L}X{cond} Rm
;
; where cccc = condition
; l = Link
; nnnn = Rn
; mmmm = Rm
LDR r3, =&002FFF00
AND r5, r4, r3
TEQ r5, r3
......@@ -2025,15 +2160,14 @@ BLX_offset
is_CLZ ; arrive here with cccc 0001 01x0 xxxx xxxx xxxx 00x1 xxxx
; (oo != 00)
;
; format is cccc 0001 0110 1111 dddd 1111 0001 nnnn
; format is cccc 0001 0110 1111 dddd 1111 0001 mmmm
;
; CLZ{cond} Rd, Rn
; CLZ{cond} Rd, Rm
;
; where cccc = condition
; dddd = Rd
; nnnn = Rn
; mmmm = Rm
LDR r3, =&002F0F10
TestBit 5
BNE Undefined
......@@ -2085,31 +2219,146 @@ is_BKPT ; arrive here with cccc 0001 0xx0 xxxx xxxx xxxx 0111 xxxx
BL StoreHex
B InstructionEnd
SaturatingArithmetic
; arrive here with cccc 0001 0xx0 xxxx xxxx xxxx 0101 xxxx
; format is cccc 0001 0ds0 nnnn dddd 0000 0101 mmmm
;
; Q{D}<ADD|SUB>{cond} Rd, Rn, Rm
;
; where cccc = condition
; d = Double
; s = Subtract/~Add
; nnnn = Rn
; dddd = Rd
; mmmm = Rm
TST r4, #2_1111:SHL:8
BNE Undefined
[ WarnARMv5E
MOV r14, #Mistake_ARMv5E
STR r14, Mistake
]
AND r14, r4, #15:SHL:16
TEQ r14, #15:SHL:16
ANDNE r14, r4, #15:SHL:12
TEQNE r14, #15:SHL:12
ANDNE r14, r4, #15
TEQNE r14, #15
MOVEQ r14, #Mistake_R15
STREQ r14, Mistake
AddChar "Q"
TestBit 22,"D"
TestStr 21,SubTAB,AddTAB,conds
MOV r5, r4, LSR #12
BL Tab_Dis_Register
MOV r5, r4, LSR #16
BL Comma_Dis_Register
MOV r5, r4
BL Comma_Dis_Register
B InstructionEnd
Mul16 ROUT
; arrive here with cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx
; format is cccc 0001 0oo0 dddd nnnn ssss 1yx0 mmmm
;
; SMLA<B|T><B|T>{cond} Rd, Rm, Rs, Rn op = 0
; SMLAW<B|T>{cond} Rd, Rm, Rs, Rn op = 1, x = 0
; SMULW<B|T>{cond} Rd, Rm, Rs op = 1, x = 1
; SMLAL<B|T><B|T>{cond} RdLo, RdHi, Rm, Rs op = 2
; SMUL<B|T><B|T>{cond} Rd, Rm, Rs op = 3
;
; where cccc = condition
; oo = operation
; dddd = Rd or RdHi
; nnnn = Rn or RdLo
; ssss = Rs
; y = Top/~Bottom of Rs
; x = Top/~Bottom of Rm
; mmmm = Rm
AND r7, r4, #2_11:SHL:21 ; r7 = oo (<< 21)
TestBit 5
ORRNE r6, r7, #1:SHL:20 ; r6 = oox (<< 20)
MOVEQ r6, r7
ADR r10, Mul16TAB
ADD r10, r10, r6, LSR #17
SUB r10, r10, r6, LSR #20 ; r10 = Mul16TAB + 7 * oox
BL SaveString
TestBit 6,"T","B"
BL Conditions
TEQ r6, #2_011:SHL:20
TEQNE r7, #2_11 :SHL:21
BNE %FT10
TST r4, #2_1111:SHL:12 ; Check Rn field is 0 for SMUL
BNE Undefined
10
[ WarnARMv5E
MOV r14, #Mistake_ARMv5E
STR r14, Mistake
]
BL TabOrPushOver
TEQ r7, #2_10 :SHL:21 ; EQ if SMLAL
BNE %FT15
MOV r5, r4, LSR #12
AND r8, r5, #15
BL Dis_Register ; RdLo
MOV r5, r4, LSR #16
AND r9, r5, #15
BL Comma_Dis_Register ; RdHi
TEQ r8, r9
MOVEQ r14, #Mistake_RdLoRdHi
STREQ r14, Mistake
B %FT17
15 MOV r5, r4, LSR #16
BL Dis_Register ; Rd
17 MOV r5, r4
BL Comma_Dis_Register ; Rm
MOV r5, r4, LSR #8
BL Comma_Dis_Register ; Rs
CMP r6, #2_010:SHL:20
MOVLS r5, r4, LSR #12
BLLS Comma_Dis_Register ; Rn
AND r14, r4, #15:SHL:16
TEQ r14, #15:SHL:16
ANDNE r14, r4, #15:SHL:12
TEQNE r14, #15:SHL:12
ANDNE r14, r4, #15:SHL:8
TEQNE r14, #15:SHL:8
ANDNE r14, r4, #15
TEQNE r14, #15
MOVEQ r14, #Mistake_R15
STREQ r14, Mistake
B InstructionEnd
AdrTAB DCB "ADR",0
MrsTAB DCB "MRS",0
MsrTAB DCB "MSR",0
BxTAB DCB "BX", 0
BkptTAB DCB "BKPT",0
BlxTAB DCB "BLX",0
ClzTAB DCB "CLZ",0
ALIGN
OpcTAB DCB "AND",0
DCB "EOR",0
DCB "SUB",0
DCB "RSB",0
DCB "ADD",0
DCB "ADC",0
DCB "SBC",0
DCB "RSC",0
DCB "TST",0
DCB "TEQ",0
DCB "CMP",0
DCB "CMN",0
DCB "ORR",0
DCB "MOV",0
DCB "BIC",0
DCB "MVN",0
Mul16TAB
DCB "SMLAB",0,0
DCB "SMLAT",0,0
DCB "SMLAW",0,0
DCB "SMULW",0,0
DCB "SMLALB",0
DCB "SMLALT",0
DCB "SMULB",0,0
DCB "SMULT",0
ALIGN
Ldc DCB "LDC", 0
Stc DCB "STC", 0
......@@ -2117,6 +2366,8 @@ Cdp DCB "CDP", 0
Mcr DCB "MCR", 0
Mrc DCB "MRC", 0
Cp DCB "CP", 0
Mcrr DCB "MCRR", 0
Mrrc DCB "MRRC", 0
ALIGN
......@@ -2181,7 +2432,7 @@ Co_Transfer
; Coprocessor Data Transfer (CPDT)
TST r4, #2_1101 :SHL: 21
BEQ Undefined ; Post-indexed, down, no writeback
BEQ CoprocessorExtension ; Post-indexed, down, no writeback
TestStr 20,Ldc,Stc,conds,2 ; Load/~Store bit
......@@ -2199,6 +2450,61 @@ CPDT_Common ; FP entry point from below
BIC r4, r4, #&00000F00 ; Clear CP# field
B DataTransfer_Common
CoprocessorExtension
; arrive here with cccc 1100 0x0x xxxx xxxx xxxx xxxx xxxx
TestBit 22
BEQ Undefined
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Coprocessor Double Register Transfer (CPRRT)
CPRRT
; arrive here with cccc 1100 010x xxxx xxxx xxxx xxxx xxxx
; format is cccc 1100 010l nnnn dddd #### oooo mmmm
;
; <MCRR|MRRC>{cond} CP#,op,Rd,Rn,Cm
;
; where cccc = cond
; l = Load/~Store (ie load from coprocessor)
; nnnn = Rn
; dddd = Rd
; #### = CP#
; oooo = operation
; mmmm = Cm
[ WarnARMv5E
MOV r14, #Mistake_ARMv5E
STR r14, Mistake
]
TestStr 20,Mrrc,Mcrr,conds
BL Tab_CPN
MOV r8, r4, LSR #4
AND r8, r8, #2_1111
BL StoreDecimal
MOV r5, r4, LSR #12
AND r6, r5, #2_1111
BL Comma_Dis_Register