Commit 8320aaab authored by Kevin Bracey's avatar Kevin Bracey
Browse files

* 32-bit compatibility added.

* New *ShowFPRegs command.
* Added ARMv5 instructions (BLX, CLZ, BKPT, CDP2 et al)
* Handling of instruction extension space adjusted as per ARMv4.
* Fixed some Thumb instructions.
* Added "info" form of LDC and STC.
* NV condition code is now undefined, except for the new instructions using
  it.

Version 1.60. Tagged as 'Debugger-1_60'
parent deb7de04
cccc 00x1 0xx0 xxxx xxxx xxxx xxxx xxxx
cccc 0001 0r00 1111 dddd 0000 0000 0000 MRS
cccc 0001 0r10 fsxc 1111 0000 0000 mmmm MSR reg
cccc 0001 0110 1111 dddd 1111 0001 mmmm CLZ
cccc 0001 0010 1111 1111 1111 00x1 mmmm BX
cccc 0001 0000 mmmm dddd 0000 0101 nnnn QADD
cccc 0001 0010 mmmm dddd 0000 0101 nnnn QSUB
cccc 0001 0100 mmmm dddd 0000 0101 nnnn QDADD
cccc 0001 0110 mmmm dddd 0000 0101 nnnn QDSUB
cccc 0001 0010 nnnn nnnn nnnn 0111 nnnn BKPT
cccc 0001 0110 dddd 0000 ssss 1yx0 mmmm SMULxy
cccc 0001 0010 dddd 0000 ssss 1y10 mmmm SMULWy
cccc 0001 0000 dddd nnnn ssss 1yx0 mmmm SMLAxy
cccc 0001 0010 dddd nnnn ssss 1y00 mmmm SMLAWy
cccc 0001 0100 hhhh llll ssss 1yx0 mmmm SMLALxy
cccc 0011 0r10 fsxc 1111 rrrr iiii iiii MSR imm
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From: David Seal <dseal@arm.com>
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for kevin.bracey@pacemicro.com; Tue, 18 Apr 2000 15:14:25 +0100 (BST)
Date: Tue, 18 Apr 2000 15:14:25 +0100 (BST)
Message-Id: <200004181414.PAA03180@sun9.cambridge.arm.com>
To: kevin.bracey@pace.co.uk
Subject: Re: Architecture 5
X-Sun-Charset: US-ASCII
Status: RO
Hi,
Just saw your article requesting details of architecture 5 instruction
encodings, etc. An updated ARM ARM should be in the next release of
ADS, I believe. In the meantime, here are brief details of the
architecture 5 changes:
Programmer's model change:
The CPSR T bit and the BX instruction become defined regardless of
whether the processor supports Thumb. Effect of setting the T bit for
a processor that does not support Thumb is that the next instruction
executed will be treated as an undefined instruction. (Effect of this
change is that identical call/return sequences can be used regardless
of whether the processor supports Thumb - exception only happens on a
processor without Thumb if an actual Thumb procedure is called, not
if a BX instruction is used for calls or returns between ARM
procedures.
General instruction change:
Condition field = 1111 is now used to select a new class of
unconditional instructions. Its old meaning of "never" has been
obsolete for some time, and is now replaced. The "NV" condition
mnemonic is no longer valid in assembler language source.
Coprocessor instructions (CDP, LDC, MCR, MRC, STC) gain an extra
unconditional form in this new class. The new form is selected in the
assembler syntax by putting "2" where the condition mnemonic would
normally be.
Changed behaviour of existing instructions:
All flag-setting multiply instructions are required to preserve the C
and V flags in architecture 5 and above. (Some previously made one or
both of these flags "UNPREDICTABLE". This is a tightening-up of the
specification and does not lead to backwards incompatibility.)
The following instructions (as designated in the current printed ARM)
have changed behaviour if they load R15:
ARM: LDM (1)
LDR
Thumb: POP
The change is that bit[0] of the loaded value controls whether the
processor is placed in Thumb or ARM state afterwards, as though a BX
<loaded value> instruction had been executed. (Previous behaviour was
as though a MOV PC,<loaded value> had been executed.)
To ease the transition in case of incompatibilities caused by this,
initial ARMv5 processors can be configured to suppress this
behaviour. This is done by setting bit[15] of CP15 register 1.
New ARM instructions:
BKPT <immediate>
31 28 27 20 19 8 7 4 3 0
+------+----------+-------------+------+------------+
| cond | 00010010 | immed[15:4] | 0111 | immed[3:0] |
+------+----------+-------------+------+------------+
Breakpoint instruction. Like a SWI, except:
* Generates a prefetch abort, not a SWI exception.
* 16-bit immediate, not 24-bit.
* Must be unconditional.
* Debug hardware is specifically permitted to intercept it and
prevent the prefetch abort ever occurring (so instruction is only
useful for debug purposes).
BLX <label>
31 28 27 25 24 23 0
+------+-----+---+-----------------+
| 1111 | 101 | H | 24_bit_offset |
+------+-----+---+-----------------+
Just like BL, except:
* Instruction is unconditional, in what was "NV space".
* Control arrives at the destination in Thumb state, not ARM state.
* The H bit (bit[24]) becomes bit[1] of the destination address, to
allow for Thumb destination instructions only necessarily being
halfword-aligned, not word-aligned.
BLX{<cond>} <Rm>
31 28 27 20 19 16 15 12 11 8 7 4 3 0
+------+----------+------+------+------+------+------+
| cond | 00010010 | 1111 | 1111 | 1111 | 0011 | Rm |
+------+----------+------+------+------+------+------+
Just like BX, except that it places a return link in R14.
CLZ{<cond>} <Rd>, <Rm>
31 28 27 20 19 16 15 12 11 8 7 4 3 0
+------+----------+------+------+------+------+------+
| cond | 00010110 | 1111 | Rd | 1111 | 0001 | Rm |
+------+----------+------+------+------+------+------+
Rd becomes equal to the number of consecutive leading zero bits
counting down from the top of Rm, ranging from 0 for negative values
(top bit = 1) to 32 for Rm being 0.
New Thumb instructions:
BKPT <immediate>
15 8 7 0
+----------+-------+
| 10111110 | immed |
+----------+-------+
Thumb equivalent of ARM BKPT instruction above.
BLX <label>
Like the Thumb BL instruction, this is actually made up from two
16-bit instructions. The first has bits[15:11] = 11110 and is
entirely identical to the first half of the BL instruction. The
second has bits[15:11] = 11101 (compared with 11111 for the BL
instruction). The differences from the Thumb BL instruction are:
* Control arrives at the destination in ARM state, compared with
Thumb state for a BL instruction.
* Bit[0] of the second instruction must be zero: basically, the
second instruction contains a 10-bit word offset rather than an
11-bit halfword offset.
* The destination address generated by the second instruction has
bit[1] cleared to ensure word-alignment of the address branched
to.
BLX <Rm>
15 7 6 5 3 2 0
+-----------+----+----+-----+
| 010001111 | H2 | Rm | 000 |
+-----------+----+----+-----+
Like the Thumb BX instruction, except it places a return link in
R14.
Hope this helps.
David Seal
email: David.Seal@arm.com
......@@ -83,6 +83,14 @@ ShowRegs_Help
ShowRegs_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= "", 0
ShowFPRegs_Help
= "*",TokenEscapeChar,Token0
= " displays the stored FPA registers."
= 13
ShowFPRegs_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= "", 0
|
BreakClr_Help DCB "HDBGBCL", 0
BreakClr_Syntax DCB "SDBGBCL", 0
......@@ -113,6 +121,9 @@ MemoryI_Syntax DCB "SDBGMMI", 0
ShowRegs_Help DCB "HDBGSHR", 0
ShowRegs_Syntax DCB "SDBGSHR", 0
ShowFPRegs_Help DCB "HDBGSFR", 0
ShowFPRegs_Syntax DCB "SDBGSFR", 0
]
ALIGN
......
......@@ -34,11 +34,11 @@ MKDIR = cdir
AS = aasm
CP = copy
RM = remove
WIPE = wipe
WIPE = -wipe
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend -Stamp -quit -module -To $@ -From
CPFLAGS = ~cfr~v
WFLAGS = ~c~v
WFLAGS = ~cr~v
TOKENISE = tokenise
TOKENS = Hdr:Tokens
......@@ -65,9 +65,7 @@ install_rom: $(TARGET)
@echo ${COMPONENT}: rom module installed
clean:
${WIPE} rm.${MACHINE} ${WFLAGS}
${RM} rm.${MACHINE}
${RM} rm
${WIPE} rm ${WFLAGS}
$(RM) $(TARGET)
$(RM) TokHelpSrc
@echo ${COMPONENT}: cleaned
......
No preview for this file type
......@@ -28,11 +28,13 @@ M63:*** RdHi=Rm
M64:*** Rn in list
M66:*** Rd=Rm
M67:*** Only 1 reg on SA-1 rev 2
M68:ARMv5 or later
M16:Store initialised to &
M17:Register dump (stored at &
M18:) is:
M19:Mode
M20: flags set:
M14: PSR =
M22:Address :
M23: ASCII Data
M24:Word at &
......@@ -58,3 +60,47 @@ M46:Invalid value
M48:No room in breakpoint table
M50:Bad breakpoint
M65:Unpredictable instruction
F00:infinity
F01:quiet NaN
F02:signalling NaN
F03: S Exp J Fraction S Exp J Fraction
F04:System:
F06:Control:
F05: Enabled exceptions:
F07: Cumulative exceptions:
FS00:Old FPE
FS01:FPE 400
FS80:FPPC
FS81:FPA
FSxx:unknown
NaN00:signalling NaN operand
NaN01:initial NaN
NaN02:massive overflow
NaN03:massive underflow
NaN04:infinity minus infinity
NaN05:infinity times zero
NaN06:zero times infinity
NaN07:zero divided by zero
NaN08:infinity / infinity
NaN09:RMF of infinity
NaN10:RMF by zero
NaN11:square root of negative
NaN12:FIX of quiet NaN
NaN13:FIX of infinity
NaN14:FIX range
NaN15:CMFE/CNFE of quiet NaN
NaN16:SIN/COS range
NaN17:SIN/COS of infinity
NaN18:TAN range
NaN19:TAN of infinity
NaN20:ASN/ACS range
NaN21:ASN/ACS of infinity
NaN22:POL on two zeros
NaN23:POL on two infinities
NaN24:LGN/LOG of negative
NaN25:bad POW/RPW of negative
NaN26:bad POW/RPW of zero
NaN27:bad POW/RPW on infinity
;
; This file is automatically maintained by srccommit, do not edit manually.
;
GBLS Module_MajorVersion
GBLA Module_Version
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
Module_MajorVersion SETS "1.59"
Module_Version SETA 159
Module_MinorVersion SETS ""
Module_Date SETS "20 Apr 1999"
Module_FullVersion SETS "1.59"
GBLS Module_MajorVersion
GBLA Module_Version
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
Module_MajorVersion SETS "1.60"
Module_Version SETA 160
Module_MinorVersion SETS ""
Module_Date SETS "02 May 2000"
Module_FullVersion SETS "1.60"
END
/* (1.59)
/* (1.60)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 1.59
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 20 Apr 1999
#define Module_MajorVersion_CMHG 1.60
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 02 May 2000
#define Module_MajorVersion "1.59"
#define Module_Version 159
#define Module_MinorVersion ""
#define Module_Date "20 Apr 1999"
#define Module_MajorVersion "1.60"
#define Module_Version 160
#define Module_MinorVersion ""
#define Module_Date "02 May 2000"
#define Module_FullVersion "1.59"
#define Module_FullVersion "1.60"
This diff is collapsed.
......@@ -42,7 +42,7 @@ Floating_Point
; iiiiiiii = 8-bit immediate offset
TST r4, #1 :SHL: 24 :OR: 1 :SHL: 21
BEQ Undefined ; Post-indexed, but no writeback!
BEQ Coprocessor_NotFP ; we don't use the "info" form
TestStr 20,Ldf,Stf,conds ; Load/~Store bit
......@@ -400,7 +400,7 @@ New_FPA
BNE Coprocessor_NotFP ;only coproc 2 codes so far are LFM/SFM
TST r4, #1 :SHL: 24 :OR: 1 :SHL: 21
BEQ Undefined ; Post-indexed, but no writeback!
BEQ Coprocessor_NotFP ; we don't use the "info" form
TestStr 20,Lfm,Sfm,conds
BL Tab
......@@ -421,4 +421,257 @@ New_FPA
B CPDT_Common ;drop into ordinary CPDT processing
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ShowFPRegs_Code
ENTRY "r6-r11",12
LDR wp, [r12]
SWI XFPEmulator_ExceptionDump
EXIT VS
MOV r5, r0
BL message_writes ; Display address of register dump
DCB "M17", 0 ; "Register dump (stored at &"
ALIGN
MOVVC r10, r0
BLVC DisplayHexWord
EXIT VS
BL message_writes
DCB "M18", 0 ; ") is:"
ALIGN
SWIVC XOS_NewLine
EXIT VS
BL message_writes
DCB "F03", 0 ; "S Exp J Fraction" headers
ALIGN
EXIT VS
RFS r1 ; save current FPSR
Push "r1"
MOV r1, #0 ; no exceptions
WFS r1
SFMFD f0, 1, [sp]! ; and save F0
MOV r4, #0
ADD r11, r5, #4
10 ; Display dumped registers in hex format first
TST r4, #1
SWIEQ XOS_NewLine
BVS ExitSFPR
BEQ %FT12
SWI XOS_WriteS
DCB " ", 0
ALIGN
12
SWIVC XOS_WriteI+"F"
ADDVC r0, r4, #"0"
SWIVC XOS_WriteC
BVS ExitSFPR
SWI XOS_WriteS
DCB " = ", 0
ALIGN
BVS ExitSFPR
LDR r3, [r11], #4 ; get extended value from dump
TST r3, #1:SHL:31 ; sign bit
SWIEQ XOS_WriteI+"0"
SWINE XOS_WriteI+"1"
SWIVC XOS_WriteI+" "
MOVVC r10, r3, LSL #17
MOVVC r10, r10, LSR #17 ; exponent
MOVVC r2, #12
BLVC DisplayHex
SWIVC XOS_WriteI + " "
BVS ExitSFPR
LDR r3, [r11], #4
TST r3, #1:SHL:31 ; J bit
SWIEQ XOS_WriteI+"0"
SWINE XOS_WriteI+"1"
SWIVC XOS_WriteI+" "
BICVC r10, r3, #1:SHL:31
BLVC DisplayHexWord
LDRVC r10, [r11], #4
BLVC DisplayHexWord
BVS ExitSFPR
ADD r4, r4, #1
TEQS r4, #8
BNE %BT10
SWI XOS_NewLine
BVS ExitSFPR
SWI XOS_WriteS
DCB "FPSR = ", 0
ALIGN
LDRVC r10, [r5]
BLVC DisplayHexWord
SWIVC XOS_NewLine
BVS ExitSFPR
MOV r4, #0
ADD r11, r5, #4
10 ; Followed by registers in decimal
TST r4, #1
BEQ %FT15
SWI XOS_WriteS
DCB " ", 0
B %FT16
15 SWI XOS_NewLine
16 BVS ExitSFPR
SWI XOS_WriteI+"F"
ADDVC r0, r4, #"0"
SWIVC XOS_WriteC
BVS ExitSFPR
SWI XOS_WriteS
DCB " = ", 0
BVS ExitSFPR
LDFE f0, [r11], #12 ; get extended value from dump
STFP f0, [sp, #16] ; and convert to expanded packed decimal
LDR r3, [sp, #16] ; r3 := sign + exponent
TST r3, #1:SHL:31
SWINE XOS_WriteI + "-"
MOVVC r10, r3, LSR #8
MOVVC r2, #0
BLVC DisplayHex
SWIVC XOS_WriteI + "."
MOVVC r10, r3
MOVVC r2, #4
BLVC DisplayHex
LDRVC r10, [sp, #20]
BLVC DisplayHexWord
LDRVC r10, [sp, #24]
BLVC DisplayHexWord
BVS ExitSFPR
BIC r10, r3, #&F0000000
MOVS r10, r10, LSR #12
BNE Exponent
TST r4, #1
BNE %FT40
SWI XOS_WriteS
DCB " ", 0
B %FT40
Exponent
SWI XOS_WriteI + "E"
BVS ExitSFPR
TST r3, #1:SHL:30
SWIEQ XOS_WriteI + "+"
SWINE XOS_WriteI + "-"
MOVVC r2, #12
BLVC DisplayHex
BVS ExitSFPR
40 ADD r4, r4, #1
TEQS r4, #8
BNE %BT10
SWI XOS_NewLine
; Now show the FPSR in human-readable form
BL message_writes ; "System: "
DCB "F04", 0
BVS ExitSFPR
MOV r0, #'F'
STRB r0, [sp, #-8]!
MOV r0, #'S'
STRB r0, [sp, #1]
LDR r10, [r5]
MOV r0, r10, LSR #24
ADD r1, sp, #2
MOV r2, #3
SWI XOS_ConvertHex2
MOVVC r0, sp
BLVC message_write0
ADD sp, sp, #8
ADRVS r0, FSxx
BLVS message_write0
BVS ExitSFPR
BL message_writes
DCB "F05", 0 ; " Enabled exceptions: "
MOV r5, r10, LSR #16
ADR r2, FPExceptList
BL ShowFPFlags
SWIVC XOS_NewLine
BVS ExitSFPR
BL message_writes
DCB "F06", 0 ; "Control:"
BVS ExitSFPR
MOV r5, r10
ADR r2, FPControlList
BL ShowFPFlags
BVS ExitSFPR
BL message_writes
DCB "F07", 0 ; " Cumulative exceptions:"
MOV r5, r10
ADR r2, FPExceptList
BL ShowFPFlags
SWIVC XOS_NewLine
ExitSFPR
LFMFD f0, 1, [sp]!
Pull "r1"
WFS r1 ; restore FPSR
EXIT
ShowFPFlags
Entry "r1"
MOV r1, #1
LDRB r14, [r2, #0]
10 TST r5, r1, LSL r14
LDRB r0, [r2, #1]
SWI XOS_WriteI + " "
ORREQ r0, r0, #&20
SWIVC XOS_WriteC
LDRB r0, [r2, #2]
ORREQ r0, r0, #&20
SWIVC XOS_WriteC
EXIT VS
LDRB r14, [r2, #3]!
TEQ r14, #255
BNE %BT10
EXIT
FPControlList
DCB AC_pos, "AC"
DCB EP_pos, "EP"
DCB SO_pos, "SO"
DCB NE_pos, "NE"
DCB ND_pos, "ND"
DCB 255
FPExceptList
DCB IXC_pos, "IX"
DCB UFC_pos, "UF"