Commit c8f22aa6 authored by Kevin Bracey's avatar Kevin Bracey

Modified ASCII display in *Memory etc to read memory using the same access...

Modified ASCII display in *Memory etc to read memory using the same access size as the main output. This helps with some hardware registers that only support, say, word-sized accesses. Note that the memory locations are still read a second time for the ASCII display, so it's still not ideal for read-sensitive hardware.

Added some ARMv6 support to disassembly, but this is incomplete and switched
out at the moment.

Version 1.77. Tagged as 'Debugger-1_77'
parent 302102ca
; arrive here with cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
; SMLAD/SMUAD etc cccc 0111 0xxx xxxx xxxx xxxx xxx1 xxxx
; USAD8/USADA8 cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx
; SMUAD/SMUSD cccc 0111 0000 dddd nnnn 1111 0sx1 ssss
; SMMUL cccc 0111 0101 dddd nnnn 1111 00r1 ssss
; SMMLA cccc 0111 0101 dddd ssss nnnn 00r1 ssss
; SMLALD cccc 0111 0100 dddd nnnn 1111 0001 ssss
; various cccc 0110 0xxx xooo xxxx xxxx xxx1 xxxx
; ADD/UNPK cccc 0110 1xxx xxxx xxxx xxxx 0111 xxxx
; PKH cccc 0110 1000 xxxx xxxx xxxx xx01 xxxx
; USAT/SSAT cccc 0110 1x1x xxxx xxxx xxxx xx01 xxxx
; USAT16/SSAT16 cccc 0110 1x10 xxxx xxxx xxxx xx11 xxxx
; SEL16/SEL8 cccc 0110 1000 xxxx xxxx xxxx x011 xxxx
; REVxx cccc 0110 1x11 xxxx xxxx xxxx x011 xxxx
; various cccc 0110 0xxx xooo xxxx xxxx xxx1 xxxx
; 0100
; ADD8 1001
; ADD16 0001
; ADDSUBX 0011
; SUB8 1111
; SUB16 0111
; SUBADDX 0101
; undefined 1101
; undefined 1011
; UH 0111
; UQ 0110
; U 0101
; SH 0011
; Q 0010
; S 0001
; REV cccc 0110 1011 1111 dddd 1111 0011 mmmm
; REV16 cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx
; REVSH cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx
; LDREX cccc 0001 1001 nnnn dddd 1111 1001 1111
; STREX cccc 0001 1000 nnnn dddd 1111 1001 mmmm
; SRS 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx
; RFE 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx
; SETEND 1111 0001 0000 xxx1 xxxx xxxx xxxx xxxx
; CPS 1111 0001 0000 xxxx xxxx xxxx xx0x xxxx
File added
......@@ -30,6 +30,7 @@ M66:*** Rd=Rm
M67:*** Only 1 reg on SA-1 rev 2
M68:ARMv5 or later
M69:ARMv5TE or later
M70:ARMv6 or later
M16:Store initialised to &
M17:Register dump (stored at &
M18:) is:
......
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.76"
Module_Version SETA 176
Module_MajorVersion SETS "1.77"
Module_Version SETA 177
Module_MinorVersion SETS ""
Module_Date SETS "03 Dec 2002"
Module_ApplicationDate SETS "03-Dec-02"
Module_Date SETS "30 Jul 2004"
Module_ApplicationDate SETS "30-Jul-04"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.76"
Module_HelpVersion SETS "1.76 (03 Dec 2002)"
Module_FullVersion SETS "1.77"
Module_HelpVersion SETS "1.77 (30 Jul 2004)"
END
/* (1.76)
/* (1.77)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.68.
*
*/
#define Module_MajorVersion_CMHG 1.76
#define Module_MajorVersion_CMHG 1.77
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 03 Dec 2002
#define Module_Date_CMHG 30 Jul 2004
#define Module_MajorVersion "1.76"
#define Module_Version 176
#define Module_MajorVersion "1.77"
#define Module_Version 177
#define Module_MinorVersion ""
#define Module_Date "03 Dec 2002"
#define Module_Date "30 Jul 2004"
#define Module_ApplicationDate "03-Dec-02"
#define Module_ApplicationDate "30-Jul-04"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.76"
#define Module_HelpVersion "1.76 (03 Dec 2002)"
#define Module_LibraryVersionInfo "1:76"
#define Module_FullVersion "1.77"
#define Module_HelpVersion "1.77 (30 Jul 2004)"
#define Module_LibraryVersionInfo "1:77"
; Copyright 2004 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; File: ARMv6.s
; Purpose: Disassembly of ARMv6 instructions
; Author: K Bracey
; History: 23-Feb-00: KJB: created
[ ARMv6
LdrexStrex ROUT
; arrive here with cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx
; format is cccc 0001 100l nnnn dddd 1111 1001 mmmm
;
; LDREX{cond} Rd,[Rn]
; STREX{cond} Rd,Rm,[Rn]
;
; where cccc = condition
; l = Load/~Store
; nnnn = Rn
; dddd = Rd
; mmmm = Rm (=1111 for LDREX)
AND r5, r4, #2_1111:SHL:8
TEQ r5, #2_1111:SHL:8
TSTEQS r4, #2_0110:SHL:20
BNE Undefined
[ WarnARMv6
MOV r14, #Mistake_ARMv6
STR r14, Mistake
]
TestStr 20,Ldrex,Strex,conds
MOV r9,r4,LSR #16
AND r9,r9,#2_1111 ; Rn
MOV R5,R4,LSR #12
AND r5,r5,#2_1111 ; Rd
AND r6,r4,#2_1111 ; Rm
; Rd=Rn & STREX -> unpredictable
TestBit 20
TEQEQS r5,r9
MOVEQ r14,#Mistake_RdRn
STREQ r14,Mistake
; Rm=Rd -> unpredictable
TEQS r6,r5
MOVEQ r14,#Mistake_RdRm
STREQ r14,Mistake
; any reg=R15 -> unpredictable
TEQS r5,#15
TEQNES r9,#15
MOVEQ r14,#Mistake_R15
STREQ r14,Mistake
BL Tab_Dis_Register
TestBit 20
MOVEQ r5, r6
BEQ SwpCommon1
; Load case - Rm field must be 15
TEQS r6, #15
BEQ SwpCommon2
B Undefined
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
maal
; Multiply-Accumulate-Accumulate long
; Arrive here with cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx
; Format is cccc 0000 0100 hhhh llll ssss 1001 mmmm
;
; UMAAL{cond}{S} RdLo,RdHi,Rm,Rs
;
; where cccc = condition
; hhhh = RdHi
; llll = RdLo
; ssss = Rs
; mmmm = Rm
;
; (RdHi,RdLo) := Rm*Rs + RdLo + RdHi
[ WarnARMv6
MOV r14, #Mistake_ARMv6 ; all instructions here are ARMv6
STR r14, Mistake
]
AddStr Umaal,,conds
Dis_RlRhRmRs
BL TabOrPushOver
MOV r5, r4, LSR #12 ; RdLo
AND r6, r5, #2_1111
BL Dis_Register
MOV r5, r4, LSR #16 ; RdHi
AND r7, r5, #2_1111
BL Comma_Dis_Register
MOV r5, r4 ; Rm
AND r8, r5, #2_1111
BL Comma_Dis_Register
MOV r5, r4, LSR #8 ; Rs
AND r9, r5, #2_1111
BL Comma_Dis_Register
; Can't use R15 as any register, unpredictable
; if RdLo=RdHi
LDR r14, Mistake
TEQS r6, r7
MOVEQ r14, #Mistake_RdLoRdHi
TEQS r6, #15
TEQNES r7, #15
TEQNES r8, #15
TEQNES r9, #15
MOVEQ r14, #Mistake_R15
STR r14, Mistake
B InstructionEnd
Ldrex DCB "LDREX", 0
Strex DCB "STREX", 0
Umaal DCB "UMAAL", 0
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ControlExtension_uncond
; arrive here with 1111 00i1 0xx0 xxxx xxxx xxxx rxxs xxxx
; (irs != 011)
;
[ WarnARMv6
MOV r14, #Mistake_ARMv6 ; all instructions here are ARMv6
STR r14, Mistake
]
; format is 1111 0001 0000 0001 0000 00e0 0000 0000
;
; SETEND <BE|LE>
;
; where e = BE/~LE
TSTS r4, #2_11111111
TSTEQS r4, #2_11111101:SHL:8
TSTEQS r4, #2_11111110:SHL:16
TSTEQS r4, #2_00001110:SHL:24
BNE Undefined
TestBit 16
BEQ Undefined
AddStr Setend
BL Tab
TestBit 9,"B","L"
AddChar "E"
B InstructionEnd
Setend DCB "SETEND",0
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UndefinedExtension ROUT
; arrive here with cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
[ WarnARMv6
MOV r14, #Mistake_ARMv6 ; all instructions here are ARMv6
STR r14, Mistake
]
TestBit 24
BNE Mulv6
TestBit 23
BEQ Parallel
; arrive here with cccc 0110 1xxx xxxx xxxx xxxx xxx1 xxxx
; will need to figure out best way of splitting as we add more opcodes
TSTS r4, #2_111 :SHL: 20
BEQ is_SEL
AND r5, r4, #2_011 :SHL: 20
TEQ r5, #2_011 :SHL: 20
BNE Undefined
AND r6, r4, #2_11 :SHL: 5
TEQ r6, #2_01 :SHL: 5
BNE Undefined
is_REV
; arrive here with cccc 0110 1x11 xxxx xxxx xxxx x011 xxxx
; format is cccc 0110 1s11 1111 dddd 1111 h011 mmmm
;
; <REV|REV16|REVSH>{cond} Rd,Rm
;
; where cccc = condition
; s = sign-extend
; dddd = Rd
; mmmm = Rm
; h = half-word (s=1 & h=0 is undefined)
AND r5, r4, #2_1111:SHL:8
TEQ r5, #2_1111:SHL:8
BNE Undefined
AND r5, r4, #2_1111:SHL:16
TEQ r5, #2_1111:SHL:16
BNE Undefined
TestBit 22
BNE %FT2
TestStr 7,Rev16,Rev,conds
B %FT3
2
TestBit 7
BEQ Undefined
AddStr RevSH,,conds
3
MOV r5, r4, LSR #12
AND r5, r5, #15
AND r6, r4, #15
TEQS r5, #15
TEQNES r6, #15
MOVEQ lr, #Mistake_R15
STREQ lr, Mistake
BL Tab_Dis_Register
MOV r5, r4
BL Comma_Dis_Register
B InstructionEnd
is_SEL
; arrive here with cccc 0110 1000 xxxx xxxx xxxx xxx1 xxxx
; format is cccc 0110 1000 nnnn dddd 0000 1011 mmmm
;
; SEL{cond} Rd,Rn,Rm
;
; where cccc = condition
; nnnn = Rn
; dddd = Rd
; mmmm = Rm
AND r5, r4, #2_11111111:SHL:4
TEQ r5, #2_00001011:SHL:4
BNE Undefined
AddStr Sel,,conds
BL Tab
B Dis_RdRnRm
Rev DCB "REV",0
Rev16 DCB "REV16",0
RevSH DCB "REVSH",0
Sel DCB "SEL",0
ALIGN
Parallel
; arrive here with cccc 0110 0xxx xxxx xxxx xxxx xxx1 xxxx
; format is cccc 0110 0ppp nnnn dddd 1111 ooo1 mmmm
;
; <S|Q|SH|U|UQ|UH><ADD8|ADD16|SUB8|SUB16|ADDSUBX|SUBADDX>{cond}
; Rd,Rn,Rm
;
; where cccc = condition
; ppp = prefix
; nnnn = Rn
; dddd = Rd
; ooo = op
; mmmm = Rm
ANDS r5, r4, #2_011:SHL:20
BEQ Undefined
AND r5, r4, #2_1111:SHL:8
TEQS r5, #2_1111:SHL:8
BNE Undefined
ADR r10,ParallelPrefixTAB-3
AND r5, r4, #2_111:SHL:20
ADD r5, r5, r5, LSL #1
ADD r10, r10, r5, LSR #20
BL SaveString
TSTS r8, #1:SHL:5 ; then bit 6 = bit 5
BNE Undefined
TestStr 6,ParSub,ParAdd
EOR r8, r4, r4, LSR #1
TSTS r8, #1:SHL:5
BEQ %FT01
; bit 5 != bit 6
TestBit 7
BNE Undefined
TestStr 5,ParSub,ParAdd
AddChar "X"
B %FT02
01
TestStr 7,Par8,Par16
02
BL Conditions
BL TabOrPushOver
Dis_RdRnRm
MOV r5, r4, LSR #12 ; Rd
AND r6, r5, #2_1111
BL Dis_Register
MOV r5, r4, LSR #16 ; Rn
AND r7, r5, #2_1111
BL Comma_Dis_Register
MOV r5, r4 ; Rm
AND r8, r5, #2_1111
BL Comma_Dis_Register
; Can't use R15 as any register
TEQS r6, #15
TEQNES r7, #15
TEQNES r8, #15
MOVEQ r14, #Mistake_R15
STREQ r14, Mistake
B InstructionEnd
ParallelPrefixTAB
DCB "S",0,0
DCB "Q",0,0
DCB "SH",0
DCB 0,0,0
DCB "U",0,0
DCB "UQ",0
DCB "UH",0
ParAdd DCB "ADD",0
ParSub DCB "SUB",0
Par8 DCB "8",0
Par16 DCB "16",0
ALIGN
Mulv6
; arrive here with cccc 0111 xxxx xxxx xxxx xxxx xxx1 xxxx
ANDS r5, r4, #2_1111:SHL:20
BEQ DualSignedMultiplySum
TEQS r5, #2_0100:SHL:20
BEQ DualSignedMultiplySumLong
TEQS r5, #2_0101:SHL:20
BEQ SignedMultiplyMSB
TEQS r5, #2_1000:SHL:20
BEQ SumAbsoluteDifferences
B Undefined
DualSignedMultiplySum
; arrive here with cccc 0111 0000 xxxx xxxx xxxx xxx1 xxxx
; format is cccc 0111 0000 dddd nnnn ssss 0sx1 mmmm
;
; <SMUAD|SMUSD>{X}{cond} Rd,Rm,Rs
; <SMLAD|SMLSD>{X}{cond} Rd,Rm,Rs,Rn
;
; where cccc = condition
; dddd = Rd
; nnnn = Rn (=1111 for SMUxD)
; ssss = Rs
; s = Subtract/~Add
; x = eXchange
; mmmm = Rm
;
; Rd = (RmLo*RsLo) +/- (RmHi*RsHi) [X swaps RsHi/RsLo]
; Rd = (RmLo*RsLo) +/- (RmHi*RsHi) + Rn
TestBit 7
BNE Undefined
AddChar "S"
AddChar "M"
AND r5, r4, #2_1111:SHL:12
TEQS r5, #2_1111:SHL:12
MOVEQ r10, #"U"
MOVNE r10, #"L"
STRB R10,[R0],#1
TestBit 6,"S","A"
AddChar "D"
TestBit 5,"X"
BL Conditions
BL TabOrPushOver
Dis_RdRmRs_OptRn
AND r8, r4, #15
MOV r6, r4, LSR #8
AND r6, r6, #15
MOV r5, r4, LSR #16
AND r5, r5, #15
TEQS r8, #15
TEQNES r6, #15
TEQNES r5, #15
MOVEQ r14, #Mistake_R15
STREQ r14, Mistake
BL Dis_Register
MOV r5, r4
BL Comma_Dis_Register
MOV r5, r4, LSR #8
BL Comma_Dis_Register
MOV r5, r4, LSR #12
AND r5, r5, #15
TEQ r5, #15
BLNE Comma_Dis_Register
B InstructionEnd
DualSignedMultiplySumLong
; arrive here with cccc 0111 0100 xxxx xxxx xxxx xxx1 xxxx
; format is cccc 0111 0100 hhhh llll ssss 0sx1 mmmm
;
; <SMLALD|SMLSLD>{X}{cond} RdLo,RdHi,Rm,Rs
;
; where cccc = condition
; hhhh = RdHi
; llll = RdLo
; ssss = Rs
; s = Subtract/~Add
; x = eXchange
; mmmm = Rm
;
; (RdHi,RdLo) += (RmLo*RsLo) +/- (RmHi*RsHi) [X swaps RsHi/RsLo]
TestBit 7
BNE Undefined
TestStr 6,Smlsld,Smlald
TestBit 5,"X"
BL Conditions
B Dis_RlRhRmRs
SignedMultiplyMSB
; arrive here with cccc 0111 0101 xxxx xxxx xxxx xxx1 xxxx
; format is cccc 0111 0101 dddd nnnn ssss ssr1 mmmm
;
; SMMUL{R}{cond} Rd,Rm,Rs
; <SMMLA|SMMLS>{R}{cond} Rd,Rm,Rs,Rn
;
; where cccc = condition
; dddd = Rd
; nnnn = Rn (=1111 for SMMUL)
; ssss = Rs
; ss = Subtract/~Add (=0 for SMMUL)
; r = Round
; mmmm = Rm
;
; Rd := (Rm*Rs).Hi
; Rd := (Rm*Rs).Hi +/- Rn
EOR r5, r4, r4, LSR #1
TSTS r5, #1:SHL:6
BNE Undefined ; bit 6 must equal bit 7
AND r5, r4, #2_1111:SHL:12
TEQ r5, #2_1111:SHL:12
BEQ %FT01
TestStr 6,Smmls,Smmla
B %FT02
01
AddStr Smmul
TestBit 6
BNE Undefined
02
TestBit 5,"R"
BL Conditions
BL TabOrPushOver
B Dis_RdRmRs_OptRn
SumAbsoluteDifferences
; arrive here with cccc 0111 1000 xxxx xxxx xxxx xxx1 xxxx
; format is cccc 0111 1000 dddd nnnn ssss 0001 mmmm
;
; USAD8{cond} Rd,Rm,Rs
; USADA8{cond} Rd,Rm,Rs,Rn
;
; where cccc = condition
; dddd = Rd
; nnnn = Rn (=1111 for USAD8)
; ssss = Rs
; a = Halfword/~Byte
; mmmm = Rm
;
; Rd = |Rm.3-Rs.3| + |Rm.2-Rs.2| + |Rm.1-Rs.1| + |Rm.0-Rs.0|
; Rd = |Rm.3-Rs.3| + |Rm.2-Rs.2| + |Rm.1-Rs.1| + |Rm.0-Rs.0| + Rn
TSTS r4, #2_111:SHL:5
BNE Undefined
AddStr Usad
AND r5, r4, #2_1111:SHL:12
TEQ r5, #2_1111:SHL:12
AddChar "A",NE
AddChar "8"
BL Conditions
BL TabOrPushOver
B Dis_RdRmRs_OptRn
Smmul DCB "SMMUL",0
Smmla DCB "SMMLA",0
Smmls DCB "SMMLS",0
Smlald DCB "SMLALD",0
Smlsld DCB "SMLSLD",0
Usad DCB "USAD",0
ALIGN
] ; ARMv6
LNK s.FP
......@@ -266,9 +266,15 @@ WarnARMv5 SETL True ; Indicate ARMv5 or later instructions
GBLL WarnARMv5E
WarnARMv5E SETL True
GBLL WarnARMv6
WarnARMv6 SETL True ; Indicate ARMv6 or later instructions
GBLL Thumb
Thumb SETL True
GBLL ARMv6
ARMv6 SETL False ; Don't do ARMv6 yet until complete
GBLL PhysAddr ; allow physical address spec in *memory etc.
PhysAddr SETL {TRUE} :LAND: Thumb
......@@ -386,6 +392,7 @@ Mistake_RdRm # 1
Mistake_STMHat # 1
Mistake_ARMv5 # 1
Mistake_ARMv5E # 1
Mistake_ARMv6 # 1
^ -1
Potential_SWICDP # -1
......@@ -1278,7 +1285,11 @@ LdrStr ROUT
; both LDR and PLD.
TST r4, #1 :SHL: 25 ; If Rm and shift and trying Rs
TSTNE r4, #1 :SHL: 4 ; then that was xxR Rd,[Rn,Rm,SHF Rs]
[ ARMv6
BNE UndefinedExtension ; but ARM2 doesn't do that anymore
|
BNE Undefined ; but ARM2 doesn't do that anymore
]
MOV r14, r4, LSR #28
TEQ r14, #15
......@@ -1434,12 +1445,6 @@ CPDT_info
B %BT80
Ldr DCB "LDR", 0
Str DCB "STR", 0
Open_B DCB ",[", 0
Close_B DCB "],", 0
Pld DCB "PLD", 0
Preload ROUT
; Preload
; arrive here with 1111 01xx xxxx xxxx xxxx xxxx xxxx xxxx
......@@ -1474,12 +1479,17 @@ Preload ROUT
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Mull DCB "MULL",0
ALIGN
Mlal DCB "MLAL",0
ALIGN
Mul DCB "MUL", 0
Mla DCB "MLA", 0
aswp DCB "SWP", 0
ALIGN
Ldr DCB "LDR", 0
Str DCB "STR", 0
Open_B DCB ",[", 0
Close_B DCB "],", 0
Pld DCB "PLD", 0
UndefinedDataProcessing ROUT
; Arrive here with cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx
......@@ -1495,7 +1505,12 @@ ArithmeticExtension
BHS mul_long ; opcode 8-15 = long multiply
CMP R5,#2_0100:SHL:20
[ ARMv6
BEQ maal ; opcode 4 = long multiply accumulatee accumulate
BHI Undefined ; opcode 5-7 undefined
|
BHS Undefined ; opcode 4-7 undefined
]
; Multiply + Multiply-with-Accumulate
; Arrive here with cccc 0000 00xx xxxx xxxx xxxx 1001 xxxx
......@@ -1620,6 +1635,15 @@ mul_long
B InstructionEnd
swp_type
; arrive here with cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx
TestBit 23
[ ARMv6
BNE LdrexStrex
|
BNE Undefined
]
swp
; Swap register/memory
; arrive here with cccc 0001 0xxx xxxx xxxx xxxx 1001 xxxx
......@@ -1647,52 +1671,40 @@ swp
MOV R5,R4,LSR #12
AND r5,r5,#2_1111 ; Rd
; Rd=R15 -> unpredictable
TEQS r5,#15
MOVEQ r14,#Mistake_R15
STREQ r14,Mistake
; Rd=Rn -> unpredictable
TEQS r5,r9
MOVEQ r14,#Mistake_RdRn
STREQ r14,Mistake
BL Tab_Dis_Register
AND R5,R4,#2_1111 ; Rm
; Rm=R15 -> unpredictable
; Rd/Rn=R15 -> unpredictable
TEQS r5,#15
TEQNES r9,#15
MOVEQ r14,#Mistake_R15
STREQ r14,Mistake
BL Tab_Dis_Register
AND R5,R4,#2_1111 ; Rm
; Rm=Rn -> unpredictable
TEQS r5,r9
MOVEQ r14,#Mistake_RmRn
STREQ r14,Mistake
BL Comma_Dis_Register
AddStr Open_B
MOV r5,r9 ; Rn
; Rn=R15 -> unpredictable
SwpCommon1
; Rm=R15 -> unpredictable
TEQS r5,#15
MOVEQ r14,#Mistake_R15