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Commit 8244d65e authored by Kevin Bracey's avatar Kevin Bracey
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Lots of bug fixes and extra warnings. Source code tidied. 

Thumb disassembly added.
parent 1cdf2627
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Showing with 2251 additions and 1074 deletions
!run,feb deleted 100644 → 0
View file @ 1cdf2627
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
set debugger$path <obey$dir>
set object$path <obey$dir>.rm
iconsprites <debugger$path>.!sprites
Set Alias$Filer Filer_OpenDir <obey$dir>
Filer
HelpSrc
View file @ 8244d65e
......@@ -70,11 +70,11 @@ MemoryA_Syntax
MemoryI_Help
= "*",TokenEscapeChar,Token0
= " disassembles ARM instructions."
= " disassembles ARM or Thumb instructions."
= 13
MemoryI_Syntax
= "Syntax: *",TokenEscapeChar,Token0
= " <addr1|reg1> [[+|-] <addr2|reg2> [+ <addr3|reg3>]]", 0
= " [T] <addr1|reg1> [[+|-] <addr2|reg2> [+ <addr3|reg3>]]", 0
ShowRegs_Help
= "*",TokenEscapeChar,Token0
......
!boot,feb → MakeMess,fd7
View file @ 8244d65e
| Copyright 1996 Acorn Computers Ltd
| Copyright 1997 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
......@@ -12,6 +12,5 @@
| See the License for the specific language governing permissions and
| limitations under the License.
|
set debugger$path <obey$dir>
set object$path <obey$dir>.rm
iconsprites <debugger$path>.!sprites
Dir <Obey$Dir>
ModGen rm.DbgMess DebuggerMessages "Debugger Msgs" 0.01 Resources.<Locale>.Messages Resources.Debugger.Messages
Makefile
View file @ 8244d65e
......@@ -64,7 +64,7 @@ install_rom: $(TARGET)
clean:
$(RM) $(TARGET)
$(RM) s.TokHelpSrc
$(RM) TokHelpSrc
@echo ${COMPONENT}: cleaned
resources:
......
Resources/UK/Messages
View file @ 8244d65e
No preview for this file type
Syntax deleted 100644 → 0
View file @ 1cdf2627
00:Syntax: *BreakClr [<addr|reg>]
01:Syntax: *BreakList
02:Syntax: *BreakSet <addr|reg>
03:Syntax: *Continue
04:Syntax: *Debug
05:Syntax: *InitStore
06:Syntax: *Memory [B] <addr1|reg1> [[+|-] <addr2|reg2> [+ <addr3|reg3>]]
07:Syntax: *MemoryA [B] <addr|reg1> [<data|reg2>]
08:Syntax: *MemoryI <addr1|reg1> [[+|-] <addr2|reg2> [+ <addr3|reg3>]]\r\
09:Syntax: *ShowRegs
TokHelpSrc deleted 100644 → 0
View file @ 1cdf2627
TTL ==> TokHelpSrc
SUBT > <wini>arm.Debugger.HelpSrc
[ International_Help = 0
BreakClr_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0," removes",TokenEscapeChar,Token2
= "breakpoint at",TokenEscapeChar,Token2,"specified address. If"
= " no address",TokenEscapeChar,Token41,"given then"
= TokenEscapeChar,Token38,"breakpoints are removed.", 13
;= " removes the breakpoint at the specified address."
;= " If no address is given then all breakpoints are removed."
;= 13
BreakClr_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token30,"<addr|reg>]", 0
;= " [<addr|reg>]", 0
BreakList_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0," lists all",TokenEscapeChar,Token2
= TokenEscapeChar,Token5,"ly set breakpoints.", 13
;= " lists all the currently set breakpoints."
;= 13
BreakList_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token1, 0
;= "", 0
BreakSet_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0," sets a breakpoint at"
= TokenEscapeChar,Token2,"given address.", 13
;= " sets a breakpoint at the given address."
;= 13
BreakSet_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token14,"addr|reg>", 0
;= " <addr|reg>", 0
Continue_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0," restarts execu"
= TokenEscapeChar,Token9," from",TokenEscapeChar,Token2,"bre"
= "akpoint saved state.", 13
;= " restarts execution from the breakpoint saved state."
;= 13
Continue_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token1, 0
;= "", 0
Debug_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0," gives access"
= TokenEscapeChar,Token40,"debugging facilities.", 13
;= " gives access to debugging facilities."
;= 13
Debug_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token1, 0
;= "", 0
InitStore_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0," fills user memory with"
= TokenEscapeChar,Token2,"specified data, or"
= TokenEscapeChar,Token2,"value &E6000010 (an illegal ARM inst"
= "ruc",TokenEscapeChar,Token9,") if no ",TokenEscapeChar,Token36
= TokenEscapeChar,Token41,"given.", 13
;= " fills user memory with the specified data,"
;= " or the value &E6000010 (an illegal ARM instruction) if no"
;= " parameter is given."
;= 13
InitStore_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token30,"<data|reg>]", 0
;= " [<data|reg>]", 0
Memory_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0,TokenEscapeChar,Token32
= TokenEscapeChar,Token2,"values in",TokenEscapeChar,Token2,"m"
= "emory in ARM words.", 13
;= " displays the values in the memory in ARM words."
;= 13
Memory_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token30,"B] <addr1|reg1> [[+|-] <addr2|reg2> "
= "[+ <addr3|reg3>]]", 0
;= " [B] <addr1|reg1> [[+|-] <addr2|reg2> [+ <addr3|reg3>]]", 0
MemoryA_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0,TokenEscapeChar,Token32
= TokenEscapeChar,Token16,"alters",TokenEscapeChar,Token2,"me"
= "mory contents in bytes or words.", 13
;= " displays and alters the memory contents in bytes or words."
;= 13
MemoryA_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token30,"B] <addr|reg1> [<data|reg2>]", 0
;= " [B] <addr|reg1> [<data|reg2>]", 0
MemoryI_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0," disassembles ARM instruc"
= TokenEscapeChar,Token9,"s.", 13
;= " disassembles ARM instructions."
;= 13
MemoryI_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token14,"addr1|reg1> [[+|-] <addr2|reg2> [+ <"
= "addr3|reg3>]]", 0
;= " <addr1|reg1> [[+|-] <addr2|reg2> [+ <addr3|reg3>]]", 0
ShowRegs_Help
;= "*",TokenEscapeChar,Token0
= "*",TokenEscapeChar,Token0,TokenEscapeChar,Token32
= TokenEscapeChar,Token2,"stored ARM registers.", 13
;= " displays the stored ARM registers."
;= 13
ShowRegs_Syntax
;= "Syntax: *",TokenEscapeChar,Token0
= TokenEscapeChar,Token1, 0
;= "", 0
|
BreakClr_Help DCB "HDBGBCL", 0
BreakClr_Syntax DCB "SDBGBCL", 0
BreakList_Help DCB "HDBGBLS", 0
BreakList_Syntax DCB "SDBGBLS", 0
BreakSet_Help DCB "HDBGBST", 0
BreakSet_Syntax DCB "SDBGBST", 0
Continue_Help DCB "HDBGCNT", 0
Continue_Syntax DCB "SDBGCNT", 0
Debug_Help DCB "HDBGDBG", 0
Debug_Syntax DCB "SDBGDBG", 0
InitStore_Help DCB "HDBGINS", 0
InitStore_Syntax DCB "SDBGINS", 0
Memory_Help DCB "HDBGMEM", 0
Memory_Syntax DCB "SDBGMEM", 0
MemoryA_Help DCB "HDBGMMA", 0
MemoryA_Syntax DCB "SDBGMMA", 0
MemoryI_Help DCB "HDBGMMI", 0
MemoryI_Syntax DCB "SDBGMMI", 0
ShowRegs_Help DCB "HDBGSHR", 0
ShowRegs_Syntax DCB "SDBGSHR", 0
]
ALIGN
END
Version
View file @ 8244d65e
SUBT > <wini>arm.Debugger.Version
GBLS Version
Version SETS "1.48"
Version SETS "1.52"
GBLS CurrentDate
CurrentDate SETS "02 Jul 1996"
CurrentDate SETS "06 Nov 1996"
END
hdr/Debugger
View file @ 8244d65e
......@@ -24,12 +24,14 @@ OldOpt SETA {OPT}
; Date Name Description
; ---- ---- -----------
; 17-May-94 AMcC Changed to using the preferred SWI base and name symbols
; 26-Jun-96 KJB Added DisassembleThumb
SWIClass SETS DebuggerSWI_Name
^ DebuggerSWI_Base
AddSWI Disassemble
AddSWI DisassembleThumb
OPT OldOpt
END
s/Debugger
View file @ 8244d65e
This diff is collapsed.
s/FP 0 → 100644
View file @ 8244d65e
; Copyright 1997 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; File: FP.s
; Purpose: Disassembly of the floating point instruction set
; Author: K Bracey
; History: 29-Oct-96: KJB: split off from Debugger.s
Floating_Point
; arrive here with cccc 11oo xxxx xxxx xxxx 0001 xxxx xxxx
; where oo <> 11
CMP r3, #&0E
BEQ Floating_processing
; Floating Point Data Transfer (FPDT)
; format is cccc 110p uywl nnnn xddd 0001 iiii iiii
;
; <LDF|STF>{cond}<S|D|E|P> Fd,[Rn,#imm]{!}
; <LDF|STF>{cond}<S|D|E|P> Fd,[Rn],#imm
;
; where cccc = condition
; p = Pre-indexing/~Post-indexing
; u = Up/~Down
; yx = transfer length (S,D,E or P)
; w = Writeback
; l = Load/~Store
; nnnn = Rn
; ddd = Fd
; iiiiiiii = 8-bit immediate offset
TST r4, #1 :SHL: 24 :OR: 1 :SHL: 21
BEQ Undefined ; Post-indexed, but no writeback!
TestStr 20,Ldf,Stf,conds ; Load/~Store bit
AND r14, r4, #1 :SHL: 15 ; FPDT precision bits (Y,X)
MOV r14, r14, LSR #15
AND r10, r4, #1 :SHL: 22
ORR r14, r14, r10, LSR #22-1
ADR r10, fp_prec
LDRB r10, [r10, r14]
STRB r10, [r0], #1
BL Tab
MOV r5, r4, LSR #12 ; Fd
BL Dis_F_Register
B CPDT_Common
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Floating_processing ROUT
; arrive here with cccc 1110 xxxx xxxx xxxx 0001 xxxx xxxx
TSTS r4, #1 :SHL: 19
TSTNES r4, #1 :SHL: 7
BNE Coprocessor_NotFP ; Silly precision
TST r4, #1 :SHL: 4 ; Transfer/~Operation bit
BNE Floating_Register_Transfer
; Floating Point Data Operation (FPDO)
; arrive here with cccc 1110 xxxx exxx xxxx 0001 fxx0 xxxx
; with ef <> 11
;
; format is cccc 1110 abcd ennn jddd 0001 fgh0 immm
;
; <Dyadic op>{cond}<S|D|E>{P|M|Z} Fd,Fn,<Fm|#constant>
; <Monadic op>{cond}<S|D|E>{P|M|Z} Fd,<Fm|#constant>
;
; where cccc = condition
; abcd = opcode
; ef = destination size
; gh = rounding mode
; immm = Fm/constant
; nnn = Fn
; ddd = Fd
; j = Monadic/~Dyadic
MOV R6, #Potential_SWICDP_Next
STR R6, Mistake
AND r6, r4, #2_01111:SHL:20 ; FPOpc
TestBit 15
BEQ %FT05
ORR r6, r6, #2_10000:SHL:20 ; jabcde
TST r4, #2_111:SHL:16 ; Check Fn=F0 for monadic opcodes
BNE Coprocessor_NotFP
5 CMP r6, #12:SHL:20
BLS %FT01
CMP r6, #15:SHL:20
BLS Coprocessor_NotFP
01 ADR r1, Floating_Operations
BL FPRT_FPDO_Common
MOV r5, r4, LSR #12 ; Fd
BL Dis_F_Register
TestBit 15
BNE Dis_FmOrConstant ; [unary op]
BL AddComma
B Dis_Fn_FmOrConstant
LTORG
Ldf DCB "LDF", 0
Stf DCB "STF", 0
Lfm DCB "LFM", 0
Sfm DCB "SFM", 0
Floating_Operations
DCB "ADF" ; 0 ... binary ops
DCB "MUF" ; 1
DCB "SUF" ; 2
DCB "RSF" ; 3
DCB "DVF" ; 4
DCB "RDF" ; 5
DCB "POW" ; 6
DCB "RPW" ; 7
DCB "RMF" ; 8
DCB "FML" ; 9
DCB "FDV" ; 10
DCB "FRD" ; 11
DCB "POL" ; 12
DCB "F0D" ; 13 ... undefined binary ops
DCB "F0E" ; 14
DCB "F0F" ; 15
DCB "MVF" ; 16 ... unary ops
DCB "MNF" ; 17
DCB "ABS" ; 18
DCB "RND" ; 19
DCB "SQT" ; 20
DCB "LOG" ; 21
DCB "LGN" ; 22
DCB "EXP" ; 23
DCB "SIN" ; 24
DCB "COS" ; 25
DCB "TAN" ; 26
DCB "ASN" ; 27
DCB "ACS" ; 28
DCB "ATN" ; 29
DCB "URD" ; 30
DCB "NRM" ; 31
fp_round
DCB 0, "PMZ"
fp_prec
DCB "SDEP"
Floating_Transfers
DCB "FLT" ; 0/L
DCB "FIX" ; 0/S
DCB "WFS" ; 1/L
DCB "RFS" ; 1/S
DCB "WFC" ; 2/L
DCB "RFC" ; 2/S
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
FPRT_FPDO_Common ENTRY
ADD r6, r6, r6, LSL #1 ; *3
ADD r1, r1, r6, LSR #20
LDRB r10, [r1], #1
STRB r10, [r0], #1
LDRB r10, [r1], #1
STRB r10, [r0], #1
LDRB r10, [r1], #1
STRB r10, [r0], #1
BL Conditions
TestBit 4
BEQ %FT01 ; FPDO always has precision bits
ANDS r14, r4, #2_1111 :SHL: 20
BEQ %FT01 ; FLT has precision
CMPS r14, #2_0110 :SHL: 20
BLO %FT02 ; WFS etc don't have precision
; Show precision for undefined instructions
01 AND r14, r4, #1 :SHL: 7 ; FPDO/FPRT precision bits (e,f)
MOV r14, r14, LSR #7
AND r10, r4, #1 :SHL: 19
ORR r14, r14, r10, LSR #19-1
ADR r10, fp_prec
LDRB r10, [r10, r14]
STRB r10, [r0], #1
; WFS etc don't use the rounding bits, but they should be set
; to zero anyway, so don't bother checking
02 ANDS r14, r4, #2_11 :SHL: 5
ADRNE r10, fp_round
LDRNEB r10, [r10, r14, LSR #5]
STRNEB r10, [r0], #1
04 BL Tab
EXIT
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Floating Point Register Transfer (FPRT)
; arrive here with cccc 1110 xxxx exxx xxxx 0001 fxx1 xxxx
; with ef <> 11
;
; format is cccc 1110 abcl ennn dddd 0001 fgh1 0mmm
;
; FLT{cond}<S|D|E>{P|M|Z} Fn,Rd
; FIX{cond}{P|M|Z} Rd,Fm
; <WFS|RFS|WFC|RFC>{cond} Rd
;
; where cccc = condition
; l = Load/~Store
; abc = operation abcl abcl
; 0000 FLT 0001 FIX
; 0010 WFS 0011 RFS
; 0100 WFC 0101 RFC
; 1xx1 may be compare
; ef = destination size (FLT only)
; gh = rounding mode (FLT and FIX only)
; nnn = Fn (FLT only)
; mmm = Fm (FIX only)
; dddd = Rd
Floating_Register_Transfer ROUT
; Check for CMF (abc=4-7, Rd=R15, efgh=0000)
LDR r2, =&0E98FFF0
LDR r10, =&0E90F110
AND r2, r4, r2
CMP r2, r10
BEQ Floating_Status_Transfer
AND r6, r4, #2_1111 :SHL: 20 ; FPOpc + L
CMP r6, #6 :SHL: 20
BHS Coprocessor_NotFP ; Show undefined as simple MCR/MRC
ADR r1, Floating_Transfers ; Needed by FPRT_FPDO_Common
CMP r6, #1 :SHL: 20
BLO FPRT_FLT
BEQ FPRT_FIX
FPRT_RFSetc
TSTS r4, #2_11101111 ; WFS etc can't have bits 0-3,5-7,16-19 set
BNE Coprocessor_NotFP
TSTS r4, #2_1111:SHL:16
BNE Coprocessor_NotFP
; arrive here with cccc 1110 0bcl 0000 dddd 0001 0001 0000 (bc <> 11)
BL FPRT_FPDO_Common
MOV r5, r4, LSR #12
BL Dis_Register ; Rd
B InstructionEnd
FPRT_FIX
TSTS r4, #1:SHL:3 :OR: 1:SHL:7
BNE Coprocessor_NotFP ; FIX can't have bits 3,7,16-19 set
TSTS r4, #2_1111:SHL:16
BNE Coprocessor_NotFP
; arrive here with cccc 1110 0001 0000 dddd 0001 0gh1 0mmm
BL FPRT_FPDO_Common
MOV r5, r4, LSR #12
BL Dis_Register ; Rd (destination ARM register)
BL Dis_FmOrConstant ; Fm (source FP register)
B InstructionEnd
FPRT_FLT
TSTS r4, #2_1111 ; FLT can't have bits 0-3 set
BNE Coprocessor_NotFP
; arrive here with cccc 1110 0000 ennn dddd 0001 fgh1 0000
BL FPRT_FPDO_Common
MOV r5, r4, LSR #16
BL Dis_F_Register ; Fn (destination FP register)
MOV r5, r4, LSR #12
BL Comma_Dis_Register ; Rd (source ARM register)
B InstructionEnd
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Floating Point Status Transfer
Cmf DCB "CMF", 0
Cnf DCB "CNF", 0
ALIGN
Floating_Status_Transfer
; Floating point compare
; arrive here with cccc 1110 1xx1 0xxx 1111 0001 0001 xxxx
;
; format is cccc 1110 1en1 0nnn 1111 0001 0001 immm
;
; <CMF|CNF>{E}{cond} Fn,Fm
; <CMF|CNF>{E}{cond} Fn,#constant
;
; where cccc = condition
; e = Exception
; n = CNF/~CMF
; nnn = Fn
; immm = Fm/constant
TestStr 21,Cnf,Cmf ; Negated compare/~Compare bit
TestBit 22,"E" ; Exception bit
BL Conditions
BL Tab
; .............................................................................
Dis_Fn_FmOrConstant
MOV r5, r4, LSR #16 ; Fn
BL Dis_F_Register
; .............................................................................
Dis_FmOrConstant ROUT
BL AddComma
TST r4, #2_1000 ; Immediate operand ?
BNE %FT50
AND r5, r4, #2_0111 ; Fm
BL Dis_F_Register
B InstructionEnd
50
AddChar "#"
AND r8, r4, #2_0111 ; 3 bits instead of Fm
CMPS r8, #6 ; 0..7 -> 0,1,2,3,4,5,0.5,10
ADREQ r10, Pt5 ; 0.5
BEQ SaveStringEnd
MOVHI r8, #10
BL StoreDecimal
B InstructionEnd
Pt5 DCB "0.5", 0
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
New_FPA
; arrive here with cccc 11oo xxxx xxxx xxxx 0010 xxxx xxxx
; where oo <> 11
;
; format is cccc 110p uywl nnnn xddd 0010 iiii iiii
;
; <LFM|SFM>{cond} Fd,count,[Rn, #imm]{!}