Commit 9371049f authored by Steve Revill's avatar Steve Revill
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Fixed ADR and modified SWI disassembly.

Detail:
  ADDS Rd,PC,#.. and SUBS Rd,PC,#.. were being incorrectly disassembled
  as ADR pseudo-instructions. Fixed.

  Unknown SWIs (such as OS_Undefined and User) are disassembled in the
  form 'SWI &<num>' so that you can re-assemble the code (and it makes
  more sense if you don't have a module loaded which defined that SWI).
Admin:
  Tested on RiscPC

  I also added some notes on ARM v5TE to the Doc directory. May be of
  some use when adding compatibility for that to Debugger.

Version 1.63. Tagged as 'Debugger-1_63'
parent 9f3e2d5e
ARM v5TE Instruction Set
~~~~~~~~~~~~~~~~~~~~~~~~
The following table shows the various classes of instruction in the ARM v5TE instruction set. These are ordered in
decreasing order of 'clarity'. For example, the instruction which we can most easily identify is the preload because
it has 14 bits defined to be either 0 or 1. Classes with an equal 'clarity' are ordered by the number of bits which
are defined as being "should be zero" (SBZ) or "should be one" (SBO).
The difference between the bits defined as 0 or 1 and the SBZ/SBO bits is that the instructions which have bits set
incorrectly in the SBZ/SBO fields are defined to be 'unpredictable' and are not 'undefined' instructions. The
Debugger module does not, at present, distinguish between these two cases.
This table exists as a reference for creating a CASE (switch) statement which can easily determine the instruction
class by testing the bit patterns in the order given here. Of course, some hard-wired hashing could be employed to
speed this operation up.
Class: Bits: Count œ:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|
Preload | 1 1 1 1 0 1| I| 1| U| 1 0 1| Rn | 1 1 1 1| addressing mode | 14
Count leading zeros | condit | 0 0 0 1 0 1 1 0| SBO | Rd | SBO | 0 0 0 1| Rm | 12 (4+4)
Software breakpoint | condit | 0 0 0 1 0 0 1 0| immediate | 0 1 1 1| immediate | 12
Branch (link)/exchange instruction set | condit | 0 0 0 1 0 0 1 0| SBO | SBO | SBO | 0 0| L| 1| Rm | 11 (4+4+4)
Swap (byte) | condit | 0 0 0 1 0| B| 0 0| Rn | Rd | SBZ | 1 0 0 1| Rm | 11 (4)
Enhanced DSP add/subtracts | condit | 0 0 0 1 0| opc | 0| Rn | Rd | SBZ | 0 1 0 1| Rm | 10 (4)
Multiply (accumulate) | condit | 0 0 0 0 0 0| A| S| Rd | Rn | Rs | 1 0 0 1| Rm | 10
Multiply (accumulate) long | condit | 0 0 0 0 1| U| A| S| RdHi | RdLo | Rs | 1 0 0 1| Rm | 9
Move register to status register | condit | 0 0 0 1 0| R| 1 0| Mask | SBO | SBZ | 0| Rm | 8 (4+7)
Ld/st halfword register offset | condit | 0 0 0| P| U| 0| W| L| Rn | Rd | SBZ | 1 0 1 1| Rm | 8 (4)
Ld signed hlfwd/byte register offset | condit | 0 0 0| P| U| 0| W| 1| Rn | Rd | SBZ | 1 1| H| 1| Rm | 8 (4)
Enhanced DSP multiplies | condit | 0 0 0 1 0| opc | 0| Rd | Rn | Rs | 1| x| y| 0| Rm | 8
Ld/st halfword immediate offset | condit | 0 0 0| P| U| 1| W| L| Rn | Rd | Hi offset | 1 0 1 1| Lo offset | 8
Ld/st two words register offset | condit | 0 0 0| P| U| 0| W| 0| Rn | Rd | Hi offset | 1 1| S| 1| Lo offset | 8
Ld/st two words immediate offset | condit | 0 0 0| P| U| 1| W| 0| Rn | Rd | Hi offset | 1 1| S| 1| Lo offset | 8
Ld signed hlfwd/byte immediate offset | condit | 0 0 0| P| U| 1| W| 1| Rn | Rd | Hi offset | 1 1| H| 1| Lo offset | 8
Undefined instruction | 1 1 1 1 1 1 1 1| x x x x x x x x x x x x x x x x x x x x x x x x| 8
Move status register to register | condit | 0 0 0 1 0| R| 0 0| SBO | Rd | SBZ | 7 (4+12)
Move immediate to status register | condit | 0 0 1 1 0| R| 1 0| Mask | SBO | rotate | immediate value | 7 (4)
Undefined instruction | condit | 0 0 1 1 0| x| 0 0| x x x x x x x x x x x x x x x x x x x x| 7
Undefined instruction | 1 1 1 1 1 0 0| x x x x x x x x x x x x x x x x x x x x x x x x x| 7
Branch (with link) and into thumb | 1 1 1 1 1 0 1| H| 24 bit, 2s-complement, signed offset | 7
Coprocessor data processing | condit | 1 1 1 0| opcode1 | CRn | CRd | cp_num | opcode2| 0| CRm | 5
Coprocessor register transfers | condit | 1 1 1 0| opcode1| L| CRn | Rd | cp_num | opcode2| 1| CRm | 5
Data processing (register shift) | condit | 0 0 0| opcode | S| Rn | Rd | Rs | 0| shf | 1| Rm | 5
Data processing (immediate shift) | condit | 0 0 0| opcode | S| Rn | Rd | immediate | shf | 0| Rm | 4
Load/store register offset | condit | 0 1 1| P| U| B| W| L| Rn | Rd | immediate | shf | 0| Rm | 4
Undefined instruction | condit | 0 1 1| x x x x x x x x x x x x x x x x x x x x| 1| x x x x| 4
Software interrupt | condit | 1 1 1 1| swi number | 4
Data processing (immediate) | condit | 0 0 1| opcode | S| Rn | Rd | rotate | immediate value | 3
Load/store immediate offset | condit | 0 1 0| P| U| B| W| L| Rn | Rd | immediate value | 3
Load/store multiple | condit | 1 0 0| P| U| S| W| L| Rn | Register list | 3
Branch (with link) | condit | 1 0 1| L| 24 bit, 2s-complement, signed offset | 3
Coprocessor load and store | condit | 1 1 0| P| U| N| W| L| Rn | CRd | cp_num | 8 bit offset | 3
-------------------------------------------------------------------------------------------------
œ Count = the number of bits fixed as being 0 or 1 in this class and
the number of SBO or SBZ bits in this class (bracketed).
Masks to AND with an instruction to determine the class...
Preload 2_11111101011100001111000000000000
Count leading zeros 2_00001111111100000000000011110000
Software breakpoint 2_00001111111100000000000011110000
Branch (link)/exchange instruction set 2_00001111111100000000000011010000
Swap (byte) 2_00001111101100000000000011110000
Enhanced DSP add/subtracts 2_00001111100100000000000011110000
Multiply (accumulate) 2_00001111110000000000000011110000
Multiply (accumulate) long 2_00001111100000000000000011110000
Move register to status register 2_00001111101100000000000000010000
Ld/st halfword register offset 2_00001110010000000000000011110000
Ld signed hlfwd/byte register offset 2_00001110010100000000000011010000
Enhanced DSP multiplies 2_00001111100100000000000010010000
Ld/st halfword immediate offset 2_00001110010000000000000011110000
Ld/st two words register offset 2_00001110010100000000000011010000
Ld/st two words immediate offset 2_00001110010100000000000011010000
Ld signed hlfwd/byte immediate offset 2_00001110010100000000000011010000
Undefined instruction 2_11111111000000000000000000000000
Move status register to register 2_00001111101100000000000000000000
Move immediate to status register 2_00001111101100000000000000000000
Undefined instruction 2_00001111101100000000000000000000
Undefined instruction 2_11111110000000000000000000000000
Branch (with link) and into thumb 2_11111110000000000000000000000000
Coprocessor data processing 2_00001111000000000000000000010000
Coprocessor register transfers 2_00001111000000000000000000010000
Data processing (register shift) 2_00001110000000000000000010010000
Data processing (immediate shift) 2_00001110000000000000000000010000
Load/store register offset 2_00001110000000000000000000010000
Undefined instruction 2_00001110000000000000000000010000
Software interrupt 2_00001111000000000000000000000000
Data processing (immediate) 2_00001110000000000000000000000000
Load/store immediate offset 2_00001110000000000000000000000000
Load/store multiple 2_00001110000000000000000000000000
Branch (with link) 2_00001110000000000000000000000000
Coprocessor load and store 2_00001110000000000000000000000000
Bit patterns to compare with ANDed instructions above to determine the instruction class...
Preload 2_11110101010100001111000000000000
Count leading zeros 2_00000001011000000000000000010000
Software breakpoint 2_00000001001000000000000001110000
Branch (link)/exchange instruction set 2_00000001001000000000000000010000
Swap (byte) 2_00000001000000000000000010010000
Enhanced DSP add/subtracts 2_00000001000000000000000001010000
Multiply (accumulate) 2_00000000000000000000000010010000
Multiply (accumulate) long 2_00000000100000000000000010010000
Move register to status register 2_00000001001000000000000000000000
Ld/st halfword register offset 2_00000000000000000000000010110000
Ld signed hlfwd/byte register offset 2_00000000000100000000000011010000
Enhanced DSP multiplies 2_00000001000000000000000010000000
Ld/st halfword immediate offset 2_00000000010000000000000010110000
Ld/st two words register offset 2_00000000000000000000000011010000
Ld/st two words immediate offset 2_00000000010000000000000011010000
Ld signed hlfwd/byte immediate offset 2_00000000010100000000000011010000
Undefined instruction 2_11111111000000000000000000000000
Move status register to register 2_00000001000000000000000000000000
Move immediate to status register 2_00000011001000000000000000000000
Undefined instruction 2_00000011000000000000000000000000
Undefined instruction 2_11111000000000000000000000000000
Branch (with link) and into thumb 2_11111010000000000000000000000000
Coprocessor data processing 2_00001110000000000000000000000000
Coprocessor register transfers 2_00001110000000000000000000010000
Data processing (register shift) 2_00000000000000000000000000010000
Data processing (immediate shift) 2_00000000000000000000000000000000
Load/store register offset 2_00000110000000000000000000000000
Undefined instruction 2_00000110000000000000000000010000
Software interrupt 2_00001111000000000000000000000000
Data processing (immediate) 2_00000010000000000000000000000000
Load/store immediate offset 2_00000100000000000000000000000000
Load/store multiple 2_00001000000000000000000000000000
Branch (with link) 2_00001010000000000000000000000000
Coprocessor load and store 2_00001100000000000000000000000000
Masks to AND with an instruction to extract the SBZ/SBO fields...
Count leading zeros 2_00000000000011110000111100000000
Branch (link)/exchange instruction set 2_00000000000011111111111100000000
Swap (byte) 2_00000000000000000000111100000000
Enhanced DSP add/subtracts 2_00000000000000000000111100000000
Move register to status register 2_00000000000000001111111111100000
Ld/st halfword register offset 2_00000000000000000000111100000000
Ld signed hlfwd/byte register offset 2_00000000000000000000111100000000
Move status register to register 2_00000000000011110000111111111111
Move immediate to status register 2_00000000000000001111000000000000
Bit patterns to compare with ANDed instructions above to find SBZ/SBO violations...
Count leading zeros 2_00000000000011110000111100000000
Branch (link)/exchange instruction set 2_00000000000011111111111100000000
Swap (byte) 2_00000000000000000000000000000000
Enhanced DSP add/subtracts 2_00000000000000000000000000000000
Move register to status register 2_00000000000000001111000000000000
Ld/st halfword register offset 2_00000000000000000000000000000000
Ld signed hlfwd/byte register offset 2_00000000000000000000000000000000
Move status register to register 2_00000000000011110000000000000000
Move immediate to status register 2_00000000000000001111000000000000
Some other useful information...
Condition codes... ...data processing opcodes
(bits 31..28) (bits 24..21)
EQ 0000 AND
NE 0001 EOR
CS/HS 0010 SUB
CC/LO 0011 RSB
MI 0100 ADD
PL 0101 ADC
VS 0110 SBC
VC 0111 RSC
HI 1000 TST
LS 1001 TEQ
GE 1010 CMP
LT 1011 CMN
GT 1100 ORR
LE 1101 MOV
AL 1110 BIC
NV 1111 MVN
......@@ -8,11 +8,17 @@
GBLS Module_FullVersion
GBLS Module_ApplicationDate2
GBLS Module_ApplicationDate4
Module_MajorVersion SETS "1.62"
Module_Version SETA 162
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "1.63"
Module_Version SETA 163
Module_MinorVersion SETS ""
Module_Date SETS "08 Sep 2000"
Module_ApplicationDate2 SETS "08-Sep-00"
Module_ApplicationDate4 SETS "08-Sep-2000"
Module_FullVersion SETS "1.62"
Module_Date SETS "30 Jan 2001"
Module_ApplicationDate2 SETS "30-Jan-01"
Module_ApplicationDate4 SETS "30-Jan-2001"
Module_ComponentName SETS "Debugger"
Module_ComponentPath SETS "RiscOS/Sources/Programmer/Debugger"
Module_FullVersion SETS "1.63"
Module_HelpVersion SETS "1.63 (30 Jan 2001)"
END
/* (1.62)
/* (1.63)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 1.62
#define Module_MajorVersion_CMHG 1.63
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 08 Sep 2000
#define Module_Date_CMHG 30 Jan 2001
#define Module_MajorVersion "1.62"
#define Module_Version 162
#define Module_MajorVersion "1.63"
#define Module_Version 163
#define Module_MinorVersion ""
#define Module_Date "08 Sep 2000"
#define Module_Date "30 Jan 2001"
#define Module_ApplicationDate2 "08-Sep-00"
#define Module_ApplicationDate4 "08-Sep-2000"
#define Module_ApplicationDate2 "30-Jan-01"
#define Module_ApplicationDate4 "30-Jan-2001"
#define Module_FullVersion "1.62"
#define Module_ComponentName "Debugger"
#define Module_ComponentPath "RiscOS/Sources/Programmer/Debugger"
#define Module_FullVersion "1.63"
#define Module_HelpVersion "1.63 (30 Jan 2001)"
......@@ -21,6 +21,7 @@
; Alan Glover (fixes/enhancements, ARM6/ARM7 instructions)
; William Turner (StrongARM compatibility)
; Kevin Bracey (ARMv4+5, Thumb, fixes/enhancements, 32-bit)
; Steve Revill (Slight changes to ADR and SWI disassembly)
; 1.18 SKS Fixed disassembly of #xx,yy operands
; 1.19 SKS Fixed disassembly of LSR #32, ASR #32
......@@ -195,6 +196,9 @@
; Disassembly of VFP instruction set added.
; PC-relative LDRH family instructions calculated
; target address incorrectly.
; 1.63 SAR 30-Jan-01 ADDS Rd,PC,#imm (and SUBS) no longer map to ADR.
; Unknown SWIs, such as 'User' and 'OS_Undefind' are now
; disassembled as 'SWI &num'.
;
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -291,6 +295,7 @@ SysIs32bit # 1 ; non-zero if on a 32-bit system
StringBuffer # 160 ; Temp string buffer. Big enough to
; hold a disassembled instruction
; and a full register set + three instrs
ASSERT (?StringBuffer :AND: 2_11)=0
TotalSpace * :INDEX: @
; List of mistakes
......@@ -337,13 +342,14 @@ ExecuteBuffer # ExeBufLen
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Useful constants
TAB * 9
LF * 10
CR * 13
space * " "
quote * """"
colon * ":"
delete * &7F
TAB * 9
LF * 10
CR * 13
space * " "
quote * """"
colon * ":"
delete * &7F
ampersand * "&"
; Useful macros
......@@ -828,11 +834,94 @@ Swi LDR R10, Mistake
SUB r2, r2, r1
BIC r0, r4, #&FF000000 ; Mask out SWI<cc>
SWI XOS_SWINumberToString ; This may give error (eg. Buffer over)
SUBVC R2,R2,#1 ;adjust to avoid taking the zero byte
ADDVC r0, r1, r2
BVS InstructionEnd
BL unknown_swis
ADD r0, r1, r2
B InstructionEnd
; Compare the string against 'User' and 'OS_Unknown' with or without the leading 'X'. If
; it matches, dump the SWI number as a string with a preceding '&' into the buffer instead.
;
; Entry...
; R0 - SWI number
; R1 - pointer to string
; R2 - offset to last char of string
; Exit...
; R0 - corrupted
; R1 - preserved
; R2 - pointer to last char of string (may be different)
;
unknown_swis
Push "R3, LR"
; Ensure all bytes after the SWI name string up to the next word boundary are zero
MOV R14, #0
ADD R3, R1, R2
unk_swi_align
TST R3, #2_11
STRNEB R14, [R3], #1
BNE unk_swi_align
; Compare this SWI name string against some pre-defined unknown SWI name strings
ADR R3, str_user
BL strcmp
BEQ unk_swi_replace
ADR R3, str_xuser
BL strcmp
BEQ unk_swi_replace
ADR R3, str_os_undefined
BL strcmp
BEQ unk_swi_replace
ADR R3, str_xos_undefined
BL strcmp
BEQ unk_swi_replace
SUB R2,R2,#1 ; Adjust to avoid taking the zero byte
Pull "R3, PC"
; Replace the SWI name string with the SWI number decoded as hexadecimal
unk_swi_replace
MOV R2, #ampersand
STRB R2, [R1], #1
MOV R2, #12
SWI XOS_ConvertHex8
SUB R2, R1, R0
SUB R1, R0, #1
ADD R2, R2, #2
Pull "R3, PC"
; Compare two word-aligned strings. They *must* be padded with zero or more null bytes after
; the terminator (which must also be null) up to the word boundary.
;
; Entry...
; R1 - pointer to first string
; R3 - pointer to second string
; Exit...
; R1 - preserved
; R3 - corrupted
; flags - EQ=match, NE=don't match
strcmp
Push "R0, R1, LR"
strcmp_loop
LDR R0, [R1], #4
LDR R14, [R3], #4
TEQ R0, R14
BNE strcmp_exit ; Conditional Pull is bad on newer ARMs, branch instead
TST R0, #&FF000000
BNE strcmp_loop
strcmp_exit
Pull "R0, R1, PC"
; Some SWI names indicating that a SWI number was not recognised (in length order)
str_user
DCB "User", 0
ALIGN
str_xuser
DCB "XUser", 0
ALIGN
str_os_undefined
DCB "OS_Undefined", 0
ALIGN
str_xos_undefined
DCB "XOS_Undefined", 0
ALIGN
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Branch, Branch and Link
......@@ -1640,6 +1729,9 @@ DataProcessing ROUT
TEQS R5,#15
BNE notADR ;Rn not R15
TST r4, #1 :SHL: 20
BNE notADR ;S bit set - not ADR
TestBit 25 ; I bit
BNE isADR
notADR
......
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