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Commits (21)
  • Steve Revill's avatar
    Miscellaneous updates: · a3bd3c3c
    Steve Revill authored
    * Added VFPSupport SWI definition.
    * Added some new industry standard file types.
    * Added some new sprite errors.
    
    Version 1.74. Tagged as 'HdrSrc-1_74'
    a3bd3c3c
  • Steve Revill's avatar
    Moved the filetypes for JPEG, GIF, PNG and BMP into the public domain. · 5b1e820c
    Steve Revill authored
    Finally... :)
    
    Version 1.75. Tagged as 'HdrSrc-1_75'
    5b1e820c
  • Jeffrey Lee's avatar
    Merge Cortex branch of HdrSrc into trunk · 934e1a24
    Jeffrey Lee authored
    Detail:
      This should merge all of the Cortex HdrSrc changes into the trunk, so we don't have to worry about OMAP builds breaking each time the trunk HdrSrc changes
    Admin:
      Untested!
    
    
    Version 1.76. Tagged as 'HdrSrc-1_76'
    934e1a24
  • Jeffrey Lee's avatar
    Fix HdrSrc merge error · 772c02e4
    Jeffrey Lee authored
    Version 1.77. Tagged as 'HdrSrc-1_77'
    772c02e4
  • Steve Revill's avatar
    Fix the Makefile's install phase. · a6a7207c
    Steve Revill authored
    This component could fail during the install phase due to the INSTDIR
    symbol not being defined. The Makefile will now set this to the appropriate
    value if not already set.
    
    Version 1.78. Tagged as 'HdrSrc-1_78'
    a6a7207c
  • Steve Revill's avatar
    Important change to Hdr:Macros. · c9afa87c
    Steve Revill authored
    Replaced LSL, LSR, etc, macros with myLSL, myLSR, etc. because the old macro
    names will clash with pseudo-opcodes that ARM have introduced which in turn will
    be supported by newer assemblers.
    
    Admin: this will cause some components to fail to build, especially with the
    existing toolchain. If you see these failures, simply replace any uses of these
    shift macros with the renamed 'my' shift macros (which are functionally identical).
    
    Version 1.79. Tagged as 'HdrSrc-1_79'
    c9afa87c
  • Ben Avison's avatar
    Resynced with master headers · 42fca50a
    Ben Avison authored
    Detail:
      Only change is "decloaking" of a couple of messages in the Wimp's private
      message block, originally for RISCOS Ltd. These are now publicly documented
      so I don't think there's any harm in revealing them in the headers.
    Admin:
      Message_ToggleBackdrop is required by a Pinboard source submission.
    
    Version 1.80. Tagged as 'HdrSrc-1_80'
    42fca50a
  • Jeffrey Lee's avatar
    Add HALSize support. Fix TEX definitions in VMSAv6 MMU file. · 3359afa1
    Jeffrey Lee authored
    Detail:
      Makefile - Now uses the HALSize environment variable to select which HALSize file to export
      hdr/HALSize/64K, hdr/HALSize/96K, hdr/HALSize/128K - HALSize files for 64K, 96K, 128K HAL sizes
      hdr/MEMM/VMSAv6 - Fix the incorrect TEX definitions that were corrupting the page permissions and resulting in ROM pages being writeable.
    Admin:
      Tested on rev A2 BB-xM.
      Needs latest Env folder.
    
    
    Version 1.81. Tagged as 'HdrSrc-1_81'
    3359afa1
  • Ben Avison's avatar
    Added support for Machine=ARM11ZF · b3bff27a
    Ben Avison authored
    Detail:
      Suitable for ARMv6Z CPUs with VFPv2, e.g. ARM1176JZF-S
    Admin:
      Required by the S3C6410 HAL
    
    Version 1.82. Tagged as 'HdrSrc-1_82'
    b3bff27a
  • Jeffrey Lee's avatar
    Update HdrSrc for correct ARM11ZF settings · 2e57ccf9
    Jeffrey Lee authored
    Detail:
      hdr/Machine/Machine - Use VMSAv6 and disable unaligned memory accesses when compiling for ARM11ZF (i.e. ARMv6)
    Admin:
      Tested with S3C6440 ROM build. Untested at runtime.
    
    
    Version 1.83. Tagged as 'HdrSrc-1_83'
    2e57ccf9
  • Jeffrey Lee's avatar
    Update VMSAv6 system control register info · 6c558c25
    Jeffrey Lee authored
    Detail:
      hdr/MEMM/VMSAv6 - Updated the system control register info to accurately reflect which bits work on ARMv6. Added missing SW, HA, FI definitions.
    Admin:
      Tested on rev A2 BB-xM
    
    
    Version 1.84. Tagged as 'HdrSrc-1_84'
    6c558c25
  • Jeffrey Lee's avatar
    Fix InsertTMLInitialisation macro · 74700c34
    Jeffrey Lee authored
    Detail:
      hdr/Debug - Corrected a bad use of mymrs from within the InsertTMLInitialisation macro
    Admin:
      Macro compiles OK, but is untested
    
    
    Version 1.85. Tagged as 'HdrSrc-1_85'
    74700c34
  • Jeffrey Lee's avatar
    Remove some macros which are now kernel-only · 474d5435
    Jeffrey Lee authored
    Detail:
      hdr/Macros - BYTEWS, LDROSB, STROSB & VDWS macros are now located in the kernel sources, to help keep kernel workspace private and to allow them to adapt properly to zero page relocation
    Admin:
      Latest kernel sources required in order for ROM builds to function.
      This change will break the Interlace module, but everything else should hopefully be fine.
    
    
    Version 1.86. Tagged as 'HdrSrc-1_86'
    474d5435
  • Ben Avison's avatar
    Added CortexA9 Machine · 4f1bf10b
    Ben Avison authored
    Admin:
      Submission from Willi Theiß
    
    Version 1.87. Tagged as 'HdrSrc-1_87'
    4f1bf10b
  • Jeffrey Lee's avatar
    Always export Machine.All32 · f1af6001
    Jeffrey Lee authored
    Detail:
      Makefile - Always export Machine.All32, to provide a safe machine type for assembler-based host tools
    Admin:
      Required for building ColourTrans 1.79
    
    
    Version 1.88. Tagged as 'HdrSrc-1_88'
    f1af6001
  • Ben Avison's avatar
    Resync with allocations database · e8953e67
    Ben Avison authored
    Detail:
      hdr.NewErrors: added new kernel error, requested by Rob Sprowson
      hdr.SWIs: added SWI chunks for SDIODriver and SDFS
    Admin:
      Untested
    
    Version 1.89. Tagged as 'HdrSrc-1_89'
    e8953e67
  • Ben Avison's avatar
    Resync with allocations database · b8efc67b
    Ben Avison authored
    Version 1.90. Tagged as 'HdrSrc-1_90'
    b8efc67b
  • Ben Avison's avatar
    Resync with allocations database (again) · dbdc5f7a
    Ben Avison authored
    Version 1.91. Tagged as 'HdrSrc-1_91'
    dbdc5f7a
  • Jeffrey Lee's avatar
    Add new OS_Heap reason code · 4027b21d
    Jeffrey Lee authored
    Detail:
      hdr/Heap - Added definition for OS_Heap 7, HeapReason_GetAligned
    Admin:
      Heap changes tested in OMAP3 & Tungsten ROMs
    
    
    Version 1.92. Tagged as 'HdrSrc-1_92'
    4027b21d
  • Steve Revill's avatar
    Added an ImageSize header file for 20MB ROM builds · 940584be
    Steve Revill authored
    Version 1.93. Tagged as 'HdrSrc-1_93'
    940584be
  • Steve Revill's avatar
    Updates and additions for non-Iyonix builds and !System distribution. · 5cf1c1db
    Steve Revill authored
    Changes provided by sprow.
    
    Version 1.94. Tagged as 'HdrSrc-1_94'
    5cf1c1db
......@@ -38,10 +38,11 @@
#
# Paths
#
TOPDIR = <hdr$dir>
HDRDIR = ${TOPDIR}.Global
HDIR = <CExport$dir>
LIBDIR = <Lib$Dir>
TOPDIR = <hdr$dir>
HDRDIR = ${TOPDIR}.Global
HDIR = <CExport$dir>
LIBDIR = <Lib$Dir>
INSTDIR ?= <APCSExport$Dir>
include StdTools
......@@ -71,6 +72,7 @@ EXPORTS = \
${HDRDIR}.FileTypes \
${HDRDIR}.FSNumbers \
${HDRDIR}.GraphicsV \
${HDRDIR}.HALSize.<HALSize> \
${HDRDIR}.Heap \
${HDRDIR}.ImageSize.<ImageSize> \
${HDRDIR}.IO.GenericIO \
......@@ -84,7 +86,9 @@ EXPORTS = \
${HDRDIR}.ListOpts \
${HDRDIR}.MEMM.ARM600 \
${HDRDIR}.MEMM.MEMC1 \
${HDRDIR}.MEMM.VMSAv6 \
${HDRDIR}.Machine.<Machine> \
${HDRDIR}.Machine.All32 \
${HDRDIR}.Machine.Machine \
${HDRDIR}.Macros \
${HDRDIR}.Messages \
......@@ -160,6 +164,7 @@ Dirs:
${MKDIR} ${HDRDIR}.APCS
${MKDIR} ${HDRDIR}.CPU
${MKDIR} ${HDRDIR}.FDC
${MKDIR} ${HDRDIR}.HALSize
${MKDIR} ${HDRDIR}.IO
${MKDIR} ${HDRDIR}.ImageSize
${MKDIR} ${HDRDIR}.Machine
......@@ -197,9 +202,10 @@ ${INSTDIR}.Hdr.ListOpts: hdr.ListOpts; ${CP} hdr.ListOpts $@ ${CP
# Special rule for exporting all ImageSize, Machine and UserIF files.
# Trigger by invoking the export with OPTIONS=ALL.
#
ALL: ${HDRDIR}.Machine.Machine ${HDRDIR}.UserIF.UserIF ${HDRDIR}.ImageSize.<ImageSize> ${HDRDIR}.APCS.<APCS>
ALL: ${HDRDIR}.Machine.Machine ${HDRDIR}.UserIF.UserIF ${HDRDIR}.HALSize.<HALSize> ${HDRDIR}.ImageSize.<ImageSize> ${HDRDIR}.APCS.<APCS>
${CP} hdr.Machine ${HDRDIR}.Machine ${CPFLAGS}
${CP} hdr.UserIF ${HDRDIR}.UserIF ${CPFLAGS}
${CP} hdr.HALSize ${HDRDIR}.HALSize ${CPFLAGS}
${CP} hdr.ImageSize ${HDRDIR}.ImageSize ${CPFLAGS}
${CP} hdr.APCS ${HDRDIR}.APCS ${CPFLAGS}
......@@ -277,7 +283,9 @@ ${HDIR}.Global.h.IOCtl: h.IOCtl; ${CP} h.IOCtl
# Machine/UI/hardware specific headers:
${HDRDIR}.Machine.<Machine>: hdr.Machine.<Machine>; ${CP} hdr.Machine.<Machine> $@ ${CPFLAGS}
${HDRDIR}.Machine.All32: hdr.Machine.All32; ${CP} hdr.Machine.All32 $@ ${CPFLAGS}
${HDRDIR}.Machine.Machine: hdr.Machine.Machine; ${CP} hdr.Machine.Machine $@ ${CPFLAGS}
${HDRDIR}.HALSize.<HALSize>: hdr.HALSize.<HALSize>; ${CP} hdr.HALSize.<HALSize> $@ ${CPFLAGS}
${HDRDIR}.ImageSize.<ImageSize>: hdr.ImageSize.<ImageSize>; ${CP} hdr.ImageSize.<ImageSize> $@ ${CPFLAGS}
${HDRDIR}.APCS.<APCS>: hdr.APCS.<APCS>; ${CP} hdr.APCS.<APCS> $@ ${CPFLAGS}
${HDRDIR}.APCS.Common: hdr.APCS.Common; ${CP} hdr.APCS.Common $@ ${CPFLAGS}
......@@ -295,6 +303,7 @@ ${HDRDIR}.IO.IOMD: hdr.IO.IOMD; ${CP} hdr.IO.IOMD
${HDRDIR}.IO.IOMDL: hdr.IO.IOMDL; ${CP} hdr.IO.IOMDL $@ ${CPFLAGS}
${HDRDIR}.MEMM.ARM600: hdr.MEMM.ARM600; ${CP} hdr.MEMM.ARM600 $@ ${CPFLAGS}
${HDRDIR}.MEMM.MEMC1: hdr.MEMM.MEMC1; ${CP} hdr.MEMM.MEMC1 $@ ${CPFLAGS}
${HDRDIR}.MEMM.VMSAv6: hdr.MEMM.VMSAv6; ${CP} hdr.MEMM.VMSAv6 $@ ${CPFLAGS}
${HDRDIR}.VIDC.VIDC1a: hdr.VIDC.VIDC1a; ${CP} hdr.VIDC.VIDC1a $@ ${CPFLAGS}
${HDRDIR}.VIDC.VIDC20: hdr.VIDC.VIDC20; ${CP} hdr.VIDC.VIDC20 $@ ${CPFLAGS}
......
/* (1.73)
/* (1.94)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.73
#define Module_MajorVersion_CMHG 1.94
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 06 Nov 2009
#define Module_Date_CMHG 11 Jan 2012
#define Module_MajorVersion "1.73"
#define Module_Version 173
#define Module_MajorVersion "1.94"
#define Module_Version 194
#define Module_MinorVersion ""
#define Module_Date "06 Nov 2009"
#define Module_Date "11 Jan 2012"
#define Module_ApplicationDate "06-Nov-09"
#define Module_ApplicationDate "11-Jan-12"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.73"
#define Module_HelpVersion "1.73 (06 Nov 2009)"
#define Module_LibraryVersionInfo "1:73"
#define Module_FullVersion "1.94"
#define Module_HelpVersion "1.94 (11 Jan 2012)"
#define Module_LibraryVersionInfo "1:94"
......@@ -433,6 +433,9 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
[ "$Machine" = "Tungsten" ; Iyonix PC
ArchitectureOption v5TEX
|
[ "$Machine" = "ARM11ZF"
ArchitectureOption v6K_VFP2D
|
[ "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7_VFP3D32_SIMD
|
......@@ -458,6 +461,7 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
]
]
]
]
]
GBLL SupportARMv3
......
......@@ -670,7 +670,7 @@ Host_Debug SETL True
HostDebugViaTML SETL True
$label Push "r1-r2, r11, lr"
mymrs r2, CPSR
mymrs ,r2, CPSR
[ Debug_MaybeIRQ
TST r2, #2_11100
ORREQ lr, r2, #SVC_mode ; 26-bit systems change to SVC_26
......
......@@ -75,6 +75,7 @@ fsnumber_ShareFS # 1 ; 99 Share: Acorn
fsnumber_FlashFS # 1 ; 136 Acorn (ap)
^ 162
fsnumber_TFTP # 1 ; 162 Kevin Bracey
fsnumber_SDFS # 1 ; 192 ROOL / Ben Avison
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......
......@@ -618,6 +618,10 @@ FileType_CapitalAuthorisation_Name SETS "C.E.A."
FileType_HPGLPlot EQU &00000CAE
FileType_HPGLPlot_Name SETS "HPGLPlot"
GBLS FileType_JPEG_Name
FileType_JPEG EQU &00000C85
FileType_JPEG_Name SETS "JPEG"
GBLS FileType_Manual_Name
FileType_Manual EQU &00000C2F
FileType_Manual_Name SETS "Manual"
......@@ -654,6 +658,10 @@ FileType_BBCROM_Name SETS "BBC ROM"
FileType_Instrument EQU &00000B63
FileType_Instrument_Name SETS "Instrum"
GBLS FileType_Fresco2_Name
FileType_Fresco2 EQU &00000B60
FileType_Fresco2_Name SETS "PNG"
GBLS FileType_Draw_Name
FileType_Draw EQU &00000AFF
FileType_Draw_Name SETS "DrawFile"
......@@ -774,6 +782,50 @@ FileType_ICA_Name SETS "ICA"
FileType_Blink EQU &00000AA4
FileType_Blink_Name SETS "Blink"
GBLS FileType_OpenDocFormulae_Name
FileType_OpenDocFormulae EQU &00000A86
FileType_OpenDocFormulae_Name SETS "ODF"
GBLS FileType_OpenDocGraphics_Name
FileType_OpenDocGraphics EQU &00000A85
FileType_OpenDocGraphics_Name SETS "ODG"
GBLS FileType_OpenDocPresentation_Name
FileType_OpenDocPresentation EQU &00000A84
FileType_OpenDocPresentation_Name SETS "ODP"
GBLS FileType_OpenDocDatabase_Name
FileType_OpenDocDatabase EQU &00000A83
FileType_OpenDocDatabase_Name SETS "ODB"
GBLS FileType_OpenDocSpreadsheet_Name
FileType_OpenDocSpreadsheet EQU &00000A82
FileType_OpenDocSpreadsheet_Name SETS "ODS"
GBLS FileType_OpenDocWord_Name
FileType_OpenDocWord EQU &00000A81
FileType_OpenDocWord_Name SETS "ODT"
GBLS FileType_OOXMLPresentation_Name
FileType_OOXMLPresentation EQU &00000A80
FileType_OOXMLPresentation_Name SETS "PowerPtX"
GBLS FileType_OOXMLSpreadsheet_Name
FileType_OOXMLSpreadsheet EQU &00000A7F
FileType_OOXMLSpreadsheet_Name SETS "ExcelX"
GBLS FileType_OOXMLDoc_Name
FileType_OOXMLDoc EQU &00000A7E
FileType_OOXMLDoc_Name SETS "MSWordX"
GBLS FileType_Translator_BMP_Name
FileType_Translator_BMP EQU &0000069C
FileType_Translator_BMP_Name SETS "BMP"
GBLS FileType_Translator_GIF_Name
FileType_Translator_GIF EQU &00000695
FileType_Translator_GIF_Name SETS "GIF"
OPT OldOpt
END
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; HAL Size definition for 128K HAL
OSROM_HALSize * 128*1024 ; HAL Size in bytes
END
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; HAL Size definition for 64K HAL
OSROM_HALSize * 64*1024 ; HAL Size in bytes
END
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; HAL Size definition for 96K HAL
OSROM_HALSize * 96*1024 ; HAL Size in bytes
END
......@@ -22,5 +22,6 @@ HeapReason_Free # 1
HeapReason_ExtendBlock # 1
HeapReason_ExtendHeap # 1
HeapReason_ReadBlockSize # 1
HeapReason_GetAligned # 1
END
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; Image Size definition for 20M ROM
OSROM_ImageSize * 20480 ; ROM Size in K
END
......@@ -125,6 +125,7 @@ CT_ctype_WB_CR7 * 2 ; write-back, clean with register 7
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDa * 6 ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb * 7 ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_size_pos * 6
CT_size_mask * 7:SHL:CT_size_pos
......
; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > hdr:VMSAv6
; ********************
; *** Changes List ***
; ********************
; 18-Feb-09 JL Created, using ARM600 as basis.
; Access privilege bits
; These comprise the AP and APX bits, which are luckily always in the same location relative to each other
AP_ROM * 2_100010 ; user read-only, svc read-only
AP_None * 2_000001 ; user no access, svc read/write
AP_Read * 2_000010 ; user read-only, svc read/write
AP_Full * 2_000011 ; user read/write, svc read/write
L1_APShift * 10 ; value to shift AP_ values by for L1 entry
L2_APShift * 4 ; value to shift AP_ values by for L2 entry
L1_APMult * 1 :SHL: L1_APShift ; value to multiply AP_ values by for L1 entry
L2_APMult * 1 :SHL: L2_APShift ; value to multiply AP_ values by for L2 entry
L2X_APMult * L2_APMult
L1_AP * 2_100011 * L1_APMult ; masks for AP fields
L2_AP * 2_100011 * L2_APMult
L1_DomainShift * 5 ; lowest bit position in L1 entry for domain number
L1_Fault * 4_0 ; translation fault specifier in L1 entry
L1_Page * 4_1 ; coarse page specifier in L1 entry
L1_Section * 4_2 ; section specifier in L1 entry
; supersections not supported ATM
L2_Fault * 4_0 ; translation fault specifier in L2 entry
L2_LargePage * 4_1 ; large page specifier in L2 entry
L2_SmallPage * 4_2 ; (extended) small page specifier in L2 entry
L2_ExtPage * L2_SmallPage
L1_TEXShift * 12
L1_TEX * 2_111 :SHL: 12 ; Type Extension bits
L1_C * 1 :SHL: 3 ; cacheable
L1_B * 1 :SHL: 2 ; bufferable
L1_nG * 1 :SHL: 17 ; 1=entry associated with ASID, 0=global
L1_XN * 1 :SHL: 4 ; eXecute Never
L1_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (is TEX bit 0)
L2L_TEXShift * 12 ; For large pages
L2_TEXShift * 6 ; For extended small pages
L2L_TEX * 2_111 :SHL: 12 ; Type Extension bits (large pages)
L2_TEX * 2_111 :SHL: 6 ; Type Extension bits (tiny and extended pages)
L2_C * 1 :SHL: 3 ; cacheable bit in level 2 entry
L2_B * 1 :SHL: 2 ; bufferable --------""----------
L2_nG * 1 :SHL: 11 ; 1=entry associated with ASID, 0=global
L2L_XN * 1 :SHL: 15 ; eXecute Never for large pages
L2_XN * 1 ; eXecute Never for extended small pages
L2L_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (large pages) (is TEX bit 0)
L2_X * 1 :SHL: 6 ; XScale - modifies meaning of C and B bits (tiny and extended pages) (is TEX bit 0)
; CP15 control register bits
; Retaining MMUC_* naming for compatability with existing code
; Validity: 5 = ARMv5 or older, 6=ARMv6, K=ARMv6K, 7=ARMv7, !=Warning, bit reused
MMUC_M * 1 :SHL: 0 ; 567 MMU enable
MMUC_A * 1 :SHL: 1 ; 567 Alignment fault enable
MMUC_C * 1 :SHL: 2 ; 567 Cache enable (or Data cache enable)
MMUC_W * 1 :SHL: 3 ; 56 Write buffer enable
MMUC_P * 1 :SHL: 4 ; 5 32-bit program space enable
MMUC_D * 1 :SHL: 5 ; 5 32-bit data space enable
MMUC_L * 1 :SHL: 6 ; 5 Late abort mode enable
MMUC_B * 1 :SHL: 7 ; 56 Big-endian mode enable
MMUC_S * 1 :SHL: 8 ; 5 S-mode enable
MMUC_R * 1 :SHL: 9 ; 5 R-mode enable (ARM7 or later)
MMUC_F * 1 :SHL: 10 ; 5!! Coprocessor frequency bit (ARM700 only)
MMUC_SW * 1 :SHL: 10 ; !!7 SWP/SWPB enable (ARMv7MP)
MMUC_Z * 1 :SHL: 11 ; 567 Branch predictor enable
MMUC_I * 1 :SHL: 12 ; 567 Instruction cache enable
MMUC_V * 1 :SHL: 13 ; 567 High exception vectors
MMUC_RR * 1 :SHL: 14 ; 567 Round-robin/alternate cache replacement strategy
MMUC_L4 * 1 :SHL: 15 ; 56 Disable ARMv5 "load Thumb state with PC" behaviour
MMUC_HA * 1 :SHL: 17 ; K7 Hardware access flag enable
MMUC_FI * 1 :SHL: 21 ; 67 Fast interrupt configuration enable
MMUC_U * 1 :SHL: 22 ; 6 Unaligned data access operation
MMUC_XP * 1 :SHL: 23 ; 6 Extended page table config
MMUC_VE * 1 :SHL: 24 ; 6 Vectored interrupts
MMUC_EE * 1 :SHL: 25 ; 67 Exception Endian bit
MMUC_L2 * 1 :SHL: 26 ; 6 L2 unified cache enable
MMUC_NMFI * 1:SHL: 27 ; 67 Non-maskable FIQ (read-only)
MMUC_TRE * 1 :SHL: 28 ; K7 TEX remap enable
MMUC_AFE * 1 :SHL: 29 ; K7 Access Flag Enable (AP[0] remap)
MMUC_nF * 1 :SHL: 30 ; 5!! not FastBus (ie separate CPUCLK from MEMCLK)
MMUC_TE * 1 :SHL: 30 ; !67 Exceptions handled in Thumb mode
MMUC_iA * 1 :SHL: 31 ; 5 Asynchronous
; ARM600 MMU coprocessor number
Arm600Cop CP 15
; ARM600 coprocessor registers
CR_Dummy CN 0
CR_ID CN 0 ; read-only
CR_Control CN 1 ; read/write
CR_TTabBase CN 2 ; read/write
CR_Domains CN 3 ; read/write
CR_FaultStatus CN 5 ; read
CR_FaultAddress CN 6 ; read
; Cache type register fields
; NOTE - need to be kept in sync with hdr.MEMM.ARM600!
CT_ctype_pos * 25
CT_ctype_mask * &F:SHL:CT_ctype_pos
CT_S_pos * 24
CT_S * 1:SHL:CT_S_pos
CT_Dsize_pos * 12
CT_Dsize_mask * &FFF:SHL:CT_Dsize_pos
CT_Isize_pos * 0
CT_Isize_mask * &FFF:SHL:CT_Isize_pos
CT_ctype_WT * 0 ; write-through cache
CT_ctype_WB_Crd * 1 ; write-back, clean by reading data
CT_ctype_WB_CR7 * 2 ; write-back, clean with register 7
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDa * 6 ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb * 7 ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_size_pos * 6
CT_size_mask * 7:SHL:CT_size_pos
CT_assoc_pos * 3
CT_assoc_mask * 7:SHL:CT_assoc_pos
CT_M_pos * 2
CT_M * 1:SHL:CT_M_pos
CT_len_pos * 0
CT_len_mask * 3:SHL:CT_len_pos
CT_size_512 * 0
CT_size_1K * 1
CT_size_2K * 2
CT_size_4K * 3
CT_size_8K * 4
CT_size_16K * 5
CT_size_32K * 6
CT_size_64K * 7
CT_size_768 * 0
CT_size_1536 * 1
CT_size_3K * 2
CT_size_6K * 3
CT_size_12K * 4
CT_size_24K * 5
CT_size_48K * 6
CT_size_96K * 7
CT_assoc_1 * 0
CT_assoc_2 * 1
CT_assoc_4 * 2
CT_assoc_8 * 3
CT_assoc_16 * 4
CT_assoc_32 * 5
CT_assoc_64 * 6
CT_assoc_128 * 7
CT_assoc_0 * 0
CT_assoc_3 * 1
CT_assoc_6 * 2
CT_assoc_12 * 3
CT_assoc_24 * 4
CT_assoc_48 * 5
CT_assoc_96 * 6
CT_assoc_192 * 7
CT_len_2 * 0
CT_len_4 * 1
CT_len_8 * 2
CT_len_16 * 3
CT_M_512 * 0
CT_M_1K * 0
CT_M_2K * 0
CT_M_4K * 0
CT_M_8K * 0
CT_M_16K * 0
CT_M_32K * 0
CT_M_64K * 0
CT_M_768 * 1
CT_M_1536 * 1
CT_M_3K * 1
CT_M_6K * 1
CT_M_12K * 1
CT_M_24K * 1
CT_M_48K * 1
CT_M_96K * 1
MACRO
SetCop $reg, $cop, $rm, $op2, $cc
[ "$op2" = ""
MCR$cc Arm600Cop, 0, $reg, $cop, CR_Dummy
|
MCR$cc Arm600Cop, 0, $reg, $cop, $rm, $op2
]
MEND
MACRO
ReadCop $reg, $cop, $rm, $op2, $cc
[ "$op2" = ""
MRC$cc Arm600Cop, 0, $reg, $cop, CR_Dummy
|
MRC$cc Arm600Cop, 0, $reg, $cop, $rm, $op2
]
MEND
END
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Architecture v6Z with VFPv2
GBLS Machine
Machine SETS "ARM11ZF"
GET Hdr:Machine.Machine
END
; Copyright 2012 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Definition of machines that predate IOMD, having instead IOC+MEMC
GBLS Machine
Machine SETS "Archimedes"
GET Hdr:Machine.Machine
END
; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Cortex-A8 machine: ARMv7 + NEON
GBLS Machine
Machine SETS "CortexA8"
GET Hdr:Machine.Machine
END
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Cortex-A9 machine: ARMv7 + NEON
GBLS Machine
Machine SETS "CortexA9"
GET Hdr:Machine.Machine
END
This diff is collapsed.
......@@ -101,7 +101,6 @@ OldOpt SETA {OPT}
;$label BADDR $reg, $dest, $cond Same as ADDR
; BlankLineInSWIFile
;$label Byte $value, $count Add a byte of workspace
; BYTEWS $reg Get pointer to OsbyteVars
;$label CallAVector $cond Call a vector
;$label ChkKernelVersion Call OS_ReadSysInfo(1) to stop modules from being soft loaded on 2.00.
;$n Chunk $v,$c,$s,$o Create a SWI chunk
......@@ -128,7 +127,6 @@ OldOpt SETA {OPT}
; JumpAddress $reg,$destination,$forward Set a viable (BAL to) return address
;$label LD $reg,$var,$cc Load byte or word
;$label LDHA $dest, $array, $index, $temp, $cond Load unsigned halfword from array: LDRH $dest, [$array, $index, LSL #1]
;$label LDROSB $reg, $var, $cond Load OSByte variable
;$label LDSHA $dest, $array, $index, $temp, $cond, $teq0 Load signed halfword from array, with optional TEQ $dest, #0
;$label LDW $dest, $addr, $temp1, $temp2 Load word from unknown alignment
;$label LowerCase $reg, $wrk, $nowarning Lowercase A-Z and top-bit set chars
......@@ -148,13 +146,11 @@ OldOpt SETA {OPT}
;$label STASH $reglist, $cond, $hat Push registers onto the stack
;$label STRIM $string Output an immediate string
;$Answer StringContains $string,$substring Assembly-time INSTR function
;$label STROSB $reg, $var, $temp, $cond Store an OSByte variable
;$label Swap $ra, $rb, $cc Swap two registers
; TerminateFile
;$label uk_LowerCase $reg, $wrk Lowercase A-Z ONLY
;$label uk_UpperCase $reg, $wrk Uppercase A-Z ONLY
;$label UpperCase $reg, $wrk, $nowarning Uppercase a-z & top bit set chars
; VDWS $reg Get pointer to VduDriverWorkSpace
;$label Word $value, $count Add word to workspace
;$label WRLN $string WriteLn a string
;$label wsaddr $reg, $object, $cc ???
......@@ -417,19 +413,19 @@ $label CMP $reg, #"a"
SUBGE $reg, $reg, #"a"-"A"
MEND
; ***************************************************************
; *** ASL - Generate an instruction which ASLs its argument ***
; ***************************************************************
; *****************************************************************
; *** myASL - Generate an instruction which ASLs its argument ***
; *****************************************************************
MACRO
$label ASL $reg, $val, $cc
$label myASL $reg, $val, $cc
$label MOV$cc $reg, $reg, ASL #$val
MEND
; ***************************************************************
; *** ASL - Generate an instruction which ASRs its argument ***
; ***************************************************************
; *****************************************************************
; *** myASL - Generate an instruction which ASRs its argument ***
; *****************************************************************
MACRO
$label ASR $reg, $val, $cc
$label myASR $reg, $val, $cc
$label MOV$cc $reg, $reg, ASR #$val
MEND
......@@ -473,21 +469,6 @@ $label # ($value)
]
MEND
; **************************************
; *** BYTEWS - Point to OsbyteVars ***
; **************************************
MACRO
$label BYTEWS $reg
$label
Immediate OsbyteVars
[ immediate
MOV $reg, #OsbyteVars
|
MOV $reg, #(OsbyteVars :AND: &FF)
ORR $reg, $reg, #(OsbyteVars :AND: :NOT: &FF)
]
MEND
; *********************
; *** CallAVector ***
; *********************
......@@ -1095,15 +1076,6 @@ $label
]
MEND
; ***************************************
; *** LDROSB - Load Osbyte variable ***
; ***************************************
MACRO
$label LDROSB $reg, $var, $cond
$label MOV$cond $reg, #0
LDR$cond.B $reg, [$reg, #OsbyteVars+$var-OSBYTEFirstVar]
MEND
; ***************************************************
; *** LDSHA - Load signed halfword from array ***
; *** This macro essentially implements: ***
......@@ -1210,19 +1182,19 @@ $label CMP $reg, #"A"
! 0, "Use the Territory Manager for any International-aware code."
MEND
; ***************************************************************
; *** LSL - Generate an instruction which LSLs its argument ***
; ***************************************************************
; *****************************************************************
; *** myLSL - Generate an instruction which LSLs its argument ***
; *****************************************************************
MACRO
$label LSL $reg, $val, $cc
$label myLSL $reg, $val, $cc
$label MOV$cc $reg, $reg, LSL #$val
MEND
; ***************************************************************
; *** LSR - Generate an instruction which LSRs its argument ***
; ***************************************************************
; *****************************************************************
; *** myLSR - Generate an instruction which LSRs its argument ***
; *****************************************************************
MACRO
$label LSR $reg, $val, $cc
$label myLSR $reg, $val, $cc
$label MOV$cc $reg, $reg, LSR #$val
MEND
......@@ -1370,11 +1342,11 @@ $label STM$cond.FD r13!, {$reglist}
]
MEND
; ***************************************************************
; *** ROR - Generate an instruction which RORs its argument ***
; ***************************************************************
; *****************************************************************
; *** myROR - Generate an instruction which RORs its argument ***
; *****************************************************************
MACRO
$label ROR $reg, $val, $cc
$label myROR $reg, $val, $cc
$label
LCLA modval
modval SETA ($val) :AND: &1F
......@@ -1385,11 +1357,11 @@ modval SETA ($val) :AND: &1F
]
MEND
; ***************************************************************
; *** RRX - Generate an instruction which RRXs its argument ***
; ***************************************************************
; *****************************************************************
; *** myRRX - Generate an instruction which RRXs its argument ***
; *****************************************************************
MACRO
$label RRX $reg, $cc
$label myRRX $reg, $cc
$label MOV$cc $reg, $reg, RRX
MEND
......@@ -1456,15 +1428,6 @@ $Answer StringContains "$temp","$substring"
]
MEND
; ****************************************
; *** STROSB - Store Osbyte variable ***
; ****************************************
MACRO
$label STROSB $reg, $var, $temp, $cond
$label MOV$cond $temp, #0
STR$cond.B $reg, [$temp, #OsbyteVars+$var-OSBYTEFirstVar]
MEND
; ***********************************
; *** Swap - Swap two registers ***
; ***********************************
......@@ -1530,22 +1493,6 @@ $label CMP $reg, #"a"
! 0, "Use the Territory Manager for any International-aware code."
MEND
; ****************************************************
; *** VDWS - Point to our new VduDriverWorkSpace ***
; ****************************************************
MACRO
$label VDWS $reg
$label
[ AssemblingArthur :LOR: Module
MOV $reg, #VduDriverWorkSpace
|
! 0, "This is a real waste if using Hdr.NewSpace"
MOV $reg, #(VduDriverWorkSpace :AND: &FF000000)
ORR $reg, $reg, #(VduDriverWorkSpace :AND: &00FF0000)
ORR $reg, $reg, #(VduDriverWorkSpace :AND: &0000FFFF)
]
MEND
; ***************************************************************
; *** VoidTypesUntil - Skip over some file type allocations ***
; ***************************************************************
......
......@@ -108,6 +108,8 @@ Message_Swap # 1 ; &400CD issued by the Wimp for Task Man
Message_ToolsChanged # 1 ; &400CE issued by Wimp when new tools installed
Message_FontChanged # 1 ; &400CF issued by application on changing WIMP$Font
Message_IconizeAt # 1 ; &400D0 issued by the Wimp when Shift-close clicked
Message_ToggleBackdrop # 1 ; &400D1 issued by application to bring backdrop to front
Message_ScreenEdgeNotification # 1 ; &400D2 issued by Wimp when pointer is at edge of screen
;
; Printer driver application messages
......