Commit 6c558c25 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Update VMSAv6 system control register info

Detail:
  hdr/MEMM/VMSAv6 - Updated the system control register info to accurately reflect which bits work on ARMv6. Added missing SW, HA, FI definitions.
Admin:
  Tested on rev A2 BB-xM


Version 1.84. Tagged as 'HdrSrc-1_84'
parent 2e57ccf9
/* (1.83)
/* (1.84)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.83
#define Module_MajorVersion_CMHG 1.84
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 04 Jun 2011
#define Module_Date_CMHG 09 Jun 2011
#define Module_MajorVersion "1.83"
#define Module_Version 183
#define Module_MajorVersion "1.84"
#define Module_Version 184
#define Module_MinorVersion ""
#define Module_Date "04 Jun 2011"
#define Module_Date "09 Jun 2011"
#define Module_ApplicationDate "04-Jun-11"
#define Module_ApplicationDate "09-Jun-11"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.83"
#define Module_HelpVersion "1.83 (04 Jun 2011)"
#define Module_LibraryVersionInfo "1:83"
#define Module_FullVersion "1.84"
#define Module_HelpVersion "1.84 (09 Jun 2011)"
#define Module_LibraryVersionInfo "1:84"
......@@ -74,10 +74,10 @@ L2_X * 1 :SHL: 6 ; XScale - modifies meaning of C and B bits (tin
; CP15 control register bits
; Retaining MMUC_* naming for compatability with existing code
; Validity: 5 = ARMv5 or older, 6=ARMv6, C=Cortex, !=Warning, bit reused
MMUC_M * 1 :SHL: 0 ; 56C MMU enable
MMUC_A * 1 :SHL: 1 ; 56C Alignment fault enable
MMUC_C * 1 :SHL: 2 ; 56C Cache enable (or Data cache enable)
; Validity: 5 = ARMv5 or older, 6=ARMv6, K=ARMv6K, 7=ARMv7, !=Warning, bit reused
MMUC_M * 1 :SHL: 0 ; 567 MMU enable
MMUC_A * 1 :SHL: 1 ; 567 Alignment fault enable
MMUC_C * 1 :SHL: 2 ; 567 Cache enable (or Data cache enable)
MMUC_W * 1 :SHL: 3 ; 56 Write buffer enable
MMUC_P * 1 :SHL: 4 ; 5 32-bit program space enable
MMUC_D * 1 :SHL: 5 ; 5 32-bit data space enable
......@@ -85,22 +85,25 @@ MMUC_L * 1 :SHL: 6 ; 5 Late abort mode enable
MMUC_B * 1 :SHL: 7 ; 56 Big-endian mode enable
MMUC_S * 1 :SHL: 8 ; 5 S-mode enable
MMUC_R * 1 :SHL: 9 ; 5 R-mode enable (ARM7 or later)
MMUC_F * 1 :SHL: 10 ; 5 Coprocessor frequency bit (ARM700 only)
MMUC_Z * 1 :SHL: 11 ; 56C Branch predictor enable
MMUC_I * 1 :SHL: 12 ; 56C Instruction cache enable
MMUC_V * 1 :SHL: 13 ; 56C High exception vectors
MMUC_RR * 1 :SHL: 14 ; 56 Round-robin/alternate cache replacement strategy
MMUC_L4 * 1 :SHL: 15 ; 5 Disable ARMv5 "load Thumb state with PC" behaviour
MMUC_F * 1 :SHL: 10 ; 5!! Coprocessor frequency bit (ARM700 only)
MMUC_SW * 1 :SHL: 10 ; !!7 SWP/SWPB enable (ARMv7MP)
MMUC_Z * 1 :SHL: 11 ; 567 Branch predictor enable
MMUC_I * 1 :SHL: 12 ; 567 Instruction cache enable
MMUC_V * 1 :SHL: 13 ; 567 High exception vectors
MMUC_RR * 1 :SHL: 14 ; 567 Round-robin/alternate cache replacement strategy
MMUC_L4 * 1 :SHL: 15 ; 56 Disable ARMv5 "load Thumb state with PC" behaviour
MMUC_HA * 1 :SHL: 17 ; K7 Hardware access flag enable
MMUC_FI * 1 :SHL: 21 ; 67 Fast interrupt configuration enable
MMUC_U * 1 :SHL: 22 ; 6 Unaligned data access operation
MMUC_XP * 1 :SHL: 23 ; 6 Extended page table config
MMUC_VE * 1 :SHL: 24 ; 6 Vectored interrupts
MMUC_EE * 1 :SHL: 25 ; 6C Exception Endian bit
MMUC_EE * 1 :SHL: 25 ; 67 Exception Endian bit
MMUC_L2 * 1 :SHL: 26 ; 6 L2 unified cache enable
MMUC_NMFI * 1:SHL: 27 ; C Non-maskable FIQ (read-only)
MMUC_TRE * 1 :SHL: 28 ; C TEX remap enable
MMUC_AFE * 1 :SHL: 29 ; C Access Flag Enable (AP[0] remap)
MMUC_NMFI * 1:SHL: 27 ; 67 Non-maskable FIQ (read-only)
MMUC_TRE * 1 :SHL: 28 ; K7 TEX remap enable
MMUC_AFE * 1 :SHL: 29 ; K7 Access Flag Enable (AP[0] remap)
MMUC_nF * 1 :SHL: 30 ; 5!! not FastBus (ie separate CPUCLK from MEMCLK)
MMUC_TE * 1 :SHL: 30 ; !!C Exceptions handled in Thumb mode
MMUC_TE * 1 :SHL: 30 ; !67 Exceptions handled in Thumb mode
MMUC_iA * 1 :SHL: 31 ; 5 Asynchronous
; ARM600 MMU coprocessor number
......
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