Commit 4f1bf10b authored by Ben Avison's avatar Ben Avison
Browse files

Added CortexA9 Machine

Admin:
  Submission from Willi Theiß

Version 1.87. Tagged as 'HdrSrc-1_87'
parent 474d5435
/* (1.86)
/* (1.87)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.86
#define Module_MajorVersion_CMHG 1.87
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 07 Aug 2011
#define Module_Date_CMHG 12 Sep 2011
#define Module_MajorVersion "1.86"
#define Module_Version 186
#define Module_MajorVersion "1.87"
#define Module_Version 187
#define Module_MinorVersion ""
#define Module_Date "07 Aug 2011"
#define Module_Date "12 Sep 2011"
#define Module_ApplicationDate "07-Aug-11"
#define Module_ApplicationDate "12-Sep-11"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.86"
#define Module_HelpVersion "1.86 (07 Aug 2011)"
#define Module_LibraryVersionInfo "1:86"
#define Module_FullVersion "1.87"
#define Module_HelpVersion "1.87 (12 Sep 2011)"
#define Module_LibraryVersionInfo "1:87"
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Cortex-A9 machine: ARMv7 + NEON
GBLS Machine
Machine SETS "CortexA9"
GET Hdr:Machine.Machine
END
......@@ -49,6 +49,7 @@ Included_Hdr_Machine_Machine SETL {TRUE}
GBLL M_32
GBLL M_ARM11ZF
GBLL M_CortexA8
GBLL M_CortexA9
M_All SETL Machine="All"
M_Falcon SETL Machine="Falcon"
M_Morris SETL Machine="Morris"
......@@ -63,6 +64,7 @@ M_Tungsten SETL Machine="Tungsten"
M_32 SETL Machine="32"
M_ARM11ZF SETL Machine="ARM11ZF"
M_CortexA8 SETL Machine="CortexA8"
M_CortexA9 SETL Machine="CortexA9"
GBLS SystemName
[ M_Omega :LOR: M_Lazarus
......@@ -98,7 +100,7 @@ MEMC_Type SETS "IOMD"
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
[ M_CortexA8 :LOR: M_ARM11ZF
[ M_CortexA8 :LOR: M_CortexA9 :LOR: M_ARM11ZF
MEMM_Type SETS "VMSAv6"
|
MEMM_Type SETS "ARM600"
......@@ -143,12 +145,12 @@ No32bitCode SETL M_Morris :LOR: M_Phoebe :LOR: M_Falcon :LOR: M_Omega :LO
; Do we support 32-bit only processors? (ARM9, ARM10...)
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
[ :LNOT: M_All
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
; HAL32 indicates the new 32-bit memory map in use.
GBLL HAL26
......@@ -160,7 +162,7 @@ HAL26 SETL HAL :LAND: :LNOT: No26bitCode
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL M_CortexA8 :LOR: M_ARM11ZF
NoUnaligned SETL M_CortexA8 :LOR: M_ARM11ZF :LOR: M_CortexA9
[ :LNOT: M_All
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -227,12 +229,12 @@ ExtROMis16bit SETL M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
; Note that this also controls HAL NVRAM support, and RTCSupport.
GBLL E2ROMSupport
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_Tungsten :LOR: M_CortexA8
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_Tungsten :LOR: M_CortexA8 :LOR: M_CortexA9
; Should we probe IIC addresses &A0 and &D0 for an RTC? (Requires E2ROMSupport, else Phillips RTC at &A0 is assumed)
; Disabling this is useful for HAL platforms that use the HAL RTC API
GBLL RTCSupport
RTCSupport SETL :LNOT: (M_ARM11ZF :LOR: M_CortexA8)
RTCSupport SETL :LNOT: (M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9)
; Support for 82C710 and 82C711 combo chips in addition to 665
GBLL OldComboSupport
......
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