Commit b3bff27a authored by Ben Avison's avatar Ben Avison
Browse files

Added support for Machine=ARM11ZF

Detail:
  Suitable for ARMv6Z CPUs with VFPv2, e.g. ARM1176JZF-S
Admin:
  Required by the S3C6410 HAL

Version 1.82. Tagged as 'HdrSrc-1_82'
parent 3359afa1
/* (1.81)
/* (1.82)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.81
#define Module_MajorVersion_CMHG 1.82
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 22 May 2011
#define Module_Date_CMHG 03 Jun 2011
#define Module_MajorVersion "1.81"
#define Module_Version 181
#define Module_MajorVersion "1.82"
#define Module_Version 182
#define Module_MinorVersion ""
#define Module_Date "22 May 2011"
#define Module_Date "03 Jun 2011"
#define Module_ApplicationDate "22-May-11"
#define Module_ApplicationDate "03-Jun-11"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.81"
#define Module_HelpVersion "1.81 (22 May 2011)"
#define Module_LibraryVersionInfo "1:81"
#define Module_FullVersion "1.82"
#define Module_HelpVersion "1.82 (03 Jun 2011)"
#define Module_LibraryVersionInfo "1:82"
......@@ -433,6 +433,9 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
[ "$Machine" = "Tungsten" ; Iyonix PC
ArchitectureOption v5TEX
|
[ "$Machine" = "ARM11ZF"
ArchitectureOption v6K_VFP2D
|
[ "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7_VFP3D32_SIMD
|
......@@ -458,6 +461,7 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
]
]
]
]
]
GBLL SupportARMv3
......
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Architecture v6Z with VFPv2
GBLS Machine
Machine SETS "ARM11ZF"
GET Hdr:Machine.Machine
END
......@@ -47,6 +47,7 @@ Included_Hdr_Machine_Machine SETL {TRUE}
GBLL M_Phoebe
GBLL M_Tungsten
GBLL M_32
GBLL M_ARM11ZF
GBLL M_CortexA8
M_All SETL Machine="All"
M_Falcon SETL Machine="Falcon"
......@@ -60,6 +61,7 @@ M_STB5 SETL Machine="STB5"
M_Phoebe SETL Machine="Phoebe"
M_Tungsten SETL Machine="Tungsten"
M_32 SETL Machine="32"
M_ARM11ZF SETL Machine="ARM11ZF"
M_CortexA8 SETL Machine="CortexA8"
GBLS SystemName
......@@ -141,12 +143,12 @@ No32bitCode SETL M_Morris :LOR: M_Phoebe :LOR: M_Falcon :LOR: M_Omega :LO
; Do we support 32-bit only processors? (ARM9, ARM10...)
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_CortexA8
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8
[ :LNOT: M_All
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_CortexA8
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8
; HAL32 indicates the new 32-bit memory map in use.
GBLL HAL26
......@@ -230,7 +232,7 @@ E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_
; Should we probe IIC addresses &A0 and &D0 for an RTC? (Requires E2ROMSupport, else Phillips RTC at &A0 is assumed)
; Disabling this is useful for HAL platforms that use the HAL RTC API
GBLL RTCSupport
RTCSupport SETL :LNOT: (M_CortexA8)
RTCSupport SETL :LNOT: (M_ARM11ZF :LOR: M_CortexA8)
; Support for 82C710 and 82C711 combo chips in addition to 665
GBLL OldComboSupport
......
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