Commit 2e57ccf9 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Update HdrSrc for correct ARM11ZF settings

Detail:
  hdr/Machine/Machine - Use VMSAv6 and disable unaligned memory accesses when compiling for ARM11ZF (i.e. ARMv6)
Admin:
  Tested with S3C6440 ROM build. Untested at runtime.


Version 1.83. Tagged as 'HdrSrc-1_83'
parent b3bff27a
/* (1.82)
/* (1.83)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.82
#define Module_MajorVersion_CMHG 1.83
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 03 Jun 2011
#define Module_Date_CMHG 04 Jun 2011
#define Module_MajorVersion "1.82"
#define Module_Version 182
#define Module_MajorVersion "1.83"
#define Module_Version 183
#define Module_MinorVersion ""
#define Module_Date "03 Jun 2011"
#define Module_Date "04 Jun 2011"
#define Module_ApplicationDate "03-Jun-11"
#define Module_ApplicationDate "04-Jun-11"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.82"
#define Module_HelpVersion "1.82 (03 Jun 2011)"
#define Module_LibraryVersionInfo "1:82"
#define Module_FullVersion "1.83"
#define Module_HelpVersion "1.83 (04 Jun 2011)"
#define Module_LibraryVersionInfo "1:83"
......@@ -98,7 +98,7 @@ MEMC_Type SETS "IOMD"
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
[ M_CortexA8
[ M_CortexA8 :LOR: M_ARM11ZF
MEMM_Type SETS "VMSAv6"
|
MEMM_Type SETS "ARM600"
......@@ -160,7 +160,7 @@ HAL26 SETL HAL :LAND: :LNOT: No26bitCode
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL M_CortexA8
NoUnaligned SETL M_CortexA8 :LOR: M_ARM11ZF
[ :LNOT: M_All
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......
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