Commit 934e1a24 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Merge Cortex branch of HdrSrc into trunk

Detail:
  This should merge all of the Cortex HdrSrc changes into the trunk, so we don't have to worry about OMAP builds breaking each time the trunk HdrSrc changes
Admin:
  Untested!


Version 1.76. Tagged as 'HdrSrc-1_76'
parent 5b1e820c
......@@ -84,6 +84,7 @@ EXPORTS = \
${HDRDIR}.ListOpts \
${HDRDIR}.MEMM.ARM600 \
${HDRDIR}.MEMM.MEMC1 \
${HDRDIR}.MEMM.VMSAv6 \
${HDRDIR}.Machine.<Machine> \
${HDRDIR}.Machine.Machine \
${HDRDIR}.Macros \
......@@ -295,6 +296,7 @@ ${HDRDIR}.IO.IOMD: hdr.IO.IOMD; ${CP} hdr.IO.IOMD
${HDRDIR}.IO.IOMDL: hdr.IO.IOMDL; ${CP} hdr.IO.IOMDL $@ ${CPFLAGS}
${HDRDIR}.MEMM.ARM600: hdr.MEMM.ARM600; ${CP} hdr.MEMM.ARM600 $@ ${CPFLAGS}
${HDRDIR}.MEMM.MEMC1: hdr.MEMM.MEMC1; ${CP} hdr.MEMM.MEMC1 $@ ${CPFLAGS}
${HDRDIR}.MEMM.VMSAv6: hdr.MEMM.VMSAv6; ${CP} hdr.MEMM.VMSAv6 $@ ${CPFLAGS}
${HDRDIR}.VIDC.VIDC1a: hdr.VIDC.VIDC1a; ${CP} hdr.VIDC.VIDC1a $@ ${CPFLAGS}
${HDRDIR}.VIDC.VIDC20: hdr.VIDC.VIDC20; ${CP} hdr.VIDC.VIDC20 $@ ${CPFLAGS}
......
/* (1.75)
/* (1.76)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.75
#define Module_MajorVersion_CMHG 1.76
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 05 Dec 2010
#define Module_Date_CMHG 15 Jan 2011
#define Module_MajorVersion "1.75"
#define Module_Version 175
#define Module_MajorVersion "1.76"
#define Module_Version 176
#define Module_MinorVersion ""
#define Module_Date "05 Dec 2010"
#define Module_Date "15 Jan 2011"
#define Module_ApplicationDate "05-Dec-10"
#define Module_ApplicationDate "15-Jan-11"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.75"
#define Module_HelpVersion "1.75 (05 Dec 2010)"
#define Module_LibraryVersionInfo "1:75"
#define Module_FullVersion "1.76"
#define Module_HelpVersion "1.76 (15 Jan 2011)"
#define Module_LibraryVersionInfo "1:76"
......@@ -125,6 +125,7 @@ CT_ctype_WB_CR7 * 2 ; write-back, clean with register 7
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDa * 6 ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb * 7 ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_size_pos * 6
CT_size_mask * 7:SHL:CT_size_pos
......
; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > hdr:VMSAv6
; ********************
; *** Changes List ***
; ********************
; 18-Feb-09 JL Created, using ARM600 as basis.
; Access privilege bits
; These comprise the AP and APX bits, which are luckily always in the same location relative to each other
AP_ROM * 2_100010 ; user read-only, svc read-only
AP_None * 2_000001 ; user no access, svc read/write
AP_Read * 2_000010 ; user read-only, svc read/write
AP_Full * 2_000011 ; user read/write, svc read/write
L1_APShift * 10 ; value to shift AP_ values by for L1 entry
L2_APShift * 4 ; value to shift AP_ values by for L2 entry
L1_APMult * 1 :SHL: L1_APShift ; value to multiply AP_ values by for L1 entry
L2_APMult * 1 :SHL: L2_APShift ; value to multiply AP_ values by for L2 entry
L2X_APMult * L2_APMult
L1_AP * 2_100011 * L1_APMult ; masks for AP fields
L2_AP * 2_100011 * L2_APMult
L1_DomainShift * 5 ; lowest bit position in L1 entry for domain number
L1_Fault * 4_0 ; translation fault specifier in L1 entry
L1_Page * 4_1 ; coarse page specifier in L1 entry
L1_Section * 4_2 ; section specifier in L1 entry
; supersections not supported ATM
L2_Fault * 4_0 ; translation fault specifier in L2 entry
L2_LargePage * 4_1 ; large page specifier in L2 entry
L2_SmallPage * 4_2 ; (extended) small page specifier in L2 entry
L2_ExtPage * L2_SmallPage
L1_TEXShift * 12
L1_TEX * 2_1111 :SHL: 12 ; Type Extension bits
L1_C * 1 :SHL: 3 ; cacheable
L1_B * 1 :SHL: 2 ; bufferable
L1_nG * 1 :SHL: 17 ; 1=entry associated with ASID, 0=global
L1_XN * 1 :SHL: 4 ; eXecute Never
L1_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (is TEX bit 0)
L2L_TEXShift * 12 ; For large pages
L2_TEXShift * 6 ; For extended small pages
L2L_TEX * 2_1111 :SHL: 12 ; Type Extension bits (large pages)
L2_TEX * 2_1111 :SHL: 6 ; Type Extension bits (tiny and extended pages)
L2_C * 1 :SHL: 3 ; cacheable bit in level 2 entry
L2_B * 1 :SHL: 2 ; bufferable --------""----------
L2_nG * 1 :SHL: 11 ; 1=entry associated with ASID, 0=global
L2L_XN * 1 :SHL: 15 ; eXecute Never for large pages
L2_XN * 1 ; eXecute Never for extended small pages
L2L_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (large pages) (is TEX bit 0)
L2_X * 1 :SHL: 6 ; XScale - modifies meaning of C and B bits (tiny and extended pages) (is TEX bit 0)
; CP15 control register bits
; Retaining MMUC_* naming for compatability with existing code
; Validity: 5 = ARMv5 or older, 6=ARMv6, C=Cortex, !=Warning, bit reused
MMUC_M * 1 :SHL: 0 ; 56C MMU enable
MMUC_A * 1 :SHL: 1 ; 56C Alignment fault enable
MMUC_C * 1 :SHL: 2 ; 56C Cache enable (or Data cache enable)
MMUC_W * 1 :SHL: 3 ; 56 Write buffer enable
MMUC_P * 1 :SHL: 4 ; 5 32-bit program space enable
MMUC_D * 1 :SHL: 5 ; 5 32-bit data space enable
MMUC_L * 1 :SHL: 6 ; 5 Late abort mode enable
MMUC_B * 1 :SHL: 7 ; 56 Big-endian mode enable
MMUC_S * 1 :SHL: 8 ; 5 S-mode enable
MMUC_R * 1 :SHL: 9 ; 5 R-mode enable (ARM7 or later)
MMUC_F * 1 :SHL: 10 ; 5 Coprocessor frequency bit (ARM700 only)
MMUC_Z * 1 :SHL: 11 ; 56C Branch predictor enable
MMUC_I * 1 :SHL: 12 ; 56C Instruction cache enable
MMUC_V * 1 :SHL: 13 ; 56C High exception vectors
MMUC_RR * 1 :SHL: 14 ; 56 Round-robin/alternate cache replacement strategy
MMUC_L4 * 1 :SHL: 15 ; 5 Disable ARMv5 "load Thumb state with PC" behaviour
MMUC_U * 1 :SHL: 22 ; 6 Unaligned data access operation
MMUC_XP * 1 :SHL: 23 ; 6 Extended page table config
MMUC_VE * 1 :SHL: 24 ; 6 Vectored interrupts
MMUC_EE * 1 :SHL: 25 ; 6C Exception Endian bit
MMUC_L2 * 1 :SHL: 26 ; 6 L2 unified cache enable
MMUC_NMFI * 1:SHL: 27 ; C Non-maskable FIQ (read-only)
MMUC_TRE * 1 :SHL: 28 ; C TEX remap enable
MMUC_AFE * 1 :SHL: 29 ; C Access Flag Enable (AP[0] remap)
MMUC_nF * 1 :SHL: 30 ; 5!! not FastBus (ie separate CPUCLK from MEMCLK)
MMUC_TE * 1 :SHL: 30 ; !!C Exceptions handled in Thumb mode
MMUC_iA * 1 :SHL: 31 ; 5 Asynchronous
; ARM600 MMU coprocessor number
Arm600Cop CP 15
; ARM600 coprocessor registers
CR_Dummy CN 0
CR_ID CN 0 ; read-only
CR_Control CN 1 ; read/write
CR_TTabBase CN 2 ; read/write
CR_Domains CN 3 ; read/write
CR_FaultStatus CN 5 ; read
CR_FaultAddress CN 6 ; read
; Cache type register fields
; NOTE - need to be kept in sync with hdr.MEMM.ARM600!
CT_ctype_pos * 25
CT_ctype_mask * &F:SHL:CT_ctype_pos
CT_S_pos * 24
CT_S * 1:SHL:CT_S_pos
CT_Dsize_pos * 12
CT_Dsize_mask * &FFF:SHL:CT_Dsize_pos
CT_Isize_pos * 0
CT_Isize_mask * &FFF:SHL:CT_Isize_pos
CT_ctype_WT * 0 ; write-through cache
CT_ctype_WB_Crd * 1 ; write-back, clean by reading data
CT_ctype_WB_CR7 * 2 ; write-back, clean with register 7
CT_ctype_WB_Cal_LD * 5 ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDa * 6 ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb * 7 ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx * 8 ; write-back, clean with register 7, multiple cache levels
CT_size_pos * 6
CT_size_mask * 7:SHL:CT_size_pos
CT_assoc_pos * 3
CT_assoc_mask * 7:SHL:CT_assoc_pos
CT_M_pos * 2
CT_M * 1:SHL:CT_M_pos
CT_len_pos * 0
CT_len_mask * 3:SHL:CT_len_pos
CT_size_512 * 0
CT_size_1K * 1
CT_size_2K * 2
CT_size_4K * 3
CT_size_8K * 4
CT_size_16K * 5
CT_size_32K * 6
CT_size_64K * 7
CT_size_768 * 0
CT_size_1536 * 1
CT_size_3K * 2
CT_size_6K * 3
CT_size_12K * 4
CT_size_24K * 5
CT_size_48K * 6
CT_size_96K * 7
CT_assoc_1 * 0
CT_assoc_2 * 1
CT_assoc_4 * 2
CT_assoc_8 * 3
CT_assoc_16 * 4
CT_assoc_32 * 5
CT_assoc_64 * 6
CT_assoc_128 * 7
CT_assoc_0 * 0
CT_assoc_3 * 1
CT_assoc_6 * 2
CT_assoc_12 * 3
CT_assoc_24 * 4
CT_assoc_48 * 5
CT_assoc_96 * 6
CT_assoc_192 * 7
CT_len_2 * 0
CT_len_4 * 1
CT_len_8 * 2
CT_len_16 * 3
CT_M_512 * 0
CT_M_1K * 0
CT_M_2K * 0
CT_M_4K * 0
CT_M_8K * 0
CT_M_16K * 0
CT_M_32K * 0
CT_M_64K * 0
CT_M_768 * 1
CT_M_1536 * 1
CT_M_3K * 1
CT_M_6K * 1
CT_M_12K * 1
CT_M_24K * 1
CT_M_48K * 1
CT_M_96K * 1
MACRO
SetCop $reg, $cop, $rm, $op2, $cc
[ "$op2" = ""
MCR$cc Arm600Cop, 0, $reg, $cop, CR_Dummy
|
MCR$cc Arm600Cop, 0, $reg, $cop, $rm, $op2
]
MEND
MACRO
ReadCop $reg, $cop, $rm, $op2, $cc
[ "$op2" = ""
MRC$cc Arm600Cop, 0, $reg, $cop, CR_Dummy
|
MRC$cc Arm600Cop, 0, $reg, $cop, $rm, $op2
]
MEND
END
; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Cortex-A8 machine: ARMv7 + NEON
GBLS Machine
Machine SETS "CortexA8"
GET Hdr:Machine.Machine
END
......@@ -47,6 +47,7 @@ Included_Hdr_Machine_Machine SETL {TRUE}
GBLL M_Phoebe
GBLL M_Tungsten
GBLL M_32
GBLL M_CortexA8
M_All SETL Machine="All"
M_Falcon SETL Machine="Falcon"
M_Morris SETL Machine="Morris"
......@@ -59,6 +60,7 @@ M_STB5 SETL Machine="STB5"
M_Phoebe SETL Machine="Phoebe"
M_Tungsten SETL Machine="Tungsten"
M_32 SETL Machine="32"
M_CortexA8 SETL Machine="CortexA8"
GBLS SystemName
[ M_Omega :LOR: M_Lazarus
......@@ -94,9 +96,13 @@ MEMC_Type SETS "IOMD"
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
[ M_CortexA8
MEMM_Type SETS "VMSAv6"
|
MEMM_Type SETS "ARM600"
]
GBLS GetMEMM
GetMEMM SETS "GET Hdr:MEMM.ARM600"
GetMEMM SETS "GET Hdr:MEMM." :CC: MEMM_Type
; floppy controller
GBLS FDC_Type
......@@ -135,12 +141,12 @@ No32bitCode SETL M_Morris :LOR: M_Phoebe :LOR: M_Falcon :LOR: M_Omega :LO
; Do we support 32-bit only processors? (ARM9, ARM10...)
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_CortexA8
[ :LNOT: M_All
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_CortexA8
; HAL32 indicates the new 32-bit memory map in use.
GBLL HAL26
......@@ -152,9 +158,8 @@ HAL26 SETL HAL :LAND: :LNOT: No26bitCode
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL {FALSE}
NoUnaligned SETL M_CortexA8
[ :LNOT: M_All
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; System build options added for STB/NCD
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -217,13 +222,14 @@ CanLiveOnROMCard SETL ROMCardSupport :LAND: {TRUE}
ExtROMis16bit SETL M_Falcon :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
; Note that this also controls HAL NVRAM support, and RTCSupport.
GBLL E2ROMSupport
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_Tungsten
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_Tungsten :LOR: M_CortexA8
; RTC is supported at IIC &A0 or &D0 (should really be HAL, but defer until
; there's a full HAL RTC API).
; Should we probe IIC addresses &A0 and &D0 for an RTC? (Requires E2ROMSupport, else Phillips RTC at &A0 is assumed)
; Disabling this is useful for HAL platforms that use the HAL RTC API
GBLL RTCSupport
RTCSupport SETL {TRUE}
RTCSupport SETL :LNOT: (M_CortexA8)
; Support for 82C710 and 82C711 combo chips in addition to 665
GBLL OldComboSupport
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment