GitLab

*Configure ANYTHINGsize was broken due to not setting R0 to ReadUnsigned
IIC ack message uninternationalised
OS_Memory was saying we only had 4M of RAM
VDU4 scrolling when output was switched to sprite was causing corruption
on use of CTRL-J and CTRL-K
Default SystemSize CMOS set to 32k

Version 5.35, 4.79.2.55. Tagged as 'Kernel-5_35-4_79_2_55'

Detail:
  Lots of changes since last version, at least the following:
  * Updated OS timestamp, removed alpha status
  * Negative INKEY OS version changed to &AA
  * GraphicsV is now alocated vector number &2A
  * ROM moved up to &FC000000
  * Max application slot increased to 512 Mbytes (for now)
  * Max size of RMA increased to 256 Mbytes
  * RMA is now first-created dynamic area (so it gets lowest address after
    top of application slot)
  * OS_Memory 10 reimplemeted
  * New OS_ReadSysInfo 6 values 18-22 added
  * OS_ReadSysInfo 8 gains flag bit to indicate soft power-off
  * Misc internal top-bit-set-address fixes
  * *ChangeDynamicArea can take sizes in megabytes or gigabytes
  * Magic word "&off" in R0 passed to OS_Reset powers down if possible
  * Added acceleration: block copy; CLS; text window scroll up; rectangle
    fill
  * Disabled LED flashing in page mode (liable to crash)
  * Masked sprite plot and VDU 5 text avoids reading the screen if poss...

Version 5.35, 4.79.2.48. Tagged as 'Kernel-5_35-4_79_2_48'

1) Bring IOMD HAL more up to date. Add support for new call HAL_CleanerSpace (preparation for StrongARM kernel support).

2) In kernel, add HAL_CleanerSpace call (preparation for
StrongARM and XScale core support). Fix bug found with
ARMv3 support during test on Risc PC.

3) Implement new API for kernel SWIs that have used top
bits of addresses as flags. The new API has an extra
flag that must be set, so kernel can distinguish and
support both APIs. The reason for all this is that
addresses are 32-bits now, people, keep up there. Briefly:

  OS_HeapSort
    bit 31 of r0 set for new API, r1 is full 32-bit address
    flags move from r1 bits 31-29 to r0 bits 30-28

  OS_ReadLine
    bit 31 of r1 set for new API, r0 is full 32-bit address
    flags move from bits 31,30 of r0 to bits 30,29 of r1

  OS_SubstituteArgs
    bit 31 of r2 set for new API, r0 is full 32-bit address
    flag moves from bit 31 of r0 to bit 30 of r2

Tested on Risc PC and briefly on Customer A 2

Ta

Version 5.35, 4.79.2.41. Tagged as 'Kernel-5_35-4_79_2_41'

Ursula. Quite a hairy code merge really, so let's hope it is
worth it to someone. What you get (back after 2 or 3 years):
- much more efficient for largish numbers of DAs (relevance
  to current build = approx 0)
- fancy reason codes to support fast update of
  Switcher bar display (relevance = 0)
- support for clamped maximum area sizes, to avoid address
  space exhaustion with big memory (relevance = 0)
- better implementation of shrinkable DAs, performance
  wise (if lots of DAs, relevance = approx 0)
- support for 'Sparse' DAs. Holey dynamic areas, Batman!
  (relevance, go on someone use the darned things)
Moderately development tested on HAL/32bit ARM9 desktop.
Note the Switcher should be compiled to use the new
reason codes 6&7, for fabled desktop builds.

Also, during this work, so I could see the wood for the
trees, redid some source code clean up, removing pre-Medusa
stuff (like I did about 3 years ago on Ursula, sigh). That's
why loads of source files have changed. The new DA stuff
is confined pretty much to hdr.KernelWS and s.ChangeDyn.

Ta.

Version 5.35, 4.79.2.38. Tagged as 'Kernel-5_35-4_79_2_38'

* Allows HAL-driven software resets.
* Sound buffers corrected to be uncacheable.

Version 5.35, 4.79.2.33. Tagged as 'Kernel-5_35-4_79_2_33'

More stuff. Up to the desktop now; cache on, working keyboard. Some source restructuring to start to make splitting it up into several object files more feasible.

Detail:
  Added the HAL NVRAM entries.
  Modified i2cutils to use the HAL entries for NVRAM and behave sensibly if the HAL reports that there is no NVRAM, in which case there must be a forced reset_cmos call so that the cache gets set up sensibly.
Admin:
  Tested under the RPC emulator and appears to be working correctly, although some calls to IIC are still being made in the no nvram case.

Version 5.35, 4.79.2.8. Tagged as 'Kernel-5_35-4_79_2_8'

* Added ARM_IMB and ARM_IMBRange SWIs as recommended by ARMv5.
* Some early prototype HAL bits popped in - a lot of source restructuring still
  to come.
* New debug target creates an AIF image with debug information, and translates
  this into an ASCII object file for the 16702B logic analyser.

Version 5.35, 4.79.2.1. Tagged as 'Kernel-5_35-4_79_2_1'

(NVRamSpeed is not defined in the Kernel workspace so we need an
 alternative way to work the speed of the I2C bus - so I've used
 I2Cticks - defined in PMF.i2cutils)

Version 5.34. Tagged as 'Kernel-5_34'

  New routine in i2cutils that allows access to protected sections such as
  MAC address
  OS_ReadSysInfo 4 now checks both copies MACAddress if MACNVRAM2copies is set
Detail:
  32K EEPROM has to be configured with IIC address &A6 (i.e wired up on the pcb)
  ClockNVMemoryFast has been replaced with MaxI2Cspeed so that several different
  rates can be used depending on the devices on the IIC bus.
Admin:
  Need to implement routine that can use one copy of the MAC address to
  replace the other in the event of it being corrupted.


Version 5.33. Tagged as 'Kernel-5_33'

Had one of those weekend brainstorms - managed to speed up SWI despatcher _and_ add Thumb support to it.

Fixed OS_BreakPt - was confused by PC/PSR split.

Version 5.24. Not tagged

Detail:
  "Podule" number now displayed again in *ROMModule output - flag
     preservation issue caused it to disappear in 5.23.
  *Eval output no longer misses its trailing space, neither do "Podule" or
    "Extn ROM" in *ROMModules output.
  Heap manager now works again in non-SVC modes.
  Exception dump now contains faked up 26-bit PC+PSR lookalike.
Admin:
  Assembled.

Details:
  The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
  set to TRUE.
  If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
  although some internal changes have taken place to minimise compile
  switches between the two cases. See Docs.32bit for more technical info.

  The hardest part was the flood-fill...

Other changes:
  Pointer shape changes now take place on the next VSync, rather than actually
  WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
  down by 5% now :)

  Lots of really crusty pre-IOMD code removed.

Admin:
  Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
  will need to see a lot of use to iron out difficulties. I'd like anyone who
  has a non-frozen project to at least attempt using this Kernel.

Version 5.23. Tagged as 'Kernel-5_23'

Detail:
  MACFROMNVRAM was intended to force the Kernel to fetch the MAC
  address from NVRAM for Customer F 5. In practice it is not needed
  as its main purpose was to avoid getting the MAC address from
  the RawMachineID but this will not happen in Customer F 5 as
  RawMachineID will not be set.

Admin:
  Not tested.
  MACFROMNVRAM will be removed from HdrSrc.

Version 5.17. Tagged as 'Kernel-5_17'

  Ensured that M_Phoebe builds set UtilityModule version to 4.00
Detail:
  The softload utility relies on the existence of the extra reason codes
    to OS_ReadSysInfo introduced in Ursula.  The main kernel now supports
    these too (they are simply interfaces to read kernel capabilities and
    configuration - eg. addresses and sizes of UND and SVC mode stacks)
  Avoid OS_ReadSysInfo 9 - ROL have used it for reading the ROM personality
    information (and it's not in our kernel)
  Added some of the new macros into Copro15ops required by the ABT dump
    area code (returned by OS_ReadSysInfo 7) and added the code into ARM600
    to store abort information there.
Admin:
  Required by softload utility for Ursula builds.
  Tested on Risc PC.

Version 5.15. Tagged as 'Kernel-5_15'

  MACFROMNVRAM is set. This is set in HdrSrc for Customer F machines.

Detail:
  If MACFROMNVRAM is TRUE then OS_ReadSysInfo 4 will read the Ethernet MAC
  Address from bytes 0-13 of the NVRAM area, instead of trying to read it
  from anywhere else. (14 bytes are ysed to store 2 copies and 2
  checksums).

  This is intended for use with a 24LC128 device (which has no OTP area
  and no clock).

  Note that these are physical addresses within the device. Logical
  addresses &F0-&FF map to physical addresses &00-&0F.

  A SetMac utility is provided in Customer F 5 !Boot.Utils to enable the MAC
  address to be programmed for prototypes and development machines.

  Since it is dangerous to rely on the NVRAM to hold our MAC address when
  it is not protected in any way, we store two copies of it, each with
  their own checksum. At present only the first copy is used, but the
  plan is to check both copies and both checksums.

Admin:
  This version of the Kernel needs Programmer/HdrSrc v0.68 or later.

  If MACFROMNVRAM is enabled, ensure that the MACADDRESS tag in the
  NVRAM file is set to point at &F0 and that MACADDRESSCHECKSUM
  is set to point at &F6. Both should have options L and P to ensure
  they are protected from NVRAM resets and other writes.

Version 5.09. Tagged as 'Kernel-5_09'

OS_ReadSysInfo 2 now reports whether the IIC bus is fast (in bit 24 of R2), and whether I/O clocks should be stopped when idling the processor (bit 25).

OS_Byte 19 is a bit more careful in its use of Portable_Idle - an edge case
where the vsync interrupt was already pending now returns immediately.

Version 5.07. Tagged as 'Kernel-5_07'

If reassigned, ReadSysInfo3 returns &00x22200 in R0, to indicate that the
serial and parallel ports aren't compatible, and IDE and floppy are
unavailable.

Version 5.01. Tagged as 'Kernel-5_01'

This has been fixed. In addition, SMC669 and UMC669 chips are reported as
a different chip configuration by OS_ReadSysInfo 3 (values 4 and 5
respectively).
A few assertions added to catch the remaining cases where the RCMM stuff
won't work - those cases will involve a bit more reordering of hardware
initialisation.

Version 5.00. Tagged as 'Kernel-5_00'

ROM speed not taken from the Machine header file.  POST can now exist in a softloaded OS, since it searches for a zero word in the ROM instead of using one within the POST when trying to communicate with the POST adapter (the zero word must be in ROM).  Fixed to build on non-chrontel STB/NC products.  Lots of duplicate code merged in

MemSize.  MemSize copes better with the softload case, and is less
willing to use the region the OS occupies as video memory, or
page tables.  POST is now ON (memory tests disabled).
OS_ReadSysInfo 4 now uses the NVRAM module to access the ethernet
address in NVRAM/CMOS, so that the availability/location of the
MAC address can be changed.  CMOS location 0 is now unprotected on
STB/NC products to try to stop people poking the hardware directly.
Fixed a CMOS resetting problem on STBs where the value expected in a
location was different from the value written on a CMOS reset, so the
CMOS would be reset every time...

Version 4.69. Tagged as 'Kernel-4_69'

Not fully tested on all hardware permutations.