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Commit e769c131 authored by Kevin Bracey's avatar Kevin Bracey
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RISC OS 3.71 kernel changes merged. 

Not fully tested on all hardware permutations.
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TestSrc/Begin
View file @ e769c131
......@@ -107,7 +107,7 @@ ShowIOMDRegs SETL (IO_Type = "IOMD") :LAND: {TRUE} :LAND: STB ; show IOMD reg
DontShowProgressColours SETL {TRUE} :LAND: STB ; Do not show the progress colour screens.
; Progress Colours will always be shown when using POST Box.
; Set to true for NC - Fault Report ANC-00159.
ts_Rom_bits * 21 ; Widest ROM address
......@@ -359,6 +359,20 @@ ts_ROM_bvectors
SetMode SVC32_mode,$tmp
MEND
[ StrongARM_POST
; ensure 26-bit mode for StrongARM or ARM 8 (since there is no 26 bit configuration)
MACRO
Ensure26bit_ARM8A $tmp
ARM_read_ID $tmp
AND $tmp, $tmp, #&F000
CMP $tmp, #&A000
CMPNE $tmp, #&8000
mrs EQ, $tmp, CPSR_all
BICEQ $tmp, $tmp, #&10
msr EQ, CPSR_all, $tmp
MEND
]
;
; Define an area of storage with the required set of data bus patterns
; These are used both for testing the complete width of the data bus
......@@ -556,8 +570,13 @@ ts_User_startup ROUT
ADDS r1,r1,r1 ; then shift it into carry
BCC ts_Self_test_end ; POR bit clear - do soft reset.
; it's a power-on reset, so assume we can't be in 32-bit mode
; it's a power-on reset, so assume we can't be in 32-bit mode for ARM 6/7
[ StrongARM_POST
; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
; note that MOV_fiq macro assumes 26-bit, so must sort this now
Ensure26bit_ARM8A r0
]
MOV_fiq r12_fiq, #R_HARD
B ts_Self_test_startup
|
......@@ -576,6 +595,11 @@ ts_User_startup ROUT
ts_Forced_startup ROUT
[ StrongARM_POST
; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
; note that MOV_fiq macro assumes 26-bit, so must sort this now
Ensure26bit_ARM8A r0
]
MOV_fiq r12_fiq, #R_TESTED
B ts_Self_test_startup
......@@ -583,6 +607,11 @@ ts_Forced_startup ROUT
ts_Dealer_startup ROUT
[ StrongARM_POST
; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
; note that MOV_fiq macro assumes 26-bit, so must sort this now
Ensure26bit_ARM8A r4
]
MOV_fiq r12_fiq, #R_EXTERN
LDR r4,%FT02 ; make a pointer to signon string
......@@ -626,7 +655,14 @@ ts_Self_test_startup ROUT
CMPNES r0,r1 ; If not ID1, check for IOMD ID Code #3
BNE %FT10 ; Not equal; not an ARM7500 or an ARM7500FE - skip
; Here bceause its an ARM7500 'FE' variant
[ RO371Timings
05
MOV r0, #0 ;Calling from POST
BL TimeCPU ;just sets things according to assumed bus speeds for each IOMD id, in this case
| ; else if not RO371Timings
; Here because its an ARM7500 'FE' variant
; Program the CPU, Memory and IO clock prescalers
; Set the prescalers to :-
; CPUCLK divide by 2
......@@ -692,6 +728,9 @@ ts_Self_test_startup ROUT
MOVNE r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_32bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
STRB r0, [r2, #IOMD_ROMCR1] ; Otherwise program it the same
]
] ;RO371Timings conditional
;
10
]
......@@ -750,14 +789,25 @@ DoROMCardThings SETS ""
]
MOV r1, #ts_VIDCPhys
[ StrongARM
;just too horrible to fix POST for StrongARM (Architecture 4) at the moment
ARM_read_ID r0
AND r0,r0,#&F000
CMP r0,#&A000 ;if we are a StrongARM...
LDREQ r0,=C_WARMSTART ;the colour that indicates no POST performed
STREQ r0,[r1]
BEQ ts_Hardstart ;RISC OS - right now!
[ :LNOT: StrongARM_POST
;skip POST for StrongARM or ARM8
ARM_read_ID r0
AND r0,r0,#&F000
CMP r0,#&A000 ;if we are a StrongARM...
CMPNE r0,#&8000 ;or an ARM8...
LDREQ r0,=C_WARMSTART ;the colour that indicates no POST performed
STREQ r0,[r1]
BEQ ts_Hardstart ;RISC OS - right now!
]
[ ARM810support :LAND: (:LNOT: ARM810_POST)
;just too horrible to fix POST for ARM 8 at the moment
ARM_read_ID r0
AND r0,r0,#&F000
CMP r0,#&8000 ;if we are an ARM 8
LDREQ r0,=C_WARMSTART ;the colour that indicates no POST performed
STREQ r0,[r1]
BEQ ts_Hardstart ;RISC OS - right now!
]
LDR r0, =C_ARMOK ; set initial screen colour
......@@ -1363,6 +1413,27 @@ ts_CAMtest
;
ts_restore_physical
[ StrongARM_POST
;make sure ARM810 cache or StrongARM data cache is cleaned/flushed, because we are going to remap
ARM_read_ID r5
AND r5,r5,#&F000
CMP r5,#&8000
BNE %FT22
;ARM810
;;; ARM8_cleanflush_IDC r5 ;not implemented yet
B %FT24
22
CMP r5,#&A000
BNE %FT24
;StrongARM
;tricky...we'll read 16k of data in current ROM space, to act as clean and flush of current data
MOV r3,pc
BIC r3,r3,#31 ;32 byte aligned
ARMA_clean_DC r3,r5,r7
24
] ;StrongARM_POST
MOV r5, pc ; obtain current address
SUB r5, r5,#PhysSpace ; adjust to point to unmapped version
MOV r5, r5, LSR #20 ; divide by 1MB
......@@ -1375,8 +1446,20 @@ ts_restore_physical
ADD r3, r3, #DRAMOffset_L1PT
STR r7, [r3, r5, LSL #2] ; store replacement entry in L1 (not U,C or B)
[ StrongARM_POST
;flush cache if ARM 6/7 (ARM 8,StrongARM already sorted, above)
;flush TLB(s)
ARM_read_ID r4
AND r4,r4,#&F000
CMP r4,#&8000 ;ARM 8?
CMPNE r4,#&A000 ;or StrongARM?
MCRNE ARM_config_cp,0,R0,ARM67_cacheflush_reg,C0,0 ;flush 6/7 cache
MCRNE ARM_config_cp,0,R0,ARM67_TLBflush_reg,C0,0 ;flush 6/7 TLB
MCREQ ARM_config_cp,0,R0,ARM8A_TLB_reg,C7,0 ;flush 8/StrongARM TLB(s)
|
SetCop r7, CR_IDCFlush ; flush cache + TLB just in case
SetCop r7, CR_TLBFlush ; (data written is irrelevant)
]
; The ROM should now be mapped at the present address less PhysSpace, which is where it
; would be if the MMU were turned off.
......@@ -1385,11 +1468,16 @@ ts_restore_physical
SUB pc,pc,r4
NOP ; this instruction is skipped
MOV r7, #MMUC_D ; Now turn the MMU off
; now turn the MMU off, also ensures 26 bit mode, if ARM 6/7 (since P bit zero)
MOV r7, #MMUC_D
SetCop r7, CR_Control
B ts_VIDCtest
[ StrongARM_POST
Ensure26bit_ARM8A r7
MOV r7, #MMUC_D ;avoid corrupting r7, just in case
]
B ts_VIDCtest
;
; The VIDC tests check vertical blanking frequency in a fixed video
......@@ -1793,16 +1881,16 @@ ts_665LEDaddr * (ts_PCaddress :OR: (&3f2 :SHL: 2))
;
ADDS r2,r2,r2
BCC %08
[ STB
[ STB
BL ld_LED_Delay ; call delay routine }
BL ld_LED_Delay ; call delay routine } One Seconds Worth
BL ld_LED_Delay ; call delay routine }
BL ld_LED_Delay ; call delay routine }
|
|
MOV r0,r7,LSL #2 ; then pause another second
05 SUBS r0,r0,#1
BNE %05
]
]
08
ANDS r2,r2,r2 ; all the bits displayed now ?
BNE %02
......@@ -1888,7 +1976,7 @@ ts_IOinitab
GET TestSrc.Ioc
GET TestSrc.Cmos
GET TestSrc.Arm3
; amg: 7/12/96 Renaissance. Once again I wish AASM could understand conditionals
; around GETs
......@@ -1905,7 +1993,7 @@ get_leddelay SETS ""
get_showiomdrs SETS ""
]
$get_toggleled
$get_leddelay
$get_leddelay
$get_showiomdrs
ALIGN 64 ; JRH: Kernel seems happier if we do this!
......
TestSrc/Mem1IOMD
View file @ e769c131
......@@ -67,9 +67,15 @@ ts_LineTest
;
MOV r14, #IOMD_Base
STRB r11, [r14, #IOMD_DRAMWID]
MOV r0,#MMUC_D ; enable 32-bit addressing of data
; enable 32-bit addressing of data, also forces 26 bit mode, if ARM 6/7 (since P bit zero)
MOV r0,#MMUC_D
SetCop r0,CR_Control
[ StrongARM_POST
Ensure26bit_ARM8A r0
]
MOV r0,#0
MOV_fiq r9,r0 ; r9-fiq records low DRAM address for use elsewhere
......@@ -356,9 +362,15 @@ ts_LineTestIOMD
MOV r11, #IOMD_DRAMCR_DRAM_Large * &55 ; set all banks to be large initially
MOV r14, #IOMD_Base
STRB r11, [r14, #IOMD_DRAMCR]
MOV r0,#MMUC_D ; enable 32-bit addressing of data
; enable 32-bit addressing of data, also forces 26 bit mode, if ARM 6/7 (since P bit zero)
MOV r0,#MMUC_D
SetCop r0,CR_Control
[ StrongARM_POST
Ensure26bit_ARM8A r10
]
MOV r10, #0 ; indicate no RAM found yet
MOV r9, #IOMD_DRAMCR_DRAM_Small ; bit to OR into DRAMCR
MOV r12, #DRAM0PhysRam
......
TestSrc/Mem2
View file @ e769c131
;> MEM2C
;
;
; RISC OS 2+ BOOT TEST SOFTWARE
; MEMORY TEST 2 VERSION A.
; BRIAN RICE 30-10-89
; 06-Apr-90 ArtG 0.1 Test variable memory size
;
; This file will perform a simple test on all DRAM.
; The test code for this test was taken from thhe A680 Quick memory
; test software. The software was copied straight but the number of times
; The test code for this test was taken from thhe A680 Quick memory
; test software. The software was copied straight but the number of times
; the test looped arround was cut down to two loops, because of time
; constraints when testing the memory.
......@@ -50,8 +50,8 @@ test_mem_quit
ANDS r2,r2,#1 ; calculate expected data
ADREQ r12,%20 ; and load suitable message
ADRNE r12,%21
MOVS r0,r0 ; with zero flag set for PASS.
10
MOVS r0,r0 ; with zero flag set for PASS.
10
LDR pc,[r13,#Test_wks_return1]
; Fail messages indicate incorrect data read after WRote 0 or Wrote 1
......@@ -84,7 +84,7 @@ test_mem_code
STR r14, [r13, #Test_wks_return2]
;
; Copy the ram test code into low ram, modifying MOV instructions
; to MVN in accordance with the test pattern.
; to MVN in accordance with the test pattern.
;
ADR r1, test_mem_template
ADD r2, r13, #Test_code_off
......@@ -149,7 +149,7 @@ test_mem_code
; The following code is copied (and modified) into RAM for execution
;
test_mem_template
test_mem_template
ROUT
STR r0, test_mem_stadd ; save initial RAM address
STR r13, test_mem_base ; save test area base address
......@@ -188,7 +188,7 @@ test_mem_template
CMPEQ r11, #0 ; Converted to cmneq if bit = 1
CMPEQ r12, #0 ; Converted to cmneq if bit = 1
CMPEQ r13, #0 ; Converted to cmneq if bit = 1
test_mem_chk
test_mem_chk
BNE %F5 ; go report fault data
CMP r0, r14
BLO %B1 ; else loop for next batch
......@@ -201,7 +201,7 @@ test_mem_chk
; the first failing address and data.
; Note that the test instructions are copied to %8 to permit individual
; execution, and %7 is overwritten with an instruction used to copy
; the failing data into r1. Change this code very carefully !
; the failing data into r1. Change this code very carefully !
5
LDR r14,%2 ; Obtain first test in the set
......@@ -218,8 +218,8 @@ test_mem_chk
; r14 => failing instruction
LDR r1,[r14,#4]! ;fetch next instruction
AND r1,r1,#&f0000 ;make an instruction
MOV r1,r1,LSR #16 ;to copy the next register
AND r1,r1,#&f0000 ;make an instruction
MOV r1,r1,LSR #16 ;to copy the next register
ORR r1,r1,#&E1000000 ;down to r1
ORR r1,r1,#&00A00000 ;e.g. CMPEQ r10,#0
ORR r1,r1,#&00001000
......@@ -243,6 +243,27 @@ test_mem_template_end
ROUT
ts_remap_ttab
[ StrongARM_POST
;make sure ARM810 cache or StrongARM data cache is cleaned/flushed, because we are going to remap
ARM_read_ID r3
AND r3,r3,#&F000
CMP r3,#&8000
BNE %FT22
;ARM810
;;; ARM8_cleanflush_IDC r3 ;not implemented yet
B %FT24
22
CMP r3,#&A000
BNE %FT24
;StrongARM
;tricky...we'll read 16k of data in current ROM space, to act as clean and flush of current data
MOV r3,pc
BIC r3,r3,#31 ;32 byte aligned
ARMA_clean_DC r3,r4,r5
24
] ;StrongARM_POST
MOV r2,#FixedAreasL2Size
ADD r0,r0,r2 ; point to locations in PhysSpace
ADD r0,r0,#PhysSpace
......@@ -255,7 +276,7 @@ ts_remap_ttab
SUBS r2,r2,#(8*4)
BNE %BT10
SUB r9,r1,r0 ; r9 = offset from original to copy
SUB r9,r1,r0 ; r9 = offset from original to copy
ADD r0, r0, #DRAMOffset_L1PT-DRAMOffset_L2PT ; r0 -> copy of L1Phys
SUB r10, r0, #PhysSpace ; keep real address of L1PT for MMU
ADD r2,r0,#((1 :SHL: (32-20))*4) ; size of L1PT - 1 word per meg of memory
......@@ -265,14 +286,27 @@ ts_remap_ttab
SUBEQ r3,r3,r9 ; adjust the page table base address
STREQ r3,[r0,#-4]
CMPS r0,r2 ; repeat for all the level 1 table
BNE %BT11
BNE %BT11
SetCop r10, CR_TTabBase ; set up MMU pointer to L1
[ StrongARM_POST
;flush cache if ARM 6/7 (ARM 8,StrongARM already sorted, above)
;flush TLB(s)
ARM_read_ID r4
AND r4,r4,#&F000
CMP r4,#&8000 ;ARM 8?
CMPNE r4,#&A000 ;or StrongARM?
MCRNE ARM_config_cp,0,R0,ARM67_cacheflush_reg,C0,0 ;flush 6/7 cache
MCRNE ARM_config_cp,0,R0,ARM67_TLBflush_reg,C0,0 ;flush 6/7 TLB
MCREQ ARM_config_cp,0,R0,ARM8A_TLB_reg,C7,0 ;flush 8/StrongARM TLB(s)
|
SetCop r0, CR_IDCFlush ; flush cache + TLB just in case
SetCop r0, CR_TLBFlush ; (data written is irrelevant)
]
MOV pc,r14
END
TestSrc/Mem3
View file @ e769c131
......@@ -38,6 +38,10 @@ ts_CRCsize * (2 * 4)
ts_ROM_checksum
;StrongARM_POST issue:
;ARM810 - this will probably go bang! because ARM810 aborts if the processor
; vectors (00 - 1C) are read in 26-bit mode
MOV r1, #&00 ; initialise accumulator
ADRL r0, ROM ; initialise pointer using PC-relative
; addressing (could be 1st or 2nd bank)
......
Version
View file @ e769c131
......@@ -9,9 +9,9 @@ Version SETA 452
VString SETS "4.52"
Date SETS "07 Nov 1996" ; version for STB/NC OS
|
Version SETA 370
VString SETS "3.70"
Date SETS "30 Jul 1996" ; version for RISC OS on desktop computers
Version SETA 371
VString SETS "3.71"
Date SETS "19 Feb 1997" ; version for RISC OS on desktop computers
]
END
s/ARM600
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s/ChangeDyn
View file @ e769c131
......@@ -3439,6 +3439,15 @@ DoTheGrowPagesSpecified
BLEQ dtgps_SAcleanflush
]
[ ARM810support
;
; ARM810 has writeback cache too
;
ARM_number r0
CMP r0,#8
BLEQ dtgps_810cleanflush
]
; now move the pages
LDR r2, TotalAmount ; amount moving
......
s/GetAll
View file @ e769c131
......@@ -210,6 +210,17 @@ IncludeTestSrc SETL :LNOT: (MEMM_Type = "MEMC2") ; not on internal test vers
IncludeTestSrc SETL {FALSE} :LAND: :LNOT: STB
]
;RISC OS 3.71 onwards assumed bus timings - if true, then ROM speeds atc are assumed according to IOMD ID regs. as follows:
; if IOMD (Risc PC) ROM ticks 5-3 (assumed bus 32 MHz)
; if 7500 (A7000) ROM ticks 5-3 (assumed bus 32 MHz), all clocks divide-by-1
; if 7500FE (A7000+) ROM ticks 5-3,half speed (asssumed bus 64 MHz), EDO memory, divide-by-2 I/O, divide-by-1 CPU and memory
;
GBLL RO371Timings
RO371Timings SETL {TRUE}
[ :LNOT: RO371Timings
GBLL NormalSpeedROMS
[ STB
NormalSpeedROMS SETL {TRUE} ;use FALSE for slow EPROMS
......@@ -226,6 +237,8 @@ RISCPCBurstMode SETL {FALSE}
;>>>RISC PC (no reason why it shouldn't) all references to RISCPCBurstMode
;>>>could be replaced by NormalSpeedROMS
] ; :LNOT:RO371Timings
GBLL DoInitialiseMode
DoInitialiseMode SETL {TRUE} :LAND: STB
......@@ -309,16 +322,38 @@ IgnoreVRAM SETL {FALSE}
LateAborts SETL MEMM_Type = "ARM600" :LAND: {TRUE}
GBLL StrongARM
GBLL SAWBbroken ;whether StrongARM Write Buffer is broken (pass 1 silicon only)
GBLL SAcleanflushbroken ;whether StrongARM single MCR for DC clean+flush broken (is always for SA110)
GBLL SAUBxferbroken ;whether extra NOPs required for user bank STM/LDM (is so far)
GBLL SASTMhatbroken ;whether ROM must support SA110's with broken STM^ (revision 3 should fix this)
GBLL StrongARM_POST ;whether to run POST for StrongARM (and possibly ARM8)
GBLL ARM810support ;StrongARM must also be true for this to be useful
GBLL ARM810bpbroken ;whether branch predict is broken
GBLL ARM810cleanflushbroken ;whether single MCR for IDC clean+flush broken (a la StrongARM!)
GBLL ARM810fastclock ;whether to attempt to use fast clock (false means bus clock)
GBLL ARM810usePLL ;whether to use PLL for fast clock (else RefClk pin)
GBLL ARM810_POST ;whether to run POST for ARM810 (StrongARM_POST must also be true)
StrongARM SETL {TRUE}
SAWBbroken SETL {FALSE} :LAND: StrongARM
SAcleanflushbroken SETL {TRUE} :LAND: StrongARM
SAUBxferbroken SETL {TRUE} :LAND: StrongARM
SASTMhatbroken SETL {TRUE} :LAND: StrongARM
StrongARM_POST SETL {TRUE} :LAND: StrongARM
ARM810support SETL {FALSE} :LAND: StrongARM
ARM810bpbroken SETL {TRUE} :LAND: ARM810support
ARM810cleanflushbroken SETL {TRUE} :LAND: ARM810support
ARM810fastclock SETL {FALSE} :LAND: ARM810support
ARM810usePLL SETL {TRUE} :LAND: ARM810fastclock
ARM810_POST SETL {FALSE} :LAND: ARM810support
GBLL VCOstartfix ;code in early kernel to fix VCO start problem on A7000 (esp. 7500FE)
VCOstartfix SETL {TRUE}
GBLL MorrisIDString ;whether printed CPU string includes 7500/7500FE recognition
MorrisIDString SETL {TRUE} :LAND: StrongARM ;printed CPU type only implemented if StrongARM true
[ StrongARM
! 0," ______________________________________________________"
......
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