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Commit 2abb437b authored by Kevin Bracey's avatar Kevin Bracey
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More L7200 HAL work

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Docs/HAL/MoreEnts
View file @ 2abb437b
......@@ -276,3 +276,34 @@ Machine ID
unsigned int64 HAL_MachineID(void)
Returns a 64-bit unique machine identifier. What does it mean?
ControllerAddress
=================
void *HAL_ControllerAddress(unsigned flags, unsigned controller)
Maps to RISC OS' OS_Memory 9 call - provides a way for people who must poke the
hardware to find it. Bits 0-7 of controller are the sequence number
(starting at zero), and bits 8-31 are the controller type. Currently allocated
types are:
0 = EASI card access speed control register (sequence no = card)
1 = EASI space (sequence no = card)
2 = VIDC1
3 = VIDC20
4 = IOMD
Matrix Keyboard
===============
Many devices provide a matrix keyboard interface. The following calls
provide access to it.
int HAL_MatrixColumns(void)
Returns the number of columns available via the matrix interface.
unsigned int HAL_MatrixScan(int column).
Returns a bitfield describing which rows are active on the specified column.
Pass in column=-1 to deassert the column selects.
Docs/HAL/OS_Hardware 0 → 100644
View file @ 2abb437b
SWI OS_Hardware (SWI &7A)
-------------------------
On entry: R0-R7 parameters
R8 = reason code (bits 0-7) and flags (bits 8-31)
R9 = hardware call number
On exit: depends on flags
This SWI provides access to the hardware layer. Conceptually, it is
similar to accessing the hardware registers directly in earlier versions
of RISC OS - whereever possible OS routines should be used in preference.
This call is primarily designed for the use of device drivers - for example
the PS2Driver module makes PS2 hardware calls using this interface.
Making hardware calls to devices normally managed by the Kernel is liable to
cause the same problems as poking the hardware. However, making hardware
calls is of course preferable to actually accessing the hardware directly.
Use this interface with caution.
SWI OS_Hardware 0 (SWI &7A)
---------------------------
On entry: R0-R7 parameters for hardware routine
R8 = 0
R9 = hardware call number
On exit: R0-R3 updated by call
R4-R9 preserved.
This SWI calls a HAL routine. HAL routines internally are ATPCS, so R0-R3 are
passed in as a1-a4, and R4-R7 are pushed on to the stack. The a1-a4 on exit
from the routine are passed back in R0-R3.
If the HAL routine is not available, an error is returned. Actual HAL
routines do not return RISC OS errors - any possible failure will be
indicated in a call-specific manner.
SWI OS_Hardware 1 (SWI &7A)
---------------------------
On entry: R8 = 1
R9 = hardware call number
On exit: R0 = routine address
R1 = static base value for routine
This call looks up the address of a HAL routine. If it does not exist, an
error is returned. Otherwise, the address of the routine is returned in R0.
Calls made to the routine should be in a privileged mode, with R9 (sb) set to
the static base value returned by this SWI. Refer to the HAL documentation
for more details of calling conditions.
Makefile
View file @ 2abb437b
......@@ -64,13 +64,14 @@ EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.VduExt \
${EXP_HDR}.HALEntries \
${EXP_HDR}.OSEntries \
${C_EXP_HDR}.RISCOS
${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.HALEntries
#
# Generic rules:
#
.SUFFIXES: .o .s
.s.o:; ${ARMASM} ${ARMASMFLAGS} -o $@ $<
.s.o:; ${ARMASM} ${ARMASMFLAGS} -o $@ $< -list list.$*
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
......@@ -157,4 +158,8 @@ ${C_EXP_HDR}.RISCOS: hdr.RISCOS
${MKDIR} ${C_EXP_HDR}
perl Build:Hdr2H hdr.RISCOS $@
${C_EXP_HDR}.HALEntries: hdr.HALEntries
${MKDIR} ${C_EXP_HDR}
perl Build:Hdr2H hdr.HALEntries $@
# Dynamic dependencies:
hdr/HALEntries
View file @ 2abb437b
......@@ -71,7 +71,15 @@ EntryNo_HAL_Video_UpdatePointer # 1
EntryNo_HAL_Video_SetDAG # 1
EntryNo_HAL_Video_VetMode # 1
EntryNo_HAL_MatrixColumns # 1
EntryNo_HAL_MatrixScan # 1
EntryNo_HAL_MachineID # 1
EntryNo_HAL_ControllerAddress # 1
EntryNo_HAL_HardwareInfo # 1
EntryNo_HAL_SuperIOInfo # 1
; Various flags and constants
; NVMemory
......@@ -79,7 +87,7 @@ EntryNo_HAL_MachineID # 1
NVMemoryFlag_None * 0
NVMemoryFlag_MaybeIIC * 1
NVMemoryFlag_IIC * 2
NVMemoryFlag_HAL * 3
NVMemoryFlag_HAL * 4
NVMemoryFlag_Provision * 7 ; mask for provision
NVMemoryFlag_ProtectAtEnd * 1:SHL:8 ; Protected region at end
NVMemoryFlag_Deprotectable * 1:SHL:9
......
hdr/KernelWS
View file @ 2abb437b
......@@ -237,28 +237,42 @@ IRQStackSize * 8*1024
ABTStackSize * 8*1024
UNDStackSize * 8*1024
AplWorkMaxSize * &20000000 ; 512M - temporary (need to decide this at boot time)
SVCStackAddress * &01C00000
AplWorkMaxSize * &01F00000 ; 31M - temporary (need to decide this at boot time)
ScreenEndAdr * &24000000 ; temporary - run time allocate
FreePoolAddress * &28000000 ; ditto
RMAAddress * &80000000 ; temporary - run time allocate
RMAAddress * &02100000 ; temporary - run time allocate
ScreenMaxSize * 480*1024
RMAMaxSize * -1
RMAMaxSize * &00F00000 ; temporary - should be max
IO * &FA000000 ; works downwards
HALWorkspace * &FA000000
IRQStackAddress * &FA100000
[ {FALSE}
SVCStackAddress * &FA200000
]
ABTStackAddress * &FA300000
UNDStackAddress * &FA400000
PhysicalAccess * &FAE00000
[ {FALSE}
CursorChunkAddress * &FAFF0000
|
CursorChunkAddress * &01F00000
]
L2PT * &FB000000
L1PT * &FB400000
[ {FALSE}
SysHeapChunkAddress * &FB404000
SysHeapAddress * SysHeapChunkAddress
SysHeapMaxSize * &FB800000 - SysHeapAddress
|
SysHeapChunkAddress * &01C08000
SysHeapAddress * SysHeapChunkAddress
SysHeapMaxSize * &001F8000
]
CAM * &FB800000
IRQSTK * IRQStackAddress + IRQStackSize
......
hdr/PublicWS
View file @ 2abb437b
......@@ -79,9 +79,18 @@ VduDriverWorkSpace # &3000
ScratchSpace # &4000
[ HAL32
[ {FALSE}
SVCSTK * &FA208000
SysHeapStart * &FB404000
|
SVCSTK * &01C08000
SysHeapStart * &01C08000
]
[ {FALSE}
^ &FAFF33FC
|
^ &01F033FC
]
SvcTable # &400
BranchToSWIExit # 4
|
......
s/ARM600
View file @ 2abb437b
......@@ -2245,6 +2245,7 @@ timecpuriscpc
LDR r7, =(1 :SHL: 16) :OR: 16000 ; assumed 16MHz RAM (32 MHz bus)
MOV pc, lr
[ :LNOT: HAL
;used by NewReset, after main kernel boot
;sets full 64MHz memory if on 7500FE
;preserves registers _and_ flags
......@@ -2264,6 +2265,7 @@ finalmemoryspeed ROUT
STREQB r0, [lr, #IOMD_CLKCTL]
fmspeed_done
EXITS ; ***KJB - flag preservation necessary?
]
| ; else if not RO371Timings
......
s/ChangeDyn
View file @ 2abb437b
......@@ -2664,8 +2664,8 @@ DoTheGrowPagesSpecified
|
LDR r6, [r8, #8] ; r6 = physical address of src for copy
ORR r6, r6, #PhysSpace ; must use physical address, as page may be mapped to 01F08000 along with others
ADD lr, r6, r5 ; lr = end src address
]
ADD lr, r6, r5 ; lr = end src address
72
LDMIA r6!, {r2, r3, r4, r7, r9, r10, r11, r12}
STMIA r0!, {r2, r3, r4, r7, r9, r10, r11, r12}
......
s/Copro15ops
View file @ 2abb437b
......@@ -144,9 +144,9 @@ C15 CN 15
;ARM 920 onwards use op2 0 and 1 - behaviour with other op2 values is as yet
;unknown...
MACRO
ARM_on_emulator $tmp
MRC ARM_config_cp,0,$tmp,ARM_ID_reg,C0,7
TEQ $tmp,#1
ARM_on_emulator $tmp,$cond
MRC$cond ARM_config_cp,0,$tmp,ARM_ID_reg,C0,7
TEQ$cond $tmp,#1
MEND
;flush whole TLB (both data and instruction for StrongARM)
......
s/GetAll
View file @ 2abb437b
......@@ -514,7 +514,7 @@ USR2632 * USR26_mode
SVC2632 * SVC26_mode
]
MaxSwi * OS_NVMemory+1
MaxSwi * OS_Hardware+1
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -658,6 +658,8 @@ StartOfAMB
GET s.AMBControl.AMB
EndOfAMB
ALIGN 65536
EndOfKernel
& 0 ; for patching by BigSplit et al
......
s/HAL
View file @ 2abb437b
......@@ -1120,6 +1120,9 @@ AllocateL2PT
STR a3, [v6, v8, LSL #2] ; fill in the L1PT
TEQ v3, #0 ; MMU off?
[ EmulatorSupport
ARM_on_emulator a1,NE ; and not on the emulator?
]
MOVNE a1, v4 ; if so, zero out the L2PT
MOVNE a2, #0 ; (if it's on then it will already
MOVNE a3, #4*1024 ; be clear from ClearPhysRAM, and
......@@ -1384,8 +1387,8 @@ HAL_Write0
ClearPhysRAM ROUT
[ EmulatorSupport
; ARM_on_emulator r0
; BEQ CPR_skipped
ARM_on_emulator r0
BEQ CPR_skipped
]
;now let us do the clear
......@@ -1596,10 +1599,77 @@ SetUpHALEntryTable ROUT
MOV a2, a4 ; a2 -> entry table (increments)
10 LDR a1, [a2], #4
SUBS ip, ip, #1 ; decrement counter
ADD a1, a4, a1 ; convert offset to absolute
TEQ a1, #0
ADREQ a1, NullHALEntry
ADDNE a1, a4, a1 ; convert offset to absolute
STR a1, [a3, #-4]! ; store backwards below HAL workspace
BHI %BT10
MOV pc, lr
NullHALEntry
MOV pc, lr
; Can freely corrupt r10-r12 (v7,v8,ip).
HardwareSWI
AND ip, v5, #&FF
CMP ip, #1
BHI HardwareBadReason
BEQ HardwareLookup
HardwareCall
Push "v1-v4,sb,lr"
ADD v8, sb, #1 ; v8 = entry no + 1
MOV ip, #0
LDR v7, [ip, #HAL_Descriptor]
AddressHAL ip ; sb set up
LDR v7, [v7, #HALDesc_Entries] ; v7 = number of entries
CMP v8, v7 ; entryno + 1 must be <= number of entries
BHI HardwareBadEntry
LDR ip, [sb, -v8, LSL #2]
ADR v7, NullHALEntry
TEQ ip, v7
BEQ HardwareBadEntry
MOV lr, pc
MOV pc, ip
ADD sp, sp, #4*4
Pull "sb,lr"
ExitSWIHandler
HardwareLookup
ADD v8, sb, #1 ; v8 = entry no + 1
MOV ip, #0
LDR v7, [ip, #HAL_Descriptor]
AddressHAL ip
LDR v7, [v7, #HALDesc_Entries]
CMP v8, v7 ; entryno + 1 must be <= number of entries
BHI HardwareBadEntry
LDR a1, [sb, -v8, LSL #2]
ADR v7, NullHALEntry
TEQ a1, v7
BEQ HardwareBadEntry
MOV a2, sb
ExitSWIHandler
HardwareBadReason
ADR r0, ErrorBlock_HardwareBadReason
[ International
Push "lr"
BL TranslateError
Pull "lr"
]
B SLVK_SetV
HardwareBadEntry
ADR r0, ErrorBlock_HardwareBadEntry
[ International
Push "lr"
BL TranslateError
Pull "lr"
]
B SLVK_SetV
MakeErrorBlock HardwareBadReason
MakeErrorBlock HardwareBadEntry
END
s/Kernel
View file @ 2abb437b
......@@ -229,9 +229,13 @@ v8 RN 11
; Set sb up ready for CallHAL.
MACRO
AddressHAL
AddressHAL $zero
[ "$zero" <> ""
LDR sb, [$zero, #HAL_Workspace]
|
LDR sb, =ZeroPage
LDR sb, [sb, #HAL_Workspace]
]
MEND
; Calls the HAL. $rout is the routine. sb must have been set up by AddressHAL
......@@ -251,7 +255,7 @@ MinAplWork * 40*1024 ; minimum size of AplWork
; Fixed addresses
MEMCADR * &3600000
[ HAL32
[ HAL32 :LAND: {FALSE}
ROM * &FC000000
|
ROM * &3800000
......@@ -331,7 +335,7 @@ DoTestThings SETS ""
RISCOS_Header
= "OSIm"
DCD 0
DCD 1*1024*1024 - 64*1024
DCD OSROM_ImageSize*1024 - 64*1024
DCD RISCOS_Entries - RISCOS_Header
DCD (RISCOS_Entries_End - RISCOS_Entries) / 4
......@@ -739,6 +743,10 @@ JTABLE & SWIWriteC ; this entry never gets used (see ^)
& NoSuchSWI
]
& NVMemorySWI
& NoSuchSWI
& NoSuchSWI
& NoSuchSWI
& HardwareSWI
ASSERT (.-JTABLE)/4 = MaxSwi
......
s/MemInfo
View file @ 2abb437b
......@@ -583,6 +583,15 @@ MemoryAmounts ROUT
;
; Return the location of the specified controller.
;
[ HAL
MemoryIOSpace ROUT
Entry "r0,r2,r3,sb,ip"
AddressHAL
CallHAL HAL_ControllerAddress
MOV r1, r0
EXIT
|
MemoryIOSpace ROUT
Entry "r2"
......@@ -609,14 +618,7 @@ MemoryIOSpace ROUT
SETV
EXIT
[ HAL
! 0, "Sort out OS_Memory 9"
]
controller_types
[ HAL
DCD 0,0,0,0
|
[ IO_Type = "IOMD"
DCD IOMD_Base + IOMD_ECTCR ; Expansion card timing control.
DCD easi_space_table - controller_types
......@@ -644,6 +646,6 @@ easi_space_table
DCD PhysSpace + IOMD_EASI_Base6
DCD PhysSpace + IOMD_EASI_Base7
]
]
] ; HAL
END
s/Middle
View file @ 2abb437b
......@@ -1286,6 +1286,22 @@ IOST_LC * 16
IOST_7500 * 32 ;Running on ARM7500 (Morris) so actually IOMDL and VIDC2L
IOST_BATMAN * 64 ;Stork keyboard/battery controller seems to be present
]
[ HAL
20
Push "r9,r14"
AddressHAL
SUB sp, sp, #12
ADD a1, sp, #0
ADD a2, sp, #4
ADD a3, sp, #8
CallHAL HAL_HardwareInfo
MOV r12, #0
LDR r3, [r12, #RawMachineID+0]
LDR r4, [r12, #RawMachineID+4]
Pull "r0-r2,r9,r14"
ExitSWIHandler
|
20
MOV r0, #0
LDR r3, [r0, #RawMachineID+0]
......@@ -1331,6 +1347,7 @@ IOST_BATMAN * 64 ;Stork keyboard/battery controller seems to be present
]
]
ExitSWIHandler
]
; ReadSysInfo(3)
;
......@@ -1358,6 +1375,16 @@ IOST_BATMAN * 64 ;Stork keyboard/battery controller seems to be present
;
30
[ HAL
Push "r9,r14"
AddressHAL
SUB sp, sp, #8
ADD a1, sp, #0
ADD a2, sp, #4
CallHAL HAL_SuperIOInfo
Pull "a1,a2,r9,r14"
ExitSWIHandler
|
MOV r0, #0 ; used as index and as default value
LDRB r1, [r0, #IOSystemType]
ANDS r1, r1, #IOST_COMBOMASK
......@@ -1381,6 +1408,7 @@ IOST_BATMAN * 64 ;Stork keyboard/battery controller seems to be present
MOV r3, #0
MOV r4, #0
ExitSWIHandler
]
; OS_ReadSysInfo 4 (SWI &58)
;
......
s/NewIRQs
View file @ 2abb437b
......@@ -1134,6 +1134,12 @@ NOIRQ ROUT
MOV r10, #VIDC
STR r14, [r10]
]
[ HAL
MOV r11, r9
AddressHAL
CallHAL HAL_IRQDisable
MOV r9, r11
|
01 SUBS r0, r0, #3
ADDGE r12, r12, #1
BGT %BT01 ; r12 := r0 DIV 3
......@@ -1176,6 +1182,7 @@ NOIRQ ROUT
MSR CPSR_c, lr ; absolute minimum FIQ disable period
STRB r1, [r0, #IOCIRQCLRA-IOCIRQMSKA] ; Clear IRQ
]
Pull pc ; claim vector
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -1247,10 +1254,10 @@ TickOne ROUT
Push r14
[ HAL
MOV r11, r9
Push "r9,r12"
AddressHAL
CallHAL HAL_IRQClear
MOV r9, r11
Pull "r9,r12"
|
MOV R0, #timer0_bit
STRB R0, [R3, #IOCIRQCLRA] ; clear timer 0 interrupt
......@@ -1337,10 +1344,10 @@ VsyncIRQ ROUT
Push r14
[ HAL
MOV r11, r9
Push "r9,r12"
AddressHAL
CallHAL HAL_IRQClear
MOV r9, r11
Pull "r9,r12"
|
MOV R0, #vsync_bit
STRB R0, [R3, #IOCIRQCLRA] ; Clear the vsync interrupt
......
s/NewReset
View file @ 2abb437b
......@@ -809,7 +809,7 @@ checkboot
MOV R0, #InitHALFlags
LDR R1, [R0]
TST R1, #OSStartFlag_NoCMOS ; If no CMOS, reset for sensible cache
BEQ cmos_reset
BNE cmos_reset
TST R1, #OSStartFlag_POR
BEQ no_cmos_reset
TST R1, #OSStartFlag_NoCMOSReset
......@@ -1871,7 +1871,7 @@ furtherpoke_notSA
SWI XOS_NewLine
]
SWI XOS_EnterOS ; switch back to SVC mode (IRQs, FIQs enabled)
[ RO371Timings
[ :LNOT: HAL :LAND: RO371Timings
BL finalmemoryspeed
]
; end of added code
......@@ -2073,21 +2073,21 @@ MonitorKeypadTable ; internal key number, CMOS bits
|
processor_names
[ International
= "600", 0
= "600:ARM 600 Processor", 0
ALIGN 8
= "610", 0
= "610:ARM 610 Processor", 0
ALIGN 8
= "700", 0
= "700:ARM 700 Processor", 0
ALIGN 8
= "710", 0
= "710:ARM 710 Processor", 0
ALIGN 8
= "810", 0
= "810:ARM 810 Processor", 0
ALIGN 8
= "SA110", 0
= "SA110:StrongARM Processor", 0
ALIGN 8
= "7500", 0
= "7500:ARM 7500 Processor", 0
ALIGN 8
= "7500FE", 0
= "7500FE:ARM 7500FE Processor", 0
ALIGN 8
|
DCB "ARM 600 Processor",10,13,10,0
......
s/PMF/i2cutils
View file @ 2abb437b
......@@ -1722,7 +1722,7 @@ InitCMOSCache Entry "r1-r6, sb"
AddressHAL
CallHAL HAL_NVMemoryType
ANDS R0, R0, #NVMemoryFlag_Provision
EXIT EQ
BEQ InitCMOSCache_NoCMOS
MOV R5, R0
; If it's only a maybe, then we probe
......@@ -1846,7 +1846,13 @@ InitCMOSCache Entry "r1-r6, sb"
BVC %FT5
; We ain't got anything!
STRB R5, [R2, #NVRamPageSize]
InitCMOSCache_NoCMOS
LDR R2, =ZeroPage
MOV R5, #8
STRB R5, [R2, #NVRamPageSize] ; Act as though we have 256 bytes of
MOV R1, #1 ; single page CMOS.
STRB R1, [R2, #NVRamSize]
STRB R1, [R2, #NVRamWriteSize]
MOV R0, #0 ; Exit failure
EXIT
......
s/SWINaming
View file @ 2abb437b
......@@ -199,6 +199,10 @@ System_Swi_Names
AddSwiNameToDecodeTab EnterUSR26
AddSwiNameToDecodeTab VIDCDivider
AddSwiNameToDecodeTab NVMemory
AddSwiNameToDecodeTab ClaimOSSWI
AddSwiNameToDecodeTab TaskControl
AddSwiNameToDecodeTab DeviceDriver
AddSwiNameToDecodeTab Hardware
= 0
[ SwisInSystemTable+1 <> MaxSwi
......
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