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Commit 2c1c85d9 authored by Kevin Bracey's avatar Kevin Bracey
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Support for keys held down in the HAL at power on. 

*Configure ANYTHINGsize was broken due to not setting R0 to ReadUnsigned
IIC ack message uninternationalised
OS_Memory was saying we only had 4M of RAM
VDU4 scrolling when output was switched to sprite was causing corruption
on use of CTRL-J and CTRL-K
Default SystemSize CMOS set to 32k

Version 5.35, 4.79.2.55. Tagged as 'Kernel-5_35-4_79_2_55'
parent bc961962
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Showing with 297 additions and 198 deletions
Docs/GraphicsV
View file @ 2c1c85d9
......@@ -58,20 +58,20 @@ out:
Write palette entry
R4 = 10
R0 = type (0 = normal entry, 1 = border, 2 = palette)
R0 = type (0 = normal entry, 1 = border, 2 = pointer)
R1 = palette entry (&BBGGRRSS)
R2 = palette index
Write palette entries
R4 = 11
R0 = type (0 = normal entry, 1 = border, 2 = palette)
R0 = type (0 = normal entry, 1 = border, 2 = pointer)
R1 -> palette entry table
R2 = first palette index
R3 = number of entries
Read palette entry
R4 = 12
R0 = type (0 = normal entry, 1 = border, 2 = palette)
R0 = type (0 = normal entry, 1 = border, 2 = pointer)
R1 = palette entry (&BBGGRRSS)
R2 = palette index
Out:
......
Docs/HAL/Entries
View file @ 2c1c85d9
......@@ -136,7 +136,9 @@ example on ARM7500 16->32 bit switch code is required, and on the 9500 parts
a special ROM header and checksum must be present. Instead of a header,
a pointer to the HAL descriptor is passed to the OS in the OS_Start call:
Word 0: Flags (0)
Word 0: Flags
bit 0 => uncachable workspace (32K) required
bits 1-31 reserved
Word 1: Offset from descriptor to start of HAL (will be <= 0)
Word 2: HAL size
Word 3: Offset from descriptor to entry table
......
Docs/HAL/HAL_API
View file @ 2c1c85d9
......@@ -155,7 +155,9 @@ For example on ARM7500 16->32 bit switch code is required, and on the
descriptor block, instead of a header, can be placed somewhere in the HAL. A
pointer to this block is passed by the HAL to the OS in the OS_Start call:
Word 0: Flags (currently should be 0)
Word 0: Flags
bit 0 => uncachable workspace (32K) required
bits 1-31 reserved
Word 1: Offset (bytes) from descriptor to start of HAL (will be <= 0)
Word 2: HAL size (bytes)
Word 3: Offset (bytes) from descriptor to table of HAL routine entry points
......@@ -424,7 +426,7 @@ Routines in detail
routines listed in relevant sections with overview. eg. video routines
with video section, etc.]
-- HAL_Init(unsigned int *riscos_header)
-- HAL_Init(unsigned int *riscos_header, void *uncacheable_ws)
The OS will call HAL_Init after enabling the MMU, and initialising the HAL
workspace (filled with 0). At this point any initialisation for the main HAL
......
Version
View file @ 2c1c85d9
......@@ -14,9 +14,9 @@ Version SETA Module_Version
VString SETS Module_MajorVersion
Date SETS Module_Date ; version for STB/NC OS
|
Version SETA 501
VString SETS "5.01"
Date SETS "18 Dec 2002" ; version for RISC OS on desktop computers
Version SETA 502
VString SETS "5.02"
Date SETS "24 Jan 2003" ; version for RISC OS on desktop computers
]
END
VersionASM
View file @ 2c1c85d9
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.54"
Module_Date SETS "22 Jan 2003"
Module_ApplicationDate SETS "22-Jan-03"
Module_MinorVersion SETS "4.79.2.55"
Module_Date SETS "27 Jan 2003"
Module_ApplicationDate SETS "27-Jan-03"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.54)"
Module_HelpVersion SETS "5.35 (22 Jan 2003) 4.79.2.54"
Module_FullVersion SETS "5.35 (4.79.2.55)"
Module_HelpVersion SETS "5.35 (27 Jan 2003) 4.79.2.55"
END
VersionNum
View file @ 2c1c85d9
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.54
#define Module_Date_CMHG 22 Jan 2003
#define Module_MinorVersion_CMHG 4.79.2.55
#define Module_Date_CMHG 27 Jan 2003
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.54"
#define Module_Date "22 Jan 2003"
#define Module_MinorVersion "4.79.2.55"
#define Module_Date "27 Jan 2003"
#define Module_ApplicationDate "22-Jan-03"
#define Module_ApplicationDate "27-Jan-03"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.54)"
#define Module_HelpVersion "5.35 (22 Jan 2003) 4.79.2.54"
#define Module_FullVersion "5.35 (4.79.2.55)"
#define Module_HelpVersion "5.35 (27 Jan 2003) 4.79.2.55"
#define Module_LibraryVersionInfo "5:35"
hdr/HALEntries
View file @ 2c1c85d9
......@@ -23,6 +23,8 @@ HALDesc_NumEntries # 4
HALDesc_Workspace # 4
HALDesc_size # 4
HALFlag_NCNBWorkspace * 1:SHL:0
; Entries to the HAL from the OS
^ 0
......@@ -142,6 +144,11 @@ EntryNo_HAL_ATACableID # 1
EntryNo_HAL_InitDevices # 1
EntryNo_HAL_KbdScanSetup # 1
EntryNo_HAL_KbdScan # 1
EntryNo_HAL_KbdScanFinish # 1
EntryNo_HAL_KbdScanInterrupt # 1
; Various flags and constants
; NVMemory
......
hdr/KernelWS
View file @ 2c1c85d9
......@@ -266,6 +266,7 @@ UNDStackAddress * &FA400000
PhysicalAccess * &FAE00000
DCacheCleanAddress * &FAF00000 ; eg. for StrongARM, 256k of space, up to FAF40000
KbuffsBaseAddress * &FAF40000 ; kernel buffers for long command lines, size KbuffsMaxSize
HALWorkspaceNCNB * &FAFE8000 ; 32K of uncacheable HAL workspace (if requested)
[ {TRUE}
CursorChunkAddress * &FAFF0000
|
......
hdr/OSEntries
View file @ 2c1c85d9
......@@ -20,6 +20,7 @@ OS_AddRAM # 1
OS_Start # 1
OS_MapInIO # 1
OS_AddDevice # 1
OS_LogToPhys # 1
HighestOSEntry * :INDEX: @ - 1
......
hdr/Options
View file @ 2c1c85d9
......@@ -419,11 +419,13 @@ GetKbdDrA1 SETS ""
]
GBLS GetKbdRes
[ :LNOT: HAL
[ Keyboard_Type = "A1A500"
GetKbdRes SETS "GET s.KbdResA1"
|
GetKbdRes SETS "GET s.KbdRes" :CC: Keyboard_Type
]
]
; control switches for med_00001 (the flood fill routines 1024 line limit).
; Switches have the following effects:
......
s/Arthur3
View file @ 2c1c85d9
......@@ -1475,6 +1475,7 @@ ReadNumParm Entry "r1"
CMP r2, #" "
BEQ %BT10
SUB r1, r0, #1
MOV r0, #10 ; set base
SWI XOS_ReadUnsigned
EXIT VS
MOV r0, r1
......@@ -1500,6 +1501,7 @@ ReadNumAuto Entry "r1,r3,r4"
; r3 corrupted in both cases
MOVEQ r2, #-1
BEQ %FT20
MOV r0, #10 ; set base
SWI XOS_ReadUnsigned
EXIT VS
20
......@@ -1521,6 +1523,7 @@ ReadSizeParm ROUT
CMP r2, #" "
BEQ %BT02
SUB r1, r0, #1
MOV r0, #10 ; set base
SWI XOS_ReadUnsigned
Pull "r1, r8", VS
BVS BadConParm
......@@ -2049,6 +2052,7 @@ Config_TV_setcode ROUT
CMP r2, #" "
BEQ Config_TV_setcode
SUB r1, r0, #1
MOV r0, #10 ; set base
SWI XOS_ReadUnsigned
BVS %FT01
CMP r2, #3
......@@ -2112,6 +2116,7 @@ Config_Ignore_setcode ROUT
CMP r2, #" "
BEQ Config_Ignore_setcode
SUB r1, r0, #1
MOV r0, #10 ; set base
SWI XOS_ReadUnsigned
MOV r0, r1
Push "r2"
......@@ -2303,6 +2308,7 @@ Config_MouseStep_setcode ROUT
CMP r2, #"-"
Push "r2"
SUBNE r1, r0, #1
MOV r0, #10 ; set base
SWI XOS_ReadUnsigned
Pull "r0"
BVS BadConParm
......@@ -2341,6 +2347,7 @@ Config_MouseType_setcode ROUT
CMP r2, #" "
BEQ Config_MouseType_setcode
SUB r1, r0, #1
MOV r0, #10 ; set base
SWI XOS_ReadUnsigned
BVS BadConParm
CMP r2, #&100
......
s/HAL
View file @ 2c1c85d9
......@@ -450,6 +450,14 @@ RISCOS_Start
STR ip, [a4, #HAL_Workspace] ; after our table of entries
BL Init_MapInRAM
LDR a3, [sp, #8] ; recover pushed HAL header
LDR lr, [a3, #HALDesc_Flags]
TST lr, #HALFlag_NCNBWorkspace ; do they want uncacheable
LDRNE a1, =HALWorkspaceNCNB ; workspace?
LDRNE a2, =(AP_None * L2X_APMult)
LDRNE a3, =32*1024
BLNE Init_MapInRAM
; Bootstrap time. We want to get the MMU on ASAP. We also don't want to have to
; clear up too much mess later. So what we'll do is map in the three fixed areas
; (L1PT, scratch space and page zero), the CAM, ourselves, and the HAL,
......@@ -566,7 +574,7 @@ RISCOS_Start
; Set up a reset IRQ handler (used during RAM clear for keyboard
; scan, and later for IIC CMOS access)
MSR CPSR_c, #IRQ32_mode + I32_bit + F32_bit
LDR sp_irq, =IRQSTK
LDR sp_irq, =ScratchSpace + ScratchSpaceSize/2
MSR CPSR_c, #SVC32_mode + I32_bit + F32_bit
LDR a2, =Reset_IRQ_Handler
STR a2, [a1, #InitIRQHandler]
......@@ -757,6 +765,7 @@ MMUon_nol1ptoverlap
STR v2, [a1, #InitUsedEnd]
LDR a1, =RISCOS_Header
LDR a2, =HALWorkspaceNCNB
AddressHAL
CallHAL HAL_Init
......@@ -776,6 +785,14 @@ MMUon_nol1ptoverlap
MOV a1, #0
CallHAL HAL_TimerSetPeriod
MOV a1, #InitIRQWs
MOV a2, #1
STRB a2, [a1, #KbdScanActive]
CallHAL HAL_KbdScanSetup
MSR CPSR_c, #F32_bit+SVC32_mode ; enable IRQs for scan
; Remember some stuff that's about to get zapped
LDR v8, =ZeroPage
LDR v5, [v8, #RAMLIMIT]
......@@ -917,11 +934,13 @@ MMUon_nol1ptoverlap
BL CountPageTablePages
[ {FALSE}
MOV a1, #InitIRQWs
MOV a2, #0
MOV a3, #0
STMIA a1!, {a2,a3}
STMIA a1!, {a2,a3}
]
B Continue_after_HALInit
......@@ -967,22 +986,6 @@ PhysAddrToPageNo
90 MOV a1, #-1
MOV pc, lr
LogToPhys
Push "lr"
LDR ip, =L1PT
MOV lr, a1, LSR #20
LDR lr, [ip, lr, LSL #2]
TST lr, #1
BEQ %FT80
LDR ip, =L2PT
MOV lr, a1, LSR #12
LDR lr, [ip, lr, LSL #2]
TST lr, #1
MOV lr, lr, LSR #12
MOV lr, lr, LSL #12
80
; A routine to construct the soft CAM from the page tables. This is used
; after a soft reset, and also on a hard reset as it's an easy way of
......@@ -1524,7 +1527,7 @@ HAL_Write0
;
ClearPhysRAM ROUT
MSR CPSR_c, #F32_bit+I32_bit+FIQ32_mode ; get some extra registers
MSR CPSR_c, #F32_bit+FIQ32_mode ; get some extra registers
MOV r8, #0
MOV r9, #0
MOV r10, #0
......@@ -1532,7 +1535,7 @@ ClearPhysRAM ROUT
MOV r12, #0
MOV r13, #0
MOV r14, #0
MSR CPSR_c, #F32_bit+I32_bit+SVC32_mode
MSR CPSR_c, #F32_bit+SVC32_mode
[ EmulatorSupport
ARM_on_emulator r0
......@@ -1597,7 +1600,7 @@ ClearPhysRAM ROUT
MOVNE r1, r2, LSL #20 ; then stop at end of megabyte
ADDNE r1, r1, #&00100000
MSR CPSR_c, #F32_bit+I32_bit+FIQ32_mode ; switch to our bank o'zeros
MSR CPSR_c, #F32_bit+FIQ32_mode ; switch to our bank o'zeros
MOV r2, #0
19 ADD r5, r5, r0
......@@ -1615,7 +1618,7 @@ ClearPhysRAM ROUT
LDR r5, [r6], #4 ; load next skip offset (NB relative to end of last skip)
B %BT19
30 MSR CPSR_c, #F32_bit+I32_bit+SVC32_mode ; back to supervisor mode
30 MSR CPSR_c, #F32_bit+SVC32_mode ; back to supervisor mode
MOV r10, r0
MOV r11, r1
LDMIA r7, {r0, r1}
......@@ -1839,6 +1842,16 @@ RISCOS_AddDevice
ADDS a1, a2, #0 ; also clears V
B HardwareDeviceAdd_Common
; uint32_t RISCOS_LogToPhys(const void *log)
RISCOS_LogToPhys
Push "r4,r5,r8,r9,lr"
MOV r4, a1
LDR r8, =L2PT
BL logical_to_physical
MOVCC a1, r5
MOVCS a1, #-1
Pull "r4,r5,r8,r9,pc"
SetUpHALEntryTable ROUT
LDR a1, =ZeroPage
......@@ -2124,6 +2137,10 @@ Reset_IRQ_Handler
TST a2, #IICFlag_Background
MOVNE ip, sb
BLNE IICIRQ
MOV a1, #InitIRQWs
LDRB a1, [a1, #KbdScanActive]
TEQ a1, #0
CallHAL HAL_KbdScanInterrupt,NE
Pull "lr"
MSR SPSR_cxsf, lr
Pull "a1-a4,sb,ip,pc",,^
......
s/Kernel
View file @ 2c1c85d9
......@@ -364,6 +364,7 @@ RISCOS_Entries
DCD RISCOS_Start - RISCOS_Entries
DCD RISCOS_MapInIO - RISCOS_Entries
DCD RISCOS_AddDevice - RISCOS_Entries
DCD RISCOS_LogToPhys - RISCOS_Entries
RISCOS_Entries_End
|
......
s/MemInfo
View file @ 2c1c85d9
......@@ -602,14 +602,13 @@ MemoryAmounts ROUT
BEQ %FT30 ; Don't understand 0 (so the spec says).
TEQ lr, #5:SHL:8 ; Check for soft ROM
MOV r1, #OSROM_ImageSize*1024 ; this much soft ROM
B %FT20
MOVEQ r1, #OSROM_ImageSize*1024 ; this much soft ROM
BEQ %FT20
05 TEQ lr, #1:SHL:8
BNE %FT10
MOV r1, #0
LDR r1, [r1, #RAMLIMIT] ; assume 0 VRAM
B %FT20
MOVEQ r1, #0
LDREQ r1, [r1, #RAMLIMIT] ; assume 0 VRAM
BEQ %FT20
10
TEQ lr, #2:SHL:8
BNE %FT40 ; not implementing anything else in this bodge
......@@ -998,6 +997,7 @@ ReleasePhysAddr
; 8=Level 2 page tables
; 9=HAL workspace
; 10=Kernel buffers
; 11=HAL uncacheable workspace
; 16-31 reserved (set to 0)
;
; Out: r1 = base of area
......@@ -1028,6 +1028,7 @@ MAI_TableStart
B MAI_L2PT
B MAI_HALWs
B MAI_Kbuffs
B MAI_HALWsNCNB
MAI_TableEnd
70
......@@ -1090,8 +1091,8 @@ MAI_L2PT
LDR r3, [r0, #L2PTUsed]
EXIT
[ HAL
MAI_HALWs
[ HAL
MOV r0, #ZeroPage
LDR r1, =HALWorkspace
MOV r2, #HALWorkspaceSpace
......@@ -1099,6 +1100,18 @@ MAI_HALWs
]
EXIT
MAI_HALWsNCNB
[ HAL
MOV r0, #ZeroPage
LDR r1, =HALWorkspaceNCNB
MOV r2, #32*1024
LDR r3, [r0, #HAL_Descriptor]
LDR r3, [r3, #HALDesc_Flags]
ANDS r3, r3, #HALFlag_NCNBWorkspace
MOVNE r3, r2
]
EXIT
MAI_Kbuffs
LDR r1, =KbuffsBaseAddress
MOV r2, #KbuffsMaxSize
......
s/Middle
View file @ 2c1c85d9
......@@ -155,10 +155,10 @@ VecRdLine ROUT
CMPCS R3, R0 ; and char <= max ?
ADDCS R6, R6, #1 ; if so, then inc pointer
BCS %FT80
TST R7, #&40000000 ; no reflection
TST R7, #&80000000 ; no reflection
BNE %BT10 ; of non-entered chars
80 TST R7, #&20000000
80 TST R7, #&40000000
ANDNE R0, R7, #&FF ; echo char -> R0
B %BT05 ; echo character
......
s/NewReset
View file @ 2c1c85d9
......@@ -37,6 +37,20 @@ CMOSLimit * &F0
; Keyboard flags
^ 1
[ HAL
KbdScanActive # 1
# 2
KbdFlags # 4
KbdFlag_Ctrl * 1:SHL:0
KbdFlag_Shift * 1:SHL:1
KbdFlag_R * 1:SHL:4
KbdFlag_T * 1:SHL:5
KbdFlag_Delete * 1:SHL:6
KbdFlag_Copy * 1:SHL:7
KbdFlag_Present * 1:SHL:30
KbdFlag_Done * 1:SHL:31
|
CTRL_Down_Flag # 1
SHIFT_Down_Flag # 1
KB_There_Flag # 1
......@@ -52,6 +66,7 @@ Port2Present # 1 ; note that these 4 form one word!!
Port3Present # 1
KeyState # 1
KeyMSB # 1
]
; On ARM600, InitIRQWs is in zero page - check it's big enough
......@@ -645,16 +660,40 @@ us * 2
]
[ HAL
! 0, "Sort out keyboard boot detection"
AddressHAL
MOV r6, #25 ; Check for keyboard 25 times (5 secs max).
MOV r4, #InitIRQWs
kbdwait
CallHAL HAL_KbdScan
STR r0, [r4, #KbdFlags]
TST r0, #KbdFlag_Done
BNE kbddone
[ EmulatorSupport
ARM_on_emulator r0
MOVEQ r0, #us
LDRNE r0, =KeyWait*us ; Wait 1/5 second (give keys down a chance to come in).
|
LDR r0, =KeyWait*us ; Wait 1/5 second (give keys down a chance to come in).
]
CallHAL HAL_CounterDelay
SUBS r6, r6, #1 ; else wait a maximum of 5 seconds.
BNE kbdwait
kbddone
MSR CPSR_c, #I32_bit+SVC32_mode
CallHAL HAL_KbdScanFinish
MOV r1, #InitIRQWs
MOV r0, #0
STRB r0, [r1, #KbdScanActive]
MSR CPSR_c, #SVC32_mode
|
[ KeyWait <> 0
; Check for keyboard there every 1/5 sec. but give up after 2 secs.
MOV r2, #IOC
MOV r6, #10 ; Check for keyboard 10 times (2 secs max).
MOV r4, #InitKbdWs
[ HAL
AddressHAL
]
kbdwait
LDRB r5, [r4, #KB_There_Flag]
[ EmulatorSupport
......@@ -664,11 +703,7 @@ kbdwait
|
LDR r0, =KeyWait*us ; Wait 1/5 second (give keys down a chance to come in).
]
[ HAL
CallHAL HAL_CounterDelay
|
BL DoMicroDelay
]
TEQ r5, #0 ; If keyboard was there 1/5 second ago then
BNE kbdthere ; continue reset
SUBS r6, r6, #1 ; else wait a maximum of 2 seconds.
......@@ -700,16 +735,6 @@ reset_loop
TEQ R1, #SpriteSizeCMOS
BHI reset_loop
[ {FALSE}
; FontCMOS should be <= 32 (128K)
; What on earth was this about? Why would anyone require FontSize to
; be less than 128K?
MOV R0, #FontCMOS
BL Read
CMP R0, #32
BHI cmos_reset
]
[ {FALSE}
; Oh, just leave it be
MOV R0, #VduCMOS
......@@ -805,8 +830,13 @@ checkboot
] ; HAL
MOV R0, #InitIRQWs
[ HAL
LDR R7, [R0, #KbdFlags]
TST R7, #KbdFlag_R:OR:KbdFlag_T:OR:KbdFlag_Delete:OR:KbdFlag_Copy
|
LDR R7, [R0, #R_Down_Flag]
CMP R7, #0
]
BEQ no_cmos_reset ; power on bit checked again there
[ :LNOT: STB
......@@ -907,10 +937,15 @@ not_full_reset
; IF R or Delete pressed THEN set sync 0 ELSE set sync Auto
MOV R0, #InitIRQWs
[ HAL
LDR R1, [R0, #KbdFlags]
TST R1, #KbdFlag_R:OR:KbdFlag_Delete
|
LDRB R1, [R0, #R_Down_Flag]
CMP R1, #0
LDREQB R1, [R0, #Del_Down_Flag]
CMPEQ R1, #0
]
MOV R0, #VduCMOS
MOVNE R1, #MonitorTypeAuto :OR: Sync_Auto ; if R or Del
MOVEQ R1, #MonitorTypeAuto :OR: Sync_Separate ; if T or Copy
......@@ -1020,11 +1055,12 @@ DefaultCMOSTable ; list of non-zero options wanted :
; terminated by offset &FF
= KeyDelCMOS, 32
= FileLangCMOS, 8
= FontCMOS, 16 ; TMD 15-Dec-93: Changed to 64K from 32K - fixes MED-01774
= FontCMOS, 64 ; KJB 13-Dec-02: Changed to 256K from 64K
= PigCMOS, 10
= KeyRepCMOS, 8
= RMASizeCMOS, 0
= SpriteSizeCMOS, 0
= SystemSizeCMOS, 8
= MODETVCMOS, &10 ; TV 0,1
= NetFSIDCMOS, 254
= NetPSIDCMOS, 235
......@@ -1099,9 +1135,10 @@ DefaultCMOSTable ; list of non-zero options wanted :
]
[ :LNOT: STB
= FontMaxCMOS, 64 ; 256k
= FontMax2CMOS, &28 ; 36 point
= FontMax3CMOS, &3C ; 36 point
= FontMaxCMOS, 64 ; 4096k
= FontMax2CMOS, 36:EOR:12 ; 36 point
= FontMax3CMOS, 36:EOR:24 ; 36 point
= FontMax4CMOS, 16 ; 16 point
|
; yes, omitting FontMaxCMOS is deliberate!
= FontMax2CMOS, &2C ; 32 point
......@@ -1109,7 +1146,7 @@ DefaultCMOSTable ; list of non-zero options wanted :
]
= AlarmAndTimeCMOS,2_00010000 ; !Alarm autosave on
= FSLockCMOS+5, &EA ; Checksum for no password
= CDROMFSCMOS, &60 ; drives = 0, buffer size = 32K
= CDROMFSCMOS, &C1 ; drives = 1, buffer size = 256K
]
= &FF
ALIGN
......@@ -1694,8 +1731,14 @@ ResetPart1Done ; R0 is reset type
STRB R0, [R1]
MOV R1, #InitIRQWs
[ HAL
LDR R0, [R1, #KbdFlags]
AND R1, R0, #KbdFlag_Shift
AND R0, R0, #KbdFlag_Present
|
LDRB R0, [R1, #KB_There_Flag]
LDRB R1, [R1, #SHIFT_Down_Flag]
]
Push "R0, R1" ; save until after MOSInit
BL InitialiseIRQ1Vtable
......@@ -1743,6 +1786,12 @@ ResetPart1Done ; R0 is reset type
LDR R1, RealIRQHandler
STR R1, [R0, #&18]
MOV R2, #InitIRQWs ; clear temp ws
MOV R3, #0
MOV R4, #0
STMIA R2!, {R3,R4}
STMIA R2!, {R3,R4}
;we need to do an IMB type thing for modifying code in vector area,
;and for copying irq handler code
;
......@@ -2131,10 +2180,8 @@ PT_lookup
Pull "R0" ; first check kbd there
[ :LNOT: HAL
CMP R0, #0
BEQ AutoBootCosNoKbd
]
MOV R0, #&FF
MOV R1, #0
......
s/PMF/IIC
View file @ 2c1c85d9
......@@ -16,8 +16,8 @@
; 05-Feb-02 BJGA Added re-entrant capability
PollMax * 150 ; Number of times to poll for an Ack (increase if you
; clock faster - need to allow 5ms for write cycle).
PollMax * 150 ; Number of times to poll for an Ack (increase if you
; clock faster - need to allow 5ms for write cycle).
; Choose a lower limit on the number of ticks per clock phase based on the
......@@ -275,7 +275,7 @@ IICDoOp ROUT
LDR iiclr, [R2, #IICType]
TST iiclr, #IICFlag_HighLevel
BNE IIC_OpV_HAL ; HAL can make use of a hardware IIC engine
BNE IIC_OpV_HAL ; HAL can make use of a hardware IIC engine
05 LDR R0, [iicsp]
SUBS R0, R0, #1
......@@ -369,8 +369,8 @@ IIC_ExitOK
80
iicBL Stop
IIC_ExitNoAck
MOV R0, #0
STR R0, [R0, #IICStatus]
MOV R0, #0
STR R0, [R0, #IICStatus]
ADR R0, ErrorBlock_IIC_NoAcknowledge
IIC_ExitError
......@@ -380,17 +380,23 @@ IIC_ExitError
; BJGA - we also can't use TranslateError, because it doesn't conform to
; our calling standard (unless we turn interrupts off)
BL TranslateError
ADD iicsp, iicsp, #8 ; skip junk on stack
iicPull "pc"
MakeInternatErrorBlock IIC_NoAcknowledge,, "NoAck:No acknowledge from IIC device"
|
SETV
]
ADD iicsp, iicsp, #8 ; skip junk on stack
iicPull "pc"
MakeInternatErrorBlock IIC_NoAcknowledge,, "NoAck:No acknowledge from IIC device"
MakeErrorBlock IIC_NoAcknowledge
]
; *****************************************************************************
;
; SetC1C0 - Set clock and data lines to values in R1 and R0 respectively
; SetC1C0 - Set clock and data lines to values in R1 and R0 respectively
;
; out: r0,r1 corrupted
;
......@@ -407,23 +413,23 @@ SetC1C0 ROUT
Pull "lr"
MSR CPSR_c, r7 ; IRQs back on
|
ADD R0, R0, R1, LSL #1 ; R0 := C0 + C1*2
MOV R2, #0 ; prepare to index soft copy
LDRB R1, [R2, #IOCControlSoftCopy] ; read soft copy
BIC R1, R1, #&03 ; clear clock and data
ORR R0, R1, R0 ; put in new clock and data
ORR R0, R0, #&C0 ; make sure two test bits are
; always set to 1 !
STRB R0, [R2, #IOCControlSoftCopy] ; store back to soft copy
MOV R2, #IOC
STRB R0, [R2, #IOCControl]
ADD R0, R0, R1, LSL #1 ; R0 := C0 + C1*2
MOV R2, #0 ; prepare to index soft copy
LDRB R1, [R2, #IOCControlSoftCopy] ; read soft copy
BIC R1, R1, #&03 ; clear clock and data
ORR R0, R1, R0 ; put in new clock and data
ORR R0, R0, #&C0 ; make sure two test bits are
; always set to 1 !
STRB R0, [R2, #IOCControlSoftCopy] ; store back to soft copy
MOV R2, #IOC
STRB R0, [R2, #IOCControl]
]
[ E2ROMSupport
MOV R0, #0
LDRB R0, [R0, #NVRamSpeed]
MOV R0, #0
LDRB R0, [R0, #NVRamSpeed]
TEQ R0, #0
MOVEQ R0, #10 ; default value if speed not checked yet
|
......@@ -435,9 +441,9 @@ SetC1C0 ROUT
; *****************************************************************************
;
; ReadC1C0 - Read clock and data lines to R1 and R0 respectively
; ReadC1C0 - Read clock and data lines to R1 and R0 respectively
;
; out: R0, R1 updated
; out: R0, R1 updated
;
ReadC1C0 ROUT
......@@ -461,10 +467,10 @@ ReadC1C0 ROUT
;
; iicDoMicroDelay - Delay for >= R0/2 microseconds, IIC calling standard
;
; in: R0 = time delay in 1/2 microsecond units
; On ARM600, we may or may not be in a 32-bit mode
; in: R0 = time delay in 1/2 microsecond units
; On ARM600, we may or may not be in a 32-bit mode
;
; out: R0,R1 corrupted
; out: R0,R1 corrupted
;
iicDoMicroDelay ROUT
......@@ -498,11 +504,11 @@ iicDoMicroDelay ROUT
; *****************************************************************************
;
; ClockData - Clock a bit of data down the IIC bus
; ClockData - Clock a bit of data down the IIC bus
;
; in: R0 = data bit
; in: R0 = data bit
;
; out: All registers preserved, including PSR
; out: All registers preserved, including PSR
;
ClockData ROUT
......@@ -514,7 +520,7 @@ ClockData ROUT
]
MOV R3, R0
MOV R1, #0 ; Clock lo
MOV R1, #0 ; Clock lo
iicBL SetC1C0
; Disable interrupts to ensure clock hi with data hi is only transient
......@@ -522,13 +528,13 @@ ClockData ROUT
MSR CPSR_c, r8
MOV R0, R3
MOV R1, #1 ; Clock hi
MOV R1, #1 ; Clock hi
iicBL SetC1C0
; Delay here must be >= 4.0 microsecs
MOV R0, R3
MOV R1, #0 ; Clock lo
MOV R1, #0 ; Clock lo
iicBL SetC1C0
[ No26bitCode
......@@ -540,78 +546,78 @@ ClockData ROUT
; *****************************************************************************
;
; Start - Send the Start signal
; Start - Send the Start signal
;
; out: All registers preserved, PSR corrupted
; out: All registers preserved, PSR corrupted
;
Start ROUT
Start ROUT
iicPush "R0-R1,iiclr"
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
iicBL SetC1C0
; Delay here must be >= 4.7 microsecs (1.3 for fast device)
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
iicBL SetC1C0
; Delay here must be >= 4.0 microsecs (0.6 for fast device)
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
iicBL SetC1C0
iicPull "R0-R1,PC"
; *****************************************************************************
;
; RepeatedStart - Send a Repeated Start signal
; RepeatedStart - Send a Repeated Start signal
;
; out: All registers preserved, PSR corrupted
; out: All registers preserved, PSR corrupted
;
RepeatedStart ROUT
RepeatedStart ROUT
iicPush "R0-R1,iiclr"
MOV R0, #1
MOV R1, #0 ; clock LO, data HI
iicBL SetC1C0
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
iicBL SetC1C0
; Delay here must be >= 4.7 microsecs (1.3 for fast device)
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
iicBL SetC1C0
; Delay here must be >= 4.0 microsecs (0.6 for fast device)
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
iicBL SetC1C0
iicPull "R0-R1,PC"
; *****************************************************************************
;
; Acknowledge - Check acknowledge after transmitting a byte
; Acknowledge - Check acknowledge after transmitting a byte
;
; out: All registers preserved
; V=0 => acknowledge received
; V=1 => no acknowledge received
; out: All registers preserved
; V=0 => acknowledge received
; V=1 => no acknowledge received
;
Acknowledge ROUT
iicPush "R0-R2,iiclr"
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
iicBL SetC1C0
[ {TRUE}
......@@ -620,8 +626,8 @@ Acknowledge ROUT
MSR CPSR_c, R8
]
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
iicBL SetC1C0
; Delay here must be >= 4.0 microsecs (0.6 for fast device)
......@@ -629,8 +635,8 @@ Acknowledge ROUT
iicBL ReadC1C0
MOV R2, R0 ; should be LO for correct acknowledge
MOV R0, #1
MOV R1, #0 ; clock LO, data HI
MOV R0, #1
MOV R1, #0 ; clock LO, data HI
iicBL SetC1C0
[ {TRUE}
......@@ -639,90 +645,90 @@ Acknowledge ROUT
TST R2, #1
MRS R2, CPSR
BICEQ R2, R2, #V_bit ; clear V if correct acknowledge
ORRNE R2, R2, #V_bit ; set V if no acknowledge
BICEQ R2, R2, #V_bit ; clear V if correct acknowledge
ORRNE R2, R2, #V_bit ; set V if no acknowledge
MSR CPSR_f, R2
iicPull "R0-R2,PC"
; *****************************************************************************
;
; Stop - Send the Stop signal
; Stop - Send the Stop signal
;
; out: All registers preserved, PSR corrupted
; out: All registers preserved, PSR corrupted
;
Stop ROUT
Stop ROUT
iicPush "R0-R1,iiclr"
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
iicBL SetC1C0
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
iicBL SetC1C0
; Delay here must be >= 4.0 microsecs (0.6 for fast device)
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
iicBL SetC1C0
iicPull "R0-R1,PC"
; *****************************************************************************
;
; TXByte - Transmit a byte
; TXByte - Transmit a byte
;
; in: R0 = byte to be transmitted
; in: R0 = byte to be transmitted
;
; out: All registers preserved, PSR corrupted
; out: All registers preserved, PSR corrupted
;
TXByte ROUT
TXByte ROUT
iicPush "R0-R2,iiclr"
MOV R1, #&80 ; 2^7 the bit mask
MOV R2, R0 ; byte goes into R2
MOV R1, #&80 ; 2^7 the bit mask
MOV R2, R0 ; byte goes into R2
10
ANDS R0, R2, R1 ; zero if bit is zero
MOVNE R0, #1
ANDS R0, R2, R1 ; zero if bit is zero
MOVNE R0, #1
iicBL ClockData ; send the bit
MOVS R1, R1, LSR #1
BNE %BT10
MOVS R1, R1, LSR #1
BNE %BT10
iicPull "R0-R2,PC"
TXAck ROUT
TXAck ROUT
iicPush iiclr
iicBL TXByte
iicPull iiclr
B Acknowledge
B Acknowledge
; *****************************************************************************
;
; TXPollAck - Transmit a byte and poll for acknowledge
; TXPollAck - Transmit a byte and poll for acknowledge
;
; This is intended for devices with a slow internal write cycle which
; don't ack until the write cycle is finished ( eg ATMEL AT24C01A/x )
; This is intended for devices with a slow internal write cycle which
; don't ack until the write cycle is finished ( eg ATMEL AT24C01A/x )
;
; in: R0 = byte to be transmitted
; in: R0 = byte to be transmitted
;
; out: All registers preserved
; out: All registers preserved
;
TXPollAck ROUT
TXPollAck ROUT
iicPush "R1,iiclr"
MOV R1, #1
MOV R1, #1
10
iicBL TXByte
iicBL Acknowledge
iicPull "R1,PC",VC
ADD R1, R1, #1
TEQ R1, #PollMax
TEQ R1, #PollMax
BEQ %FT90
[ {FALSE}
BREG R1, "i2c tries:"
[ {FALSE}
BREG R1, "i2c tries:"
]
iicBL RepeatedStart
B %BT10
......@@ -731,19 +737,19 @@ TXPollAck ROUT
; *****************************************************************************
;
; RXByte - Receive a byte
; RXByte - Receive a byte
;
; out: R0 = byte received
; All other registers preserved, PSR corrupted
; out: R0 = byte received
; All other registers preserved, PSR corrupted
;
RXByte ROUT
RXByte ROUT
iicPush "R1-R3,iiclr"
MOV R3, #0 ; byte:=0
MOV R2, #7
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
iicBL SetC1C0
10
[ {TRUE}
......@@ -752,24 +758,24 @@ RXByte ROUT
MSR CPSR_c, R8
]
MOV R0, #1 ; pulse clock HI
MOV R1, #1
MOV R0, #1 ; pulse clock HI
MOV R1, #1
iicBL SetC1C0
iicBL ReadC1C0
ADD R3, R0, R3, LSL #1 ; byte:=byte*2+ SDA
MOV R0, #1 ; return clock LO
MOV R1, #0
MOV R0, #1 ; return clock LO
MOV R1, #0
iicBL SetC1C0
[ {TRUE}
MSR CPSR_c, R7
]
SUBS R2, R2, #1
BCS %BT10
BCS %BT10
MOV R0, R3 ; return the result in R0
MOV R0, R3 ; return the result in R0
iicPull "R1-R3,PC"
; *****************************************************************************
......@@ -781,19 +787,19 @@ IIC_OpV_HAL
; [iicsp, #4] unused on entry, used to hold number of retries remaining
; [iicsp, #8] = return address
LDR iiclr, [R2, #IICStatus]
LDR iiclr, [R2, #IICStatus]
TEQ iiclr, #0
BNE IIC_Busy
LDR iiclr, [R3]
TST iiclr, #1:SHL:29 ; retries reqd?
MOVNE iiclr, #PollMax
MOVEQ iiclr, #1 ; no,just try once
MOVEQ iiclr, #1 ; no,just try once
STR iiclr, [iicsp, #4]
IIC_OpV_HAL_Retry
MOV iiclr, #1
STR iiclr, [R2, #IICStatus]
MOV iiclr, #1
STR iiclr, [R2, #IICStatus]
iicPush "R3"
MOV R0, #0
......@@ -801,7 +807,7 @@ IIC_OpV_HAL_Retry
MOV R2, R3
MSR CPSR_c, R8 ; IRQs off for use of ATPCS
Push "lr"
CallHAL HAL_IICTransfer
CallHAL HAL_IICTransfer
Pull "lr"
MSR CPSR_c, R7 ; IRQs back on
iicPull "R3"
......@@ -834,8 +840,8 @@ IICBusy_Error
MakeErrorBlock IIC_Busy
IIC_Error
MOV R0, #0
STR R0, [R0, #IICStatus]
MOV R0, #0
STR R0, [R0, #IICStatus]
ADR R0,IICError_Error
B IIC_ExitError
......@@ -848,7 +854,7 @@ interrupt_protected_end
IICIRQ
Push "R9,R14"
MOV R9, R12
MOV R0, #0
MOV R0, #0
CallHAL HAL_IICMonitorTransfer
MOV R12, #0
STR R0, [R12, #IICStatus]
......
s/vdu/vduwrch
View file @ 2c1c85d9
......@@ -1619,6 +1619,7 @@ GetBoxInfo
LDR R7, [WsPtr, #ModeFlags]
MOV R6, R8, LSL #3 ; *8
TST R7, #Flag_GapMode ; if gap mode
ADDNE R6, R6, R8, LSL #1 ; (+*2) = *10
TST R7, #Flag_DoubleVertical ; if double mode
......@@ -2314,17 +2315,9 @@ PlainBit ROUT
LDR bpp, [WsPtr, #BytesPerChar]
MOV R1, #1
; *****Change made by DJS
; Original code was:
; MOV R1, R1, LSL bpp ; first form mask for leftmost pixel
; SUB R1, R1, #1 ; = (2^BytesPerChar)-1
RSB R1, R1, R1, LSL bpp ; first form mask for leftmost pixel
; = (2^BytesPerChar)-1
; *****End of change made by DJS
ADD R3, WsPtr, #RAMMaskTb
10
STR R1, [R3], #4 ; store mask
......
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