GitLab

Add OS_PlatformFeatures 0 flag to indicate that the "Unknown OS_PlatformFeatures reason codes always raise an error" bug has been fixed

Detail:
  hdr/OSMisc - Use bit 31 to indicate that the error reporting bug has been fixed
  s/ARMops - Make sure the flag is set when preparing ProcessorFlags (i.e. the OS_PlatformFeatures 0 flags)
Admin:
  Tested on Raspberry Pi


Version 5.35, 4.79.2.325. Tagged as 'Kernel-5_35-4_79_2_325'

Detail:
  s/ChangeDyn - When DynArea_PMP_PhysOp generates an error during the initial page list scan, make sure r12 is initialised to the (new) PMP size, as expected by PMPMemoryMoved.
  s/AMBControl/allocate, s/AMBControl/growshrink - Document some extra exit conditions for the AMB allocate & grow/shrink routines
Admin:
  Tested on BB-xM
  Fixes RAM disc PMP becoming corrupt when attempting to grow it (e.g. via *ChangeDynamicArea) by an amount larger than the amount of free memory in the system


Version 5.35, 4.79.2.324. Tagged as 'Kernel-5_35-4_79_2_324'

Version 5.35, 4.79.2.323. Tagged as 'Kernel-5_35-4_79_2_323'

Detail:
  s/CPUFeatures - Take account of the fact that single-core ARMv7+ chips implement MPIDR but aren't guaranteed to implement a useful WFE. So for ARMv7+, only report WFE as being available/useful if MPIDR indicates that virtualisation extensions are supported.
Admin:
  Tested on Raspberry Pi 1 & 3, BB-xM


Version 5.35, 4.79.2.322. Tagged as 'Kernel-5_35-4_79_2_322'

Detail:
  s/vdu/vdugrafh - Rewrite MergeSpriteAreas so that memory movement is now O(N) instead of O(N^2). Checking for duplicate sprites is still slow (O(N^2) search), but this resolves the main performance bottleneck with the code.
  s/vdu/vdugrafg - Add a variant of SpriteCtrlBlk which skips the call to GetName; this helps MergeSpriteAreas for the common case of a dest area with lots of sprites and a source area with a handful of sprites (SpriteCtrlBlk is now called on the source area once per dest sprite, previously was called on the dest area once per source sprite).
Admin:
  Tested on Raspberry Pi 1, merging Sovereign theme Sprites11 file with itself (2.2MB file, 358 sprites)
  Old code took 860cs, new code takes 18cs (15cs of which appears to be loading the second copy of the file, judging by *SLoad timings)


Version 5.35, 4.79.2.321. Tagged as 'Kernel-5_35-4_79_2_321'

Detail:
  s/ARMops, s/HAL - Move CPU feature init to after the RAM clear, to prevent the cached values being clobbered on platforms where the HAL doesn't perform the RAM clear
  s/CPUFeatures - Update/clarify comment
Admin:
  Tested on Raspberry Pi
  Fixes issue spotted by Sprow


Version 5.35, 4.79.2.320. Tagged as 'Kernel-5_35-4_79_2_320'

Add new OS_PlatformFeatures reason code for reading CPU features (inspired by ARMv6+ CPUID scheme). Add OS_ReadSysInfo 8 flags for indicating the alignment mode the ROM was built with. Fix long-standing bug with OS_PlatformFeatures when an unknown reason code is used.

Detail:
  s/CPUFeatures, hdr/OSMisc, hdr/KernelWS - Code and definitions for reading CPU features and reporting them via OS_PlatformFeatures 34. All the instruction set features which are exposed by the CPUID scheme and which are relevant to RISC OS are exposed, along with a few extra flags which we derive ourselves (e.g. things relating to < ARMv4, and some register usage restrictions in instructions). s/CPUFeatures is designed to be easily copyable into a future version of CallASWI without requiring any changes.
  s/ARMops - Read and cache CPU features during ARMop initialisation
  s/GetAll - GET new file
  s/Kernel - Hook up the CPU features code to OS_PlatformFeatures. Fix a long standing stack imbalance bug (fixed in RISC OS 3.8, but never merged back to our main branch) which meant that calling OS_PlatformFeatures with an invalid reason code would raise an error, even if it was the X form of the SWI that was called. Similar fix also applied to the unused service call code, along with a fix for the user's R1-R9 being corrupt (shuffled up one place) should an error have been generated.
  s/MemInfo - Extra LTORG needed to keep things happy
  s/Middle - Extend OS_ReadSysInfo 8 to include flags for indicating what memory alignment mode (if any) the OS relies upon. Together with OS_PlatformFeatures 34 this could e.g. be used by !CPUSetup to determine which options should be offered to the user.
Admin:
  Tested on Raspberry Pi 1, 2, 3


Version 5.35, 4.79.2.319. Tagged as 'Kernel-5_35-4_79_2_319'

Detail:
  s/HeapSort, s/vdu/vdugrafc, s/vdu/vduswis - Avoid unnecessary remainder calculations in DivRem macro
  s/PMF/i2cutils, s/PMF/osword - Make use of DivRem's ability to accept a constant as the divisor
Admin:
  Tested on Cortex-A15


Version 5.35, 4.79.2.318. Tagged as 'Kernel-5_35-4_79_2_318'

The TST operations for LongMul & Thumb were at odds with the ARM ARM, move those. We can get the DSP flag from an ID register too now, rather than relying on the Q flag being writeable in the PSR.
Fortunately, the fields we were previously TSTing also had set bits - so the OS_PlatformFeatures 0 flags were coming out right anyway on all real ARMv7's.

Version 5.35, 4.79.2.317. Tagged as 'Kernel-5_35-4_79_2_317'

Version 5.35, 4.79.2.316. Tagged as 'Kernel-5_35-4_79_2_316'

Detail:
  s/Kernel - Some types of error lookup code work by passing a bogus error number into MessageTrans_ErrorLookup and then fixing it up afterwards. To avoid breaking such code, we'll now ignore any bad error numbers from XMessageTrans_ErrorLookup. However obviously bad pointers and the non-X form will still be caught.
Admin:
  Tested on Raspberry Pi 3
  (e.g.) SWI "XMessageTrans_Lookup","@@@@BadParm" now works


Version 5.35, 4.79.2.315. Tagged as 'Kernel-5_35-4_79_2_315'

Detail:
  s/Kernel, hdr/KernelWS - Avoid performing error pointer checks for XOS_GenerateError, since (a) it's a no-op as far as errors are concerned, and (b) many programs take advantage of that fact and abuse the SWI for other purposes (triggering callbacks, BASIC string conversion, etc.)
Admin:
  Tested on Raspberry Pi
  Fixes issue reported on forums with Sunfish crashing:
  https://www.riscosopen.org/forum/forums/5/topics/4060


Version 5.35, 4.79.2.314. Tagged as 'Kernel-5_35-4_79_2_314'

Detail:
  Resources/UK/Messages, hdr/KernelWS, s/Kernel - On return from a SWI with V set, do some basic validity checks on the error pointer in order to try and catch buggy SWIs that return bad pointers or invalid error blocks. If a bad pointer is found we'll substitute it with a pointer to a different error block, which has the SWI number in the error message, to allow the user to identify the source of the problem. (There's also a chance we'll crash when investigating a bad pointer, but crashing here in the kernel is preferable to crashing elsewhere because R12 should still contain the SWI number)
  hdr/OSMisc - Define SeriousErrorV reason codes and extended ROM footer entry IDs
  hdr/Options - Remove HangWatch integration flag, obsolete now that SeriousErrorV is available
  s/ArthurSWIs - Keep defaultvectab up to date with vector allocations
  s/Middle - Update serious error handling to call SeriousErrorV at several key points. This allows for accurate crash dumps to be obtained, along with a mechanism to warn low-level components such as RTSupport that the privileged mode stacks are being flattened.
  s/Middle - Add OS_ReadSysInfo 15, for enumerating extended ROM footer entries
  s/PMF/osbyte - Update InitNewFX0Error to use the ROM footer entry ID defined in hdr/OSMisc
Admin:
  Tested on Pi 1B, 2B, 3B


Version 5.35, 4.79.2.313. Tagged as 'Kernel-5_35-4_79_2_313'

Version 5.35, 4.79.2.312. Tagged as 'Kernel-5_35-4_79_2_312'

Detail:
  s/MemInfo - Wrap OS_Memory 0 in some code which will temporarily claim the FIQ vector when making pages temporarily uncacheable, to avoid any issues caused by modern ARMs ignoring unexpected cache hits
  s/VMSAv6 - Claim FIQs when OS_MMUControl is asked to make a change to the SCTLR, to avoid similar issues on modern ARMs. Also make the stack temporarily uncacheable before disabling the cache, so that we don't run into any problems using the stack inbetween disabling the cache and completing the clean+invalidate.
Admin:
  Tested on Pi 2B, 3B
  *Cache off now works reliably on Pi 2B, although there is sometimes a pause of a few seconds while things sort themselves out (USB?)
  *Cache off "works" on Pi 3B but everything will fall over soon afterwards due to the Cortex-A53 not supporting LDREX/STREX to non-cacheable pages (or when the page is effectively non-cacheable, i.e. cacheable page with cache disabled)


Version 5.35, 4.79.2.311. Tagged as 'Kernel-5_35-4_79_2_311'

Detail:
  hdr/HALDevice - Reserve device IDs for BCM283x CPU clock device and GPU mailbox device
Admin:
  Tested on Raspberry Pi 1B/2B/3B


Version 5.35, 4.79.2.310. Tagged as 'Kernel-5_35-4_79_2_310'

Detail:
  (remove reference to SPIDevice in makefile)


Version 5.35, 4.79.2.309. Tagged as 'Kernel-5_35-4_79_2_309'

Version 5.35, 4.79.2.308. Tagged as 'Kernel-5_35-4_79_2_308'

Detail:
  s/MemInfo - To avoid cache coherency issues when the current SVC stack page is being made uncacheable, shift SP somewhere else by temporarily dropping into IRQ mode
  s/ARMops - Change default VMSAv6 cache policy to writeback, write allocate. Unlike other CPUs we've supported so far, Cortex-A53 suffers very badly from writes to read-allocate pages, with performance being roughly equivalent to writes to non-cacheable memory. Using a write (+read) allocate policy seems to be needed to get the expected performance, and may help boost other CPUs too.
Admin:
  Tested on IGEPv5, Pi 3


Version 5.35, 4.79.2.307. Tagged as 'Kernel-5_35-4_79_2_307'

Detail:
  This set of changes tackles two main issues:
  * Before mapping out a cacheable page or making it uncacheable, the OS performs a cache clean+invalidate op. However this leaves a small window where data may be fetched back into the cache, either accidentally (dodgy interrupt handler) or via agressive prefetch (as allowed for by the architecture). This rogue data can then result in coherency issues once the pages are mapped out or made uncacheable a short time later.
    The fix for this is to make the page uncacheable before performing the cache maintenance (although this isn't ideal, as prior to ARMv7 it's implementation defined whether address-based cache maintenance ops affect uncacheable pages or not - and on ARM11 it seems that they don't, so for that CPU we currently force a full cache clean instead)
  * Modern ARMs generally ignore unexpected cache hits, so there's an interrupt hole in the current OS_Memory 0 "make temporarily uncacheable" implementation where the cache is being flushed after the page has been made uncacheable (consider the case of a page that's being used by an interrupt handler, but the page is being made uncacheable so it can also be used by DMA). As well as affecting ARMv7+ devices this was found to affect XScale (and ARM11, although untested for this issue, would have presumably suffered from the "can't clean uncacheable pages" limitation)
    The fix for this is to disable IRQs around the uncache sequence - however FIQs are currently not being dealt with, so there's still a potential issue there.
  File changes:
  - Docs/HAL/ARMop_API, hdr/KernelWS, hdr/OSMisc - Add new Cache_CleanInvalidateRange ARMop
  - s/ARM600, s/VMSAv6 - BangCam updated to make the page uncacheable prior to flushing the cache. Add GetTempUncache macro to help with calculating the page flags required for making pages uncacheable. Fix abort in OS_MMUControl on Raspberry Pi - MCR-based ISB was resetting ZeroPage pointer to 0
  - s/ARMops - Cache_CleanInvalidateRange implementations. PL310 MMU_ChangingEntry/MMU_ChangingEntries refactored to rely on Cache_CleanInvalidateRange_PL310, which should be a more optimal implementation of the cache cleaning code that was previously in MMU_ChangingEntry_PL310.
  - s/ChangeDyn - Rename FastCDA_UpFront to FastCDA_Bulk, since the cache maintenance is no longer performed upfront. CheckCacheabilityR0ByMinusR2 now becomes RemoveCacheabilityR0ByMinusR2. PMP LogOp implementation refactored quite a bit to perform cache/TLB maintenance after making page table changes instead of before. One flaw with this new implementation is that mapping out large areas of cacheable pages will result in multiple full cache cleans while the old implementation would have (generally) only performed one - a two-pass approach over the page list would be needed to solve this.
  - s/GetAll - Change file ordering so GetTempUncache macro is available earlier
  - s/HAL - ROM decompression changed to do full MMU_Changing instead of MMU_ChangingEntries, to make sure earlier cached data is truly gone from the cache. ClearPhysRAM changed to make page uncacheable before flushing cache.
  - s/MemInfo - OS_Memory 0 interrupt hole fix
  - s/AMBControl/memmap - AMB_movepagesout_L2PT now split into cacheable+non-cacheable variants. Sparse map out operation now does two passes through the page list so that they can all be made uncacheable prior to the cache flush + map out.
Admin:
  Tested on StrongARM, XScale, ARM11, Cortex-A7, Cortex-A9, Cortex-A15, Cortex-A53
  Appears to fix the major issues plaguing SATA on IGEPv5


Version 5.35, 4.79.2.306. Tagged as 'Kernel-5_35-4_79_2_306'

Detail:
  s/HAL - Change RISCOS_AccessPhysicalAddress & RISCOS_ReleasePhysicalAddress (aka OS_Memory 14 & 15) to use the MMU_ChangingUncached ARMop instead of TLB_InvalidateEntry, as on ARMv6+ the MMU version ensures the write has been flushed to be visible by the TLB, while the TLB invalidate call doesn't.
  Fix RISCOS_MapInIO (aka OS_Memory 13) not detecting regions which have already been mapped in due to L1_XN flag masking issue. Also issue DSB+ISB after the page table write(s) to ensure it's visible by the TLB hardware.
Admin:
  Tested on IGEPv5


Version 5.35, 4.79.2.305. Tagged as 'Kernel-5_35-4_79_2_305'

Detail:
  * Filled in CPU tables for publicly documented ARMv8 cores (Cortex-A53,57,72).
  * Recent ARM ARMs (e.g. section B1.9.2 of the ARMv7AR ARM) permit the core to
    take an undefined instruction exception upon encountering even not-taken
    conditional undefined instructions. This option is exercised by the
    Cortex-A53, unlike all ARMv7 cores previously supported by RISC OS. This
    unfortunately trips up a lot of kernel code that adapts to different
    architectures at runtime. These have now all been replaced with branches
    over the affected code on the opposite condition.
  * Fixed bug in HAL_InvalidateCache_ARMvF: for the main body of the loop,
    which was written as though to act on the CLIDR register, r8 actually
    contained the CTR register instead.
Admin:
  Tested on Raspberry Pi 3

Version 5.35, 4.79.2.304. Tagged as 'Kernel-5_35-4_79_2_304'

For disc based applications (ie. those that don't know the architecture at build time, like a ROM would) we have OS_PlatformFeatures to provide an abstract way of seeing when new chunks of instructions get added. Back at ARMv6 ARM deprecated SWP, but currently we have no way of knowing that at runtime without grubbing round the coprocessor registers.
Add 3 new flags
* One to say LDR/STREX is (not) available
* One to say that SWP/SWPB is (not) available
* One to say that CLREX and LDR/STREX[B|H|D] is (not) available
shame it took a few goes for ARM to bring in these variants, requiring 3 flags not 1.

Also:
Condition the exception on vector read code on No32bitCode, rather than just having it permanently disabled.
Improve the HAL device docs.

Tested on a StrongARM Risc PC, Model B Pi, and Titanium.

Version 5.35, 4.79.2.303. Tagged as 'Kernel-5_35-4_79_2_303'

The HAL device APIs are modelled around the C APCS, and furthermore can be implemented either in a HAL (with SB) or RISC OS module (with R12). Therefore, exporting SB or requiring its use as a function argument precludes implementing the device in a normal module.
For examples of how to keep track of SB for the HAL case, see AudC or BMU or CPUClk or DMA or GPIO or IDE or Mixer or RTC or SDHCI or CacheC devices, which typically keep it in their HAL workspace referenced relative to the device pointer passed in a1/R0.

Detail:
  s/vdu/vduswis - Fix conversion of mode specifier to mode string so that the X eigen value is only reported in the mode string if it was included in the mode specifier; previously was erroneously basing the decision on whether the Y eigen was specified, resulting in e.g. "EX4294967295" if only the Y eigen was included
  - Fix a stack imbalance causing the conversion of mode string to mode specifier crashing (typically with branch through zero) if an invalid eigen value is specified in the string (e.g. EX-1 as above)
Admin:
  Tested on Raspberry Pi


Version 5.35, 4.79.2.302. Tagged as 'Kernel-5_35-4_79_2_302'

Subreason 7 returns a string naming the HAL platform. Use HAL entry 97 to get this, and obsolete 97/98/99 in favour of using a HAL device. Line up the HAL video entries to match the others.
Subreason 6 is just back filling one ROL added, testing this on RISC OS Select just returned the OS name so we do the same now (same as subreason 0, not sure what ROL's distinction was for).
Allocate a HAL device for PATA IDE controllers, and the 2 known ones to date - Tungsten and IOMD systems.

Version 5.35, 4.79.2.301. Tagged as 'Kernel-5_35-4_79_2_301'

Detail:
  hdr/HALDevice - Allocate device IDs for iMX6 HDMI audio controller, and a generic software mixer
Admin:
  Tested in iMX6 ROM build


Version 5.35, 4.79.2.300. Tagged as 'Kernel-5_35-4_79_2_300'

Fix overriding of default CMOS settings. Reserve HAL device ID for the official Raspberry Pi touchscreen/display.

Detail:
  s/PMF/i2cutils - Move $CMOS_Override to the start of DefaultCMOSTable, so that it can be used to override values which are already in the table (since NVMemory_ResetValue stops its search on the first address match)
  hdr/HALDevice - Add new Touchscreen device type and reserve an ID for the official Pi touchscreen controller
Admin:
  Tested on Raspberry Pi
  Fixes filesystem incorrectly defaulting to ADFS


Version 5.35, 4.79.2.299. Tagged as 'Kernel-5_35-4_79_2_299'

Detail:
  Rather than fill the Kernel sources with an ever-increasing number of
  platform-specific switches to control the default CMOS settings, this
  change introduces a variable which passes the requirements direct from
  the Components file to the Kernel. Since it uses a comma-separated list
  of address/value pairs, it is inherently extensible. All the symbolic
  names of addresses from Hdr:CMOS are available, and any valid objasm
  expression can be used for the value.
Admin:
  This removes the need for the EnforceSCSI4 switch, and leaves almost
  no uses of the Machine variable in the Kernel either.


Version 5.35, 4.79.2.298. Tagged as 'Kernel-5_35-4_79_2_298'

Detail:
  Raise the maximum number of interrupts and IIC buses acceptable, to account for the OMAP5 port.
  Add TLV320/TLV320/SDMA/SDMA/AM572x/GC320/CPSW/SynopsisDWC for Titanium.
  Add OMAP5/OMAP5/OMAP5/TWL6037/OMAP5/OMAP5/SynopsisDWC for OMAP5.
Admin:
  There's likely some rationalisation to be had here, these controllers especially across the OMAP3/4/5 are probably the same thing really and don't merit individual allocations.

Version 5.35, 4.79.2.297. Tagged as 'Kernel-5_35-4_79_2_297'

The kernel has no place holding this header export, since it doesn't use it nor implement any of its interfaces.

Version 5.35, 4.79.2.296. Tagged as 'Kernel-5_35-4_79_2_296'

Version 5.35, 4.79.2.295. Tagged as 'Kernel-5_35-4_79_2_295'

Detail:
  s/vdu/vdugrafj - Rewrite WritePaletteFromSprite to fix some issues with the logic which decides whether to change screen mode:
  - ModeNo was always being treated as if it was a mode selector block, causing bad pointer dereferences if it was actually a numbered mode. Prior to zero page protection the code would have eventually stumbled its way through to the mode change code.
  - For checking the pixel format, only the Log2BPP was being compared, resulting in code deciding that (e.g.) modes with differing RGB order were the same
  - However the eigen value checking was also broken (checking wrong part of generated mode selector block), causing the mode change logic to always be taken
  s/vdu/vdugrafdec - Increase size of SloadModeSel so it's actually large enough to hold the generated mode selector - old code would have run off the end a bit (thankfully, it was the last thing in that particular workspace block)
Admin:
  Tested on BB-xM, *ScreenLoad'ing sprites from various modes
  Fixes issue reported on forums:
  https://www.riscosopen.org/forum/forums/4/topics/3649


Version 5.35, 4.79.2.294. Tagged as 'Kernel-5_35-4_79_2_294'

Detail:
  s/ChangeDyn - Fix a couple of places where registers were being clobbered, preventing application space & shrinkable DA shrinking logic from being invoked correctly when performing a PMP PhysOp call
Admin:
  Tested on Raspberry Pi


Version 5.35, 4.79.2.293. Tagged as 'Kernel-5_35-4_79_2_293'

Detail:
  s/Middle - When handling an FIQ-mode exception, protect the register dump pointer around the call to HAL_FIQDisableAll
Admin:
  Tested on Raspberry Pi
  Fixes data abort within kernel when an abort occurs is FIQ mode


Version 5.35, 4.79.2.292. Tagged as 'Kernel-5_35-4_79_2_292'

Detail:
  s/ChangeDyn - A few fixes to make behaviour be a closer match for the pre-PMP code, and a bit of tidying to get rid of redundant code paths:
  - Remove shrinkable DA checks from AreaShrink - the source of the op is never the free pool, so TryToShrinkShrinkables wouldn't have done anything anyway
  - Fix ShrinkFreePoolToAppSpace to behave more like old OS_ChangeDynamicArea when it was asked to shrink the free pool - allow partial moves (if move amount too large to fit in app space), shrink shrinkables if free pool is unable to satisfy request, and call CheckAppSpace to make sure app space is OK with being changed
  - Remove redundant logic from AreaGrow for clamping grow size to free pool max size (if dest was free pool - dest will never be free pool with current implementation). "Dest is apl space, moving reduced amount" comment was also inaccurate.
  - Fix AreaGrow logic for taking memory from application space to only do so if the dest isn't application space (I can't see anything in the old implementation to protect against this - but, then again, the old implementation didn't seem to fully deal with grows of application space properly anyway, e.g. MemLimit would be updated on a free pool shrink, but not on an app space grow)
  - Add extra sanity check to AreaGrow after taking memory from application space
Admin:
  Tested on iMx6
  Fixes issue with application space having little or no memory if not booting to desktop (due to free pool shrink performed by kernel failing due to shrink amount being larger than app space max size)


Version 5.35, 4.79.2.291. Tagged as 'Kernel-5_35-4_79_2_291'

Detail:
  Default to SCSI::4 for boot driver is custom switch at buildtime
  (EnforceSCSI4) is defined. 2 fontcache items also defaulted with this switch
Admin:
  tested on iMx6


Version 5.35, 4.79.2.290. Tagged as 'Kernel-5_35-4_79_2_290'

Detail:
  s/PMF/IIC - when dealing with IIC transfers which use the high-level HAL API, take into account the bus speed when calculating the max retry count. Otherwise if (e.g.) writing to CMOS we may give up before the device has recovered from the previous write (which is typically listed as a max time of 5ms)
Admin:
  Fixes issues with CMOS checksum not being updated correctly if using IIC bus speeds > 100khz


Version 5.35, 4.79.2.289. Tagged as 'Kernel-5_35-4_79_2_289'

Detail:
  Ideally, $Machine would only exist within Hdr:Machine, they define a class of machines which in turn requires the lowest common denominator. It doesn't encode any capabilities about the class (eg. amount of memory, screen capabilities, peripherals).
Admin:
  Fixes report of Pandaboard no longer booting, since it has no drive 4.

Detail:
  default SCSIFSDrive to 4, and both FontMax and FontSize to their
  max values. (the machines in question have a min of 512Meg of ram -
  being miserly with font caches is unhelpful)
Admin:
  tested on iMx6

Version 5.35, 4.79.2.288. Tagged as 'Kernel-5_35-4_79_2_288'