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Commit eb908a1e authored by Jeffrey Lee's avatar Jeffrey Lee
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OS_Memory 13/14/15 fixes 

Detail:
  s/HAL - Change RISCOS_AccessPhysicalAddress & RISCOS_ReleasePhysicalAddress (aka OS_Memory 14 & 15) to use the MMU_ChangingUncached ARMop instead of TLB_InvalidateEntry, as on ARMv6+ the MMU version ensures the write has been flushed to be visible by the TLB, while the TLB invalidate call doesn't.
  Fix RISCOS_MapInIO (aka OS_Memory 13) not detecting regions which have already been mapped in due to L1_XN flag masking issue. Also issue DSB+ISB after the page table write(s) to ensure it's visible by the TLB hardware.
Admin:
  Tested on IGEPv5


Version 5.35, 4.79.2.305. Tagged as 'Kernel-5_35-4_79_2_305'
parent 66b90f9d
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Showing with 16 additions and 9 deletions
VersionASM
View file @ eb908a1e
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.304"
Module_MinorVersion SETS "4.79.2.305"
Module_Date SETS "29 Feb 2016"
Module_ApplicationDate SETS "29-Feb-16"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.304)"
Module_HelpVersion SETS "5.35 (29 Feb 2016) 4.79.2.304"
Module_FullVersion SETS "5.35 (4.79.2.305)"
Module_HelpVersion SETS "5.35 (29 Feb 2016) 4.79.2.305"
END
VersionNum
View file @ eb908a1e
......@@ -5,12 +5,12 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.304
#define Module_MinorVersion_CMHG 4.79.2.305
#define Module_Date_CMHG 29 Feb 2016
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.304"
#define Module_MinorVersion "4.79.2.305"
#define Module_Date "29 Feb 2016"
#define Module_ApplicationDate "29-Feb-16"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.304)"
#define Module_HelpVersion "5.35 (29 Feb 2016) 4.79.2.304"
#define Module_FullVersion "5.35 (4.79.2.305)"
#define Module_HelpVersion "5.35 (29 Feb 2016) 4.79.2.305"
#define Module_LibraryVersionInfo "5:35"
s/HAL
View file @ eb908a1e
......@@ -2095,7 +2095,7 @@ RISCOS_AccessPhysicalAddressUnchecked ; well OK then, I trust
MOV a3, a2, LSL #12 ; take bottom 20 bits of address
ORR a3, a1, a3, LSR #12 ; and make an offset within PhysicalAccess
Push "a3,lr"
ARMop TLB_InvalidateEntry ; sufficient, cause not cacheable
ARMop MMU_ChangingUncached ; sufficient, cause not cacheable
Pull "a1,pc"
; void RISCOS_ReleasePhysicalAddress(void *old)
......@@ -2103,7 +2103,7 @@ RISCOS_ReleasePhysicalAddress
LDR ip, =L1PT + (PhysicalAccess:SHR:18) ; ip -> L1PT entry
STR a1, [ip]
LDR a1, =PhysicalAccess
ARMop TLB_InvalidateEntry,,tailcall ; sufficient, cause not cacheable
ARMop MMU_ChangingUncached,,tailcall ; sufficient, cause not cacheable
; void Init_PageTablesChanged(void)
......@@ -2402,6 +2402,7 @@ RISCOS_MapInIO ROUT
AND a1, a1, v7 ; mask out unsupported attributes
[ MEMM_Type = "VMSAv6"
ORR a1, a1, #L1_XN ; force non-executable to prevent speculative instruction fetches
ORR v7, v7, #L1_XN
]
LDR v2, =IO ; logical end (exclusive) of currently mapped IO
LDR v1, [ip, #IOAllocPtr] ; logical start (inclusive)
......@@ -2494,6 +2495,12 @@ RISCOS_MapInIO ROUT
ADD v1, v1, #&100000 ; next section
CMP a2, a3
BLO %BT34
[ MEMM_Type = "VMSAv6"
; DSB + ISB required to ensure effect of page table write is fully
; visible (after overwriting a faulting entry)
myDSB ,a1
myISB ,a1,,y
]
LDR v1, [ip, #IOAllocPtr]
40
ADD a1, v1, v4 ; logical address for request
......
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