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Commit 96546b5a authored by Robert Sprowson's avatar Robert Sprowson
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Define some extra platform feature flags 

For disc based applications (ie. those that don't know the architecture at build time, like a ROM would) we have OS_PlatformFeatures to provide an abstract way of seeing when new chunks of instructions get added. Back at ARMv6 ARM deprecated SWP, but currently we have no way of knowing that at runtime without grubbing round the coprocessor registers.
Add 3 new flags
* One to say LDR/STREX is (not) available
* One to say that SWP/SWPB is (not) available
* One to say that CLREX and LDR/STREX[B|H|D] is (not) available
shame it took a few goes for ARM to bring in these variants, requiring 3 flags not 1.

Also:
Condition the exception on vector read code on No32bitCode, rather than just having it permanently disabled.
Improve the HAL device docs.

Tested on a StrongARM Risc PC, Model B Pi, and Titanium.

Version 5.35, 4.79.2.303. Tagged as 'Kernel-5_35-4_79_2_303'
parent d5669ff5
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Showing with 74 additions and 28 deletions
Docs/HAL/NewAPI
View file @ 96546b5a
......@@ -28,14 +28,13 @@ A simple call to a activate a device from assembler might look like:
If an assembler device driver module is using a lot of device calls, it
might be preferable to move the workspace pointer from the traditional R12
to R11.
The device descriptor
=====================
The device descriptor starts with a fixed format header, as described
below. Following this header are more function pointers providing device-specific
calls.
below. Following this header are more function pointers providing device-specific calls.
struct device
{
......@@ -186,6 +185,40 @@ Returns 0 if the device is not interrupting, or 1 if the device is interrupting.
When DeviceNumber is -1, this must be a null pointer.
Workspace
=========
As noted in the overview, a device may be implemented either in the HAL
or supplemented after the kernel starts through RISC OS modules.
The HAL uses the ATPCS assigned static base (sb/r9) to access position
independent data, while traditional modules use the workspace pointer (wp/r12).
Assembler modules use r12 directly, for C modules CMHG arranges this to keep
track of position independent data as r12 may be corrupted across function
calls as the ATPCS uses it as scratch register 'ip'.
When designing device specific extensions to the basic device descriptor, do
not create a dependence on the data pointer that would preclude implementing
the device in the HAL or a RISC OS module.
Each device specific extension takes a
struct device *
as its first argument. This is the structure which is defined as part of the
client API. You are free to keep other unrelated private data or state in
addition to this structure, typically this would be implemented as:
a) For a HAL based device, the device structure is typically allocated from
the global HAL workspace, so it is possible to compute the base of that
workspace (and hence recover sb) by subtraction.
Alternatively, keep a larger version of the structure internally, and
keep the original sb in a private area off the end or the one seen by
the client.
In both cases the original sb was known at the point the HAL device was
registered.
b) For a RISC OS module based device, keep private data in global variables
associated with your module. CMHG will dereference these automatically
by deriving offsets from the R12 value passed to the CMHG veneers.
Creation and removal of devices
===============================
......
VersionASM
View file @ 96546b5a
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.302"
Module_Date SETS "06 Jan 2016"
Module_ApplicationDate SETS "06-Jan-16"
Module_MinorVersion SETS "4.79.2.303"
Module_Date SETS "28 Feb 2016"
Module_ApplicationDate SETS "28-Feb-16"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.302)"
Module_HelpVersion SETS "5.35 (06 Jan 2016) 4.79.2.302"
Module_FullVersion SETS "5.35 (4.79.2.303)"
Module_HelpVersion SETS "5.35 (28 Feb 2016) 4.79.2.303"
END
VersionNum
View file @ 96546b5a
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.302
#define Module_Date_CMHG 06 Jan 2016
#define Module_MinorVersion_CMHG 4.79.2.303
#define Module_Date_CMHG 28 Feb 2016
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.302"
#define Module_Date "06 Jan 2016"
#define Module_MinorVersion "4.79.2.303"
#define Module_Date "28 Feb 2016"
#define Module_ApplicationDate "06-Jan-16"
#define Module_ApplicationDate "28-Feb-16"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.302)"
#define Module_HelpVersion "5.35 (06 Jan 2016) 4.79.2.302"
#define Module_FullVersion "5.35 (4.79.2.303)"
#define Module_HelpVersion "5.35 (28 Feb 2016) 4.79.2.303"
#define Module_LibraryVersionInfo "5:35"
hdr/OSMisc
View file @ 96546b5a
......@@ -35,6 +35,9 @@ CPUFlag_No26bitMode * 1:SHL:7 ; CPU does not support 26-bit mo
CPUFlag_LongMul * 1:SHL:8 ; Has M extensions (UMULL etc)
CPUFlag_Thumb * 1:SHL:9 ; Supports Thumb
CPUFlag_DSP * 1:SHL:10 ; Has E extensions (QADD etc)
CPUFlag_NoSWP * 1:SHL:11 ; CPU does not support SWP/SWPB
CPUFlag_LoadStoreEx * 1:SHL:12 ; Has LDR/STREX
CPUFlag_LoadStoreClearExSizes * 1:SHL:13 ; Has CLREX and LDR/STREX[B|H|D]
CPUFlag_ExtendedPages * 1:SHL:15 ; Supports extended small page L2 descriptors
CPUFlag_NoWBDrain * 1:SHL:16 ; CPU does not support Drain Write Buffer instruction
CPUFlag_AbortRestartBroken * 1:SHL:17 ; Aborts do not correctly follow documented abort model
......
s/ARMops
View file @ 96546b5a
......@@ -35,11 +35,11 @@ v7 RN 10
; AREA KernelCode,CODE,READONLY
; ARM keep changing their mind about ID field layout.
; Here's a summary, courtesy of the ARM ARM (v5):
; Here's a summary, courtesy of the ARM ARM:
;
; pre-ARM 7: xxxx0xxx
; ARM 7: xxxx7xxx where bit 23 indicates v4T/~v3
; post-ARM 7: xxxanxxx where n<>0 or 7 and a = architecture (1=4,2=4T,3=5,4=5T)
; post-ARM 7: xxxanxxx where n<>0 or 7 and a = architecture (1=v4,2=v4T,3=v5,4=v5T,5=v5TE,6=v5TEJ,7=v6)
;
; int Init_ARMarch(void)
......@@ -139,17 +139,8 @@ FindARMloop
TEQ a1, a2
ORREQ v5, v5, #CPUFlag_StorePCplus8
[ 0=1
; Check whether 26-bit mode is available
MSR CPSR_c, #F32_bit+I32_bit+SVC26_mode
MRS a1, CPSR
AND a1, a1, #M32_bits
TEQ a1, #SVC26_mode
ORRNE v5, v5, #CPUFlag_No26bitMode
MSREQ CPSR_c, #F32_bit+I32_bit+SVC32_mode
BNE %FT35
; Do we get vector exceptions on read?
[ No32bitCode
; Do we get vector exceptions on 26 bit read?
LDR a2, =ZeroPage
MOV a1, a2
LDR a1, [a1] ; If this aborts a1 will be left unchanged
......@@ -173,6 +164,9 @@ FindARMloop
TST lr, #Q32_bit
ORRNE v5, v5, #CPUFlag_DSP
TEQ a1, #ARMv6
ORREQ v5, v5, #CPUFlag_LoadStoreEx ; Implicit clear of CPUFlag_NoSWP for <= ARMv6
LDRB v4, [v6, #ProcessorType]
TEQ v4, #ARMunk ; Modify deduced flags
......@@ -976,6 +970,22 @@ ARM_Analyse_Fancy
TST lr, #Q32_bit
ORRNE v5, v5, #CPUFlag_DSP ; Should we check instruction set attr register 3 for this?
MRC p15, 0, a1, c0, c2, 0
TST a1, #&F ; Swap_instrs
MRC p15, 0, a1, c0, c2, 4
TSTEQ a1, #&F0000000 ; SWP_frac
ORREQ v5, v5, #CPUFlag_NoSWP
MRC p15, 0, a2, c0, c2, 3
AND a2, a2, #&00F000 ; SynchPrim_instrs
AND a1, a1, #&F00000 ; SynchPrim_instrs_frac
ORR a1, a2, a1, LSR #12
TEQ a1, #2_00010000:SHL:8
ORREQ v5, v5, #CPUFlag_LoadStoreEx
TEQ a1, #2_00010011:SHL:8
TEQNE a1, #2_00100000:SHL:8
ORREQ v5, v5, #CPUFlag_LoadStoreEx :OR: CPUFlag_LoadStoreClearExSizes
; Other flags not checked for above:
; CPUFlag_InterruptDelay
; CPUFlag_VectorReadException
......
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