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Commit 66b90f9d authored by Ben Avison's avatar Ben Avison
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Support for ARMv8 

Detail:
  * Filled in CPU tables for publicly documented ARMv8 cores (Cortex-A53,57,72).
  * Recent ARM ARMs (e.g. section B1.9.2 of the ARMv7AR ARM) permit the core to
    take an undefined instruction exception upon encountering even not-taken
    conditional undefined instructions. This option is exercised by the
    Cortex-A53, unlike all ARMv7 cores previously supported by RISC OS. This
    unfortunately trips up a lot of kernel code that adapts to different
    architectures at runtime. These have now all been replaced with branches
    over the affected code on the opposite condition.
  * Fixed bug in HAL_InvalidateCache_ARMvF: for the main body of the loop,
    which was written as though to act on the CLIDR register, r8 actually
    contained the CTR register instead.
Admin:
  Tested on Raspberry Pi 3

Version 5.35, 4.79.2.304. Tagged as 'Kernel-5_35-4_79_2_304'
parent 96546b5a
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Showing with 69 additions and 24 deletions
Resources/UK/Messages
View file @ 66b90f9d
......@@ -189,3 +189,6 @@ CA8:Cortex-A8 Processor
CA9:Cortex-A9 Processor
CA15:Cortex-A15 Processor
CA17:Cortex-A17 Processor
CA53:Cortex-A53 Processor
CA57:Cortex-A57 Processor
CA72:Cortex-A72 Processor
VersionASM
View file @ 66b90f9d
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.303"
Module_Date SETS "28 Feb 2016"
Module_ApplicationDate SETS "28-Feb-16"
Module_MinorVersion SETS "4.79.2.304"
Module_Date SETS "29 Feb 2016"
Module_ApplicationDate SETS "29-Feb-16"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.303)"
Module_HelpVersion SETS "5.35 (28 Feb 2016) 4.79.2.303"
Module_FullVersion SETS "5.35 (4.79.2.304)"
Module_HelpVersion SETS "5.35 (29 Feb 2016) 4.79.2.304"
END
VersionNum
View file @ 66b90f9d
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.303
#define Module_Date_CMHG 28 Feb 2016
#define Module_MinorVersion_CMHG 4.79.2.304
#define Module_Date_CMHG 29 Feb 2016
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.303"
#define Module_Date "28 Feb 2016"
#define Module_MinorVersion "4.79.2.304"
#define Module_Date "29 Feb 2016"
#define Module_ApplicationDate "28-Feb-16"
#define Module_ApplicationDate "29-Feb-16"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.303)"
#define Module_HelpVersion "5.35 (28 Feb 2016) 4.79.2.303"
#define Module_FullVersion "5.35 (4.79.2.304)"
#define Module_HelpVersion "5.35 (29 Feb 2016) 4.79.2.304"
#define Module_LibraryVersionInfo "5:35"
hdr/ARMops
View file @ 66b90f9d
......@@ -50,6 +50,9 @@ Cortex_A9 # 1
Cortex_A12 # 1
Cortex_A15 # 1
Cortex_A17 # 1
Cortex_A53 # 1
Cortex_A57 # 1
Cortex_A72 # 1
ARMunk * 255
; The macro to do an ARM operation. All ARM operations are expected
......
s/ARMops
View file @ 66b90f9d
......@@ -614,16 +614,18 @@ Analyse_WB_CR7_Lx
MOV a3, #0
10
ANDS v1, a1, #6 ; Data or unified cache at this level?
BEQ %FT11
MCRNE p15, 2, a3, c0, c0, 0 ; Program cache size selection register
myISB ,v1
MRCNE p15, 1, v1, c0, c0, 0 ; Get size info (data/unified)
STR v1, [a2]
11 STR v1, [a2]
ADD a3, a3, #1
ANDS v1, a1, #1 ; Instruction cache at this level?
BEQ %FT12
MCRNE p15, 2, a3, c0, c0, 0 ; Program cache size selection register
myISB ,v1
MRCNE p15, 1, v1, c0, c0, 0 ; Get size info (instruction)
STR v1, [a2, #Cache_Lx_ITable-Cache_Lx_DTable]
12 STR v1, [a2, #Cache_Lx_ITable-Cache_Lx_DTable]
; Shift the cache level ID register along to get the type of the next
; cache level
; However, we need to stop once we reach the first blank entry, because
......@@ -827,6 +829,9 @@ KnownCPUTable_Fancy
CPUDesc Cortex_A12, &00C0D0, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
CPUDesc Cortex_A15, &00C0F0, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
CPUDesc Cortex_A17, &00C0E0, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
CPUDesc Cortex_A53, &00D030, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
CPUDesc Cortex_A57, &00D070, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
CPUDesc Cortex_A72, &00D080, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
DCD -1
] ; MEMM_Type = "VMSAv6"
......@@ -857,6 +862,9 @@ KnownCPUFlags
DCD 0, 0 ; Cortex_A12
DCD 0, 0 ; Cortex_A15
DCD 0, 0 ; Cortex_A17
DCD 0, 0 ; Cortex_A53
DCD 0, 0 ; Cortex_A57
DCD 0, 0 ; Cortex_A72
[ MEMM_Type = "VMSAv6"
; --------------------------------------------------------------------------
......@@ -2517,6 +2525,7 @@ MMU_ChangingUncachedEntries_WB_CR7_Lx ROUT
myDSB ,lr ; Ensure the page table write has actually completed
myISB ,lr,,y ; Also required
CMP a2, #32 ; arbitrary-ish threshold
BLO %FT10
MCRHS p15, 0, a1, c8, c7, 0 ; invalidate ITLB and DTLB
BHS %FT20
10
......@@ -3025,6 +3034,9 @@ PNameTable
DCW PName_Cortex_A17 - PNameTable ; A12 rebranded as A17
DCW PName_Cortex_A15 - PNameTable
DCW PName_Cortex_A17 - PNameTable
DCW PName_Cortex_A53 - PNameTable
DCW PName_Cortex_A57 - PNameTable
DCW PName_Cortex_A72 - PNameTable ; A58 rebranded as A72
PName_ARM600
= "600:ARM 600 Processor",0
......@@ -3070,6 +3082,12 @@ PName_Cortex_A15
= "CA15:Cortex-A15 Processor",0
PName_Cortex_A17
= "CA17:Cortex-A17 Processor",0
PName_Cortex_A53
= "CA53:Cortex-A53 Processor",0
PName_Cortex_A57
= "CA57:Cortex-A57 Processor",0
PName_Cortex_A72
= "CA72:Cortex-A72 Processor",0
ALIGN
......
s/HAL
View file @ 66b90f9d
......@@ -95,12 +95,17 @@ RISCOS_InitARM
[ MEMM_Type = "VMSAv6"
CMP a1, #ARMvF
; Assume that all ARMvF ARMs have multi-level caches and thus no single MCR op for invalidating all the caches
ADREQ lr, %FT01
BEQ HAL_InvalidateCache_ARMvF
MCRNE ARM_config_cp,0,a2,ARMv4_cache_reg,C7 ; invalidate I+D caches
BLEQ HAL_InvalidateCache_ARMvF
01
]
CMP a1, #ARMv3
BNE %FT01
MCREQ ARM_config_cp,0,a2,ARMv3_TLBflush_reg,C0 ; flush TLBs
MCRNE ARM_config_cp,0,a2,ARMv4_TLB_reg,C7 ; flush TLBs
B %FT02
01 MCRNE ARM_config_cp,0,a2,ARMv4_TLB_reg,C7 ; flush TLBs
02
[ MEMM_Type = "VMSAv6"
myDSB ,a2,,y
myISB ,a2,,y
......@@ -832,13 +837,18 @@ MMU_activation_zone
ARM_MMU_transbase v3 ; Always useful to tell it where L1PT is...
MOV lr, #0
BNE %FT01
MCREQ p15, 0, lr, c5, c0 ; MMU may already be on (but flat mapped)
MCRNE p15, 0, lr, c8, c7 ; if HAL needed it (eg XScale with ECC)
; so flush TLBs now
B %FT02
01 MCRNE p15, 0, lr, c8, c7 ; if HAL needed it (eg XScale with ECC)
02 ; so flush TLBs now
[ MEMM_Type = "VMSAv6"
CMP ip, #ARMv6
BLT %FT01
MCRGE p15, 0, lr, c2, c0, 2 ; Ensure only TTBR0 is used (v6)
BLE %FT01
MCRGT p15, 0, lr, c12, c0, 0 ; Ensure exception vector base is 0 (Cortex)
01
myISB ,lr,,y
ORRGE v5, v5, #MMUC_XP ; Extended pages enabled (v6)
BICGE v5, v5, #MMUC_TRE+MMUC_AFE ; TEX remap, Access Flag disabled
......@@ -862,12 +872,15 @@ MMUon_instr
[ MEMM_Type = "VMSAv6"
CMP ip, #ARMvF
BEQ %FT01
MCRNE ARM_config_cp,0,lr,ARMv4_cache_reg,C7 ; junk MMU-off contents of I-cache (works on ARMv3)
MCREQ p15, 0, lr, c7, c5, 0 ; invalidate instruction cache
B %FT02
01 MCREQ p15, 0, lr, c7, c5, 0 ; invalidate instruction cache
MCREQ p15, 0, lr, c8, c7, 0 ; invalidate TLBs
MCREQ p15, 0, lr, c7, c5, 6 ; invalidate branch predictor
myISB ,lr,,y ; Ensure below branch works
BLEQ HAL_InvalidateCache_ARMvF ; invalidate data cache (and instruction+TLBs again!)
02
|
MOV lr, #0 ; junk MMU-off contents of I-cache
MCR ARM_config_cp,0,lr,ARMv4_cache_reg,C7 ; (works on ARMv3)
......@@ -1375,10 +1388,10 @@ HAL_InvalidateCache_ARMvF
; Check whether we're ARMv7 (and thus multi-level cache) or ARMv6 (and thus single-level cache)
MRC p15, 0, r8, c0, c0, 1
TST r8, #&80000000 ; EQ=ARMv6, NE=ARMv7
MCREQ ARM_config_cp,0,r9,ARMv4_cache_reg,C7 ; ARMv3-ARMv6 I+D cache flush
BEQ %FT50 ; Skip to the end
BEQ %FT80
; This is basically the same algorithm as the MaintainDataCache_WB_CR7_Lx macro, but tweaked to use less registers and to read from CP15 directly
MRC p15, 1, r8, c0, c0, 1 ; Read CLIDR to r8
TST r8, #&07000000
BEQ %FT50
MOV r11, #0 ; Current cache level
......@@ -1409,7 +1422,7 @@ HAL_InvalidateCache_ARMvF
SUBS r8, r8, #1 ; decrement the way number
BGE %BT20
myDSB ,r8 ; Cortex-A7 errata 814220: DSB required when changing cache levels when using set/way operations. This also counts as our end-of-maintenance DSB.
MRC p15, 0, r8, c0, c0, 1
MRC p15, 1, r8, c0, c0, 1
40 ; Skip
ADD r11, r11, #2
AND r14, r8, #&07000000
......@@ -1428,6 +1441,9 @@ HAL_InvalidateCache_ARMvF
MSR CPSR_c, #F32_bit+I32_bit+SVC32_mode
MSR CPSR_cxsf, ip
MOV pc, lr
80 ; ARMv6 case
MCR ARM_config_cp,0,r9,ARMv4_cache_reg,C7 ; ARMv3-ARMv6 I+D cache flush
B %BT50
] ; MEMM_Type = "VMSAv6"
CountPageTablePages ROUT
......@@ -2102,12 +2118,17 @@ Init_PageTablesChanged
MOV a3, lr
BL Init_ARMarch
MOV ip, #0
BNE %FT01
MCREQ ARM_config_cp,0,ip,ARMv3_TLBflush_reg,C0
MCRNE ARM_config_cp,0,ip,ARMv4_TLB_reg,C7
B %FT02
01 MCRNE ARM_config_cp,0,ip,ARMv4_TLB_reg,C7
02
[ MEMM_Type = "VMSAv6"
CMP a1, #ARMvF
ADREQ lr, %FT01
BEQ HAL_InvalidateCache_ARMvF
MCRNE ARM_config_cp,0,ip,ARMv4_cache_reg,C7 ; works on ARMv3
BLEQ HAL_InvalidateCache_ARMvF
01
|
MCR ARM_config_cp,0,ip,ARMv4_cache_reg,C7 ; works on ARMv3
]
......
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