1. 07 Sep, 2016 1 commit
    • Jeffrey Lee's avatar
      Misc memory management fixes · 2f224a37
      Jeffrey Lee authored
        s/ChangeDyn - Fix register corruption in PMP_LogOp when mapping a page into a location that already contains a page. Fix excessive TLB flush in AreaShrink.
        s/ARM600, s/VMSAv6 - Add asserts to GetTempUncache to detect invalid register combinations
        Tested on BB-xM
      Version 5.59. Tagged as 'Kernel-5_59'
  2. 23 Aug, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix stack imbalance and incorrect return value in OS_DynamicArea 23 (PMP resize) · d181963e
      Jeffrey Lee authored
        s/ChangeDyn - When OS_DynamicArea 23 returned an error, R2 wasn't being set to zero correctly, incorrectly suggesting that a change had been made. And when a non-error resize of zero was being performed, registers were being pulled twice, resulting in a stack imbalance and crash.
        Tested on BB-xM
      Version 5.58. Tagged as 'Kernel-5_58'
  3. 18 Aug, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix OS_FindMemMapEntries · d5e09872
      Jeffrey Lee authored
        s/ChangeDyn - Since the introduction of the 16 byte CAM entry format, OS_FindMemMapEntries has contained a bug where requesting the details for an address which does not have an L2PT page allocated for it (e.g. a location in ROM) would result in a misaligned CAM entry pointer being generated, resulting in either a crash or incorrect data being returned
        Tested on Raspberry Pi 2
        Fixes issue reported on forums:
      Version 5.57. Tagged as 'Kernel-5_57'
  4. 08 Aug, 2016 1 commit
  5. 02 Aug, 2016 2 commits
    • Jeffrey Lee's avatar
      Add support for shareable pages and additional access privileges · 9cd4cbe4
      Jeffrey Lee authored
        This set of changes:
        * Refactors page table entry encoding/decoding so that it's (mostly) performed via functions in the MMU files (s.ARM600, s.VMSAv6) rather than on an ad-hoc basis as was the case previously
        * Page table entry encoding/decoding performed during ROM init is also handled via the MMU functions, which resolves some cases where the wrong cache policy was in use on ARMv6+
        * Adds basic support for shareable pages - on non-uniprocessor systems all pages will be marked as shareable (however, we are currently lacking ARMops which broadcast cache maintenance operations to other cores, so safe sharing of cacheable regions isn't possible yet)
        * Adds support for the VMSA XN flag and the "privileged ROM" access permission. These are exposed via RISC OS access privileges 4 and above, taking advantage of the fact that 4 bits have always been reserved for AP values but only 4 values were defined
        * Adds OS_Memory 17 and 18 to convert RWX-style access flags to and from RISC OS access privelege numbers; this allows us to make arbitrary changes to the mappings of AP values 4+ between different OS/hardware versions, and allows software to more easily cope with cases where the most precise AP isn't available (e.g. no XN on <=ARMv5)
        * Extends OS_Memory 24 (CheckMemoryAccess) to return executability information
        * Adds exported OSMem header containing definitions for OS_Memory and OS_DynamicArea
        File changes:
        - Makefile - export C and assembler versions of hdr/OSMem
        - Resources/UK/Messages - Add more text for OS_Memory errors
        - hdr/KernelWS - Correct comment regarding DCacheCleanAddress. Allocate workspace for MMU_PPLTrans and MMU_PPLAccess.
        - hdr/OSMem - New file containing exported OS_Memory and OS_DynamicArea constants, and public page flags
        - hdr/Options - Reduce scope of ARM6support to only cover builds which require ARMv3 support
        - s/AMBControl/Workspace - Clarify AMBNode_PPL usage
        - s/AMBControl/growp, mapslot, mapsome, memmap - Use AreaFlags_ instead of AP_
        - s/AMBControl/main, memmap - Use GetPTE instead of generating page table entry manually
        - s/ARM600 - Remove old coments relating to lack of stack. Update BangCam to use GetPTE. Update PPL tables, removing PPLTransL1 (L1 entries are now derived from L2 table on demand) and adding a separate table for ARM6. Implement the ARM600 versions of the Get*PTE ('get page table entry') and Decode*Entry functions
        - s/ARMops - Add Init_PCBTrans function to allow relevant MMU_PPLTrans/MMU_PCBTrans pointers to be set up during the pre-MMU stage of ROM init. Update ARM_Analyse to set up the pointers that are used post MMU init.
        - s/ChangeDyn - Move a bunch of flags to hdr/OSMem. Rename the AP_ dynamic area flags to AreaFlags_ to avoid name clashes and confusion with the page table AP_ values exported by Hdr:MEMM.ARM600/Hdr:MEMM.VMSAv6. Also generate the relevant flags for OS_Memory 24 so that it can refer to the fixed areas by their name instead of hardcoding the permissions.
        - s/GetAll - GET Hdr:OSMem
        - s/HAL - Change initial page table setup to use DA/page flags and GetPTE instead of building page table entries manually. Simplify AllocateL2PT by removing the requirement for the user to supply the access perimssions that will be used for the area; instead for ARM6 we just assume that cacheable memory is the norm and set L1_U for any L1 entry we create here.
        - s/Kernel - Add GetPTE macro (for easier integration of Get*PTE functions) and GenPPLAccess macro (for easy generation of OS_Memory 24 flags)
        - s/MemInfo - Fixup OS_Memory 0 to not fail on seeing non-executable pages. Implement OS_Memory 17 & 18. Tidy up some error generation. Make OS_Memory 13 use GetPTE. Extend OS_Memory 24 to return (non-) executability information, to use the named CMA_ constants generated by s/ChangeDyn, and to use the Decode*Entry functions when it's necessary to decode page table entries.
        - s/NewReset - Use AreaFlags_ instead of AP_
        - s/VMSAv6 - Remove old comments relating to lack of stack. Update BangCam to use GetPTE. Update PPL tables, removing PPLTransL1 (L1 entries are now derived from L2 table on demand) and adding a separate table for shareable pages. Implement the VMSAv6 versions of the Get*PTE and Decode*Entry functions.
        Tested on Raspberry Pi 1, Raspberry Pi 3, Iyonix, RPCEmu (ARM6 & ARM7), comparing before and after CAM and page table dumps to check for any unexpected differences
      Version 5.55. Tagged as 'Kernel-5_55'
    • Robert Sprowson's avatar
      Remove a dead function · 72a424b7
      Robert Sprowson authored
      CheckBits is a hangover from when the kernel used to read the monitor ID lines on a Risc PC, no longer called with a HAL.
  6. 24 Jul, 2016 1 commit
    • Robert Sprowson's avatar
      Resolve 2x header clashes · 8cfe216b
      Robert Sprowson authored
        Remove this, since it clashes with the (differing API version number) copy exported by SATADriver. Post merging the Kernel back to the trunk the newer file datestamp has meant the wrong one gets exported during any ROM build which includes both components. Since the Kernel doesn't need AHCIDevice itself, it is left to the respective client (SATADriver or AHCIDriver in this case) to export them.
        Resolve the longstanding clash of Module_Title with the same named symbol that CMHG uses. There are very few assembler needing to look at the module header (Kernel, FileCore, Debugger, Podule) directly, but every C module which uses CMHG and wants one of the ModHandReason values ends up with a duplicate define.
        Obsolete Arthur era Module_LoadAddr value.
        Recode Module_LoadAddr using the file type from Hdr:FileTypes.
        Drop unused NVRAM and PortMan headers. Add Hdr:FileTypes.
      Version 5.54. Tagged as 'Kernel-5_54'
  7. 15 Jul, 2016 1 commit
    • Robert Sprowson's avatar
      Improve handling of *DUMPing a stream · cf929f7e
      Robert Sprowson authored
      The checks in *DUMP tried to spot a stream (ie. a file that can be opened with OS_Find but that OS_File 5 doesn't think is there), but in doing so never set the address or offset, so the hex values shown on the left of the screen would be whatever junk was in r2 & r3.
      Reorder the tests so it starts at 0 and runs until EOF.
      Make use of OSFile_ReadWithType rather than trying to deduce if it's an untyped file ourselves.
      Tested with
        *DUMP random:
      from SystemDevs-1_33.
      Version 5.53. Tagged as 'Kernel-5_53'
  8. 30 Jun, 2016 5 commits
    • Jeffrey Lee's avatar
      Tidy things up a bit · 055b24c3
      Jeffrey Lee authored
        hdr/Options - Reduce the scope of SASTMhatbroken and InterruptDelay switches so that they're only enabled when we're building for ARMv4 targets
        s/ARM600, s/VMSAv6, s/ExtraSWIs, s/Exceptions - Move duplicate code out of s/ARM600 & s/VMSAv6 and into shared locations. OS_UpdateMEMC, the bulk of OS_MMUControl, and OS_SynchroniseCodeAreas are now located in s/ExtraSWIs. Meanwhile the data & prefetch abort veneers have been moved to the new file s/Exceptions. s/ARM600 and s/VMSAv6 are now almost purely to do with the different page table formats.
        s/GetAll - GET s/Exceptions
        Tested on Raspberry Pi
      Version 5.52. Tagged as 'Kernel-5_52'
    • Jeffrey Lee's avatar
      Delete lots of old switches · f655fcf6
      Jeffrey Lee authored
        This change gets rid of the following switches from the source (picking appropriate code paths for a 32bit HAL build):
        * FixCallBacks
        * UseProcessTransfer
        * CanLiveOnROMCard
        * BleedinDaveBell
        * NewStyleEcfs
        * DoVdu23_0_12
        * LCDPowerCtrl
        * HostVdu
        * Print
        * EmulatorSupport
        * TubeInfo
        * AddTubeBashers
        * TubeChar, TubeString, TubeDumpNoStack, TubeNewlNoStack macros
        * FIQDebug
        * VCOstartfix
        * AssemblingArthur (n.b. still defined for safety with anything in Hdr: which uses it, but not used explicitly by the kernel)
        * MouseBufferFix
        * LCDInvert
        * LCDSupport
        * DoInitialiseMode
        * Interruptible32bitModes
        * MouseBufferManager
        * StrongARM (new CacheCleanerHack and InterruptDelay switches added to hdr/Options to cover some functionality that StrongARM previously covered)
        * SAcleanflushbroken
        * StrongARM_POST
        * IrqsInClaimRelease
        * CheckProtectionLink
        * GSWorkspaceInKernelBuffers
        * EarlierReentrancyInDAShrink
        * LongComman...
    • Jeffrey Lee's avatar
      Delete STB code · 9a571a08
      Jeffrey Lee authored
        This change gets rid of the following switches from the source (picking appropriate code paths for a desktop build):
        * STB
        * RO371Timings
        * NormalSpeedROMS
        * AutoSpeedROMS
        * RISCPCBurstMode
        * InterlacedPointer
        * ParallelFlashUpgrade (and s/FlashROM file)
        * Embedded_UI
        Some of the deleted code might be worth revisiting in future:
        * OS_ReadSysInfo 4 support for storing the MAC in alternate CMOS locations (including 2nd copy for error checking) or fetching via Service_MachineAddress
        * Mouse handling changes, possibly aimed at hiding the mouse pointer if a mouse isn't connected
        * More strict CMOS validation in s/NewReset
        Identical binary to previous revision for IOMD & Raspberry Pi builds
      Version 5.50. Tagged as 'Kernel-5_50'
    • Jeffrey Lee's avatar
      Delete pre-HAL and 26bit code · 7d5bfc66
      Jeffrey Lee authored
        This change gets rid of the following switches from the source (picking appropriate code paths for a 32bit HAL build):
        * HAL
        * HAL26
        * HAL32
        * No26bitCode
        * No32bitCode
        * IncludeTestSrc
        * FixR9CorruptionInExtensionSWI
        Various old files have also been removed (POST code, Arc/STB keyboard drivers, etc.)
        Identical binary to previous revision for IOMD & Raspberry Pi builds
      Version 5.49. Tagged as 'Kernel-5_49'
    • Jeffrey Lee's avatar
      Merge HAL branch to trunk · bafe3084
      Jeffrey Lee authored
        This change merges the past 15+ years of HAL branch development back to the trunk.
        This is effectively the end for non-HAL builds of the kernel, as no attempt has been made to maintain it during this merge, and all non-HAL & non-32bit code will soon be removed anyway.
        Rather than list everything that's been added to the HAL branch, it's easier to describe the change in terms of the things that the HAL branch was lacking:
        * Trunk version of Docs/32bit contained updated comments for the SVC stack structure during ErrorV
        * Trunk version of s/HeapMan contained a tweak to try and reduce the number of small free blocks that are created
        * Trunk version of s/Kernel contained a change to only copy 248 bytes of the error string to the error buffer (down from 252 bytes), to take into account the extra 4 bytes needed by the PSR. However this goes against the decision that's been made in the HAL branch that the error buffer should be enlarged to 260 bytes instead (ref: https://www.riscosopen.org/tracker/tickets/201), so the HAL build will retain its current behaviour.
        * Trunk version of s/MsgCode had RMNot32bit error in the list of error messages to count when countmsgusage {TRUE}
        * Trunk version of s/PMF/i2cutils contained support for OS_Memory 5, "read/write value of NVRamWriteSize". Currently the HAL branch doesn't have a use for this (in particular, the correct NVRamWriteSize should be specified by the HAL, so there should be no need for software to change it at runtime), and so this code will remain switched out in the HAL build.
        Tested on Raspberry Pi
      Version 5.48. Tagged as 'Kernel-5_48'
  9. 15 Jun, 2016 1 commit
    • Jeffrey Lee's avatar
      Clear the exclusive monitor when returning to pre-empted code · d10d2336
      Jeffrey Lee authored
        s/Kernel - Add macro for CLREX, which uses a dummy STREX on basic ARMv6 machines. Clear the exclusive monitor after issuing transient callbacks, to cope with callbacks being triggered on exit from IRQ
        s/ArthurSWIs, s/HAL, s/NewIRQs - Clear the exclusive monitor on exit from IRQ handlers & default FIQ handler
        s/VMSAv6 - Clear the exclusive monitor on entry to the data abort pre-veneer
        Tested on Raspberry Pi
        Non-transient callback handlers, custom abort handlers, FIQ handlers, and anything else which returns directly to interrupted user code is responsible for issuing its own CLREX if the code has done something that could have left the local monitor in the exclusive state (e.g. calling a SWI counts towards this, as there's no guarantee the monitor will be open on exit from the SWI)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_327'
  10. 01 Jun, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix teletext mode when zero page relocated · 8a653457
      Jeffrey Lee authored
        s/vdu/vduttx - References to VduDriverWorkSpace need to be ZeroPage-relative. Without relocation, it looks like most of these addresses were hitting the Debugger workspace page, avoiding an immediate crash but causing no text to appear on screen.
        Tested on Raspberry Pi 1
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_326'
  11. 24 May, 2016 1 commit
    • Jeffrey Lee's avatar
      Add OS_PlatformFeatures 0 flag to indicate that the "Unknown... · 417d0f7c
      Jeffrey Lee authored
      Add OS_PlatformFeatures 0 flag to indicate that the "Unknown OS_PlatformFeatures reason codes always raise an error" bug has been fixed
        hdr/OSMisc - Use bit 31 to indicate that the error reporting bug has been fixed
        s/ARMops - Make sure the flag is set when preparing ProcessorFlags (i.e. the OS_PlatformFeatures 0 flags)
        Tested on Raspberry Pi
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_325'
  12. 23 May, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix PMP corruption caused by early errors generated by OS_DynamicArea 21 · 88376e28
      Jeffrey Lee authored
        s/ChangeDyn - When DynArea_PMP_PhysOp generates an error during the initial page list scan, make sure r12 is initialised to the (new) PMP size, as expected by PMPMemoryMoved.
        s/AMBControl/allocate, s/AMBControl/growshrink - Document some extra exit conditions for the AMB allocate & grow/shrink routines
        Tested on BB-xM
        Fixes RAM disc PMP becoming corrupt when attempting to grow it (e.g. via *ChangeDynamicArea) by an amount larger than the amount of free memory in the system
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_324'
  13. 22 May, 2016 3 commits
    • Jeffrey Lee's avatar
      Revise comments - it's multiprocessing extensions, not virtualisation · 02664d59
      Jeffrey Lee authored
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_323'
    • Jeffrey Lee's avatar
      Revise WFE detection · 7c914258
      Jeffrey Lee authored
        s/CPUFeatures - Take account of the fact that single-core ARMv7+ chips implement MPIDR but aren't guaranteed to implement a useful WFE. So for ARMv7+, only report WFE as being available/useful if MPIDR indicates that virtualisation extensions are supported.
        Tested on Raspberry Pi 1 & 3, BB-xM
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_322'
    • Jeffrey Lee's avatar
      [308] SpriteOp 11 (merge sprite areas) gets slow for large numbers of sprites · 0b904557
      Jeffrey Lee authored
        s/vdu/vdugrafh - Rewrite MergeSpriteAreas so that memory movement is now O(N) instead of O(N^2). Checking for duplicate sprites is still slow (O(N^2) search), but this resolves the main performance bottleneck with the code.
        s/vdu/vdugrafg - Add a variant of SpriteCtrlBlk which skips the call to GetName; this helps MergeSpriteAreas for the common case of a dest area with lots of sprites and a source area with a handful of sprites (SpriteCtrlBlk is now called on the source area once per dest sprite, previously was called on the dest area once per source sprite).
        Tested on Raspberry Pi 1, merging Sovereign theme Sprites11 file with itself (2.2MB file, 358 sprites)
        Old code took 860cs, new code takes 18cs (15cs of which appears to be loading the second copy of the file, judging by *SLoad timings)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_321'
  14. 20 May, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix CPU features being clobbered by software RAM clear · 36bf6e21
      Jeffrey Lee authored
        s/ARMops, s/HAL - Move CPU feature init to after the RAM clear, to prevent the cached values being clobbered on platforms where the HAL doesn't perform the RAM clear
        s/CPUFeatures - Update/clarify comment
        Tested on Raspberry Pi
        Fixes issue spotted by Sprow
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_320'
  15. 19 May, 2016 1 commit
    • Jeffrey Lee's avatar
      Add new OS_PlatformFeatures reason code for reading CPU features (inspired by... · 9944f0f8
      Jeffrey Lee authored
      Add new OS_PlatformFeatures reason code for reading CPU features (inspired by ARMv6+ CPUID scheme). Add OS_ReadSysInfo 8 flags for indicating the alignment mode the ROM was built with. Fix long-standing bug with OS_PlatformFeatures when an unknown reason code is used.
        s/CPUFeatures, hdr/OSMisc, hdr/KernelWS - Code and definitions for reading CPU features and reporting them via OS_PlatformFeatures 34. All the instruction set features which are exposed by the CPUID scheme and which are relevant to RISC OS are exposed, along with a few extra flags which we derive ourselves (e.g. things relating to < ARMv4, and some register usage restrictions in instructions). s/CPUFeatures is designed to be easily copyable into a future version of CallASWI without requiring any changes.
        s/ARMops - Read and cache CPU features during ARMop initialisation
        s/GetAll - GET new file
        s/Kernel - Hook up the CPU features code to OS_PlatformFeatures. Fix a long standing stack imbalance bug (fixed in RISC OS 3.8, but never merged back to our main branch) which meant that calling OS_PlatformFeatures with an invalid reason code would raise an error, even if it was the X form of the SWI that was called. Similar fix also applied to the unused service call code, along with a fix for the user's R1-R9 being corrupt (shuffled up one place) should an error have been generated.
        s/MemInfo - Extra LTORG needed to keep things happy
        s/Middle - Extend OS_ReadSysInfo 8 to include flags for indicating what memory alignment mode (if any) the OS relies upon. Together with OS_PlatformFeatures 34 this could e.g. be used by !CPUSetup to determine which options should be offered to the user.
        Tested on Raspberry Pi 1, 2, 3
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_319'
  16. 08 May, 2016 1 commit
    • Jeffrey Lee's avatar
      Avoid unnecesssary remainder calculations · 53682077
      Jeffrey Lee authored
        s/HeapSort, s/vdu/vdugrafc, s/vdu/vduswis - Avoid unnecessary remainder calculations in DivRem macro
        s/PMF/i2cutils, s/PMF/osword - Make use of DivRem's ability to accept a constant as the divisor
        Tested on Cortex-A15
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_318'
  17. 26 Apr, 2016 1 commit
    • Robert Sprowson's avatar
      Deduce CPUFlag_LongMul/Thumb/DSP from the right bitfields · 280c28ef
      Robert Sprowson authored
      The TST operations for LongMul & Thumb were at odds with the ARM ARM, move those. We can get the DSP flag from an ID register too now, rather than relying on the Q flag being writeable in the PSR.
      Fortunately, the fields we were previously TSTing also had set bits - so the OS_PlatformFeatures 0 flags were coming out right anyway on all real ARMv7's.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_317'
  18. 14 Apr, 2016 2 commits
    • Jeffrey Lee's avatar
      Correction to comment - it's NVRAM, not PortMan · 50a30c72
      Jeffrey Lee authored
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_316'
    • Jeffrey Lee's avatar
      Relax error pointer validity checks some more · 4f06ca80
      Jeffrey Lee authored
        s/Kernel - Some types of error lookup code work by passing a bogus error number into MessageTrans_ErrorLookup and then fixing it up afterwards. To avoid breaking such code, we'll now ignore any bad error numbers from XMessageTrans_ErrorLookup. However obviously bad pointers and the non-X form will still be caught.
        Tested on Raspberry Pi 3
        (e.g.) SWI "XMessageTrans_Lookup","@@@@BadParm" now works
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_315'
  19. 06 Apr, 2016 1 commit
    • Jeffrey Lee's avatar
      Revise error pointer validity checks · 67837a43
      Jeffrey Lee authored
        s/Kernel, hdr/KernelWS - Avoid performing error pointer checks for XOS_GenerateError, since (a) it's a no-op as far as errors are concerned, and (b) many programs take advantage of that fact and abuse the SWI for other purposes (triggering callbacks, BASIC string conversion, etc.)
        Tested on Raspberry Pi
        Fixes issue reported on forums with Sunfish crashing:
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_314'
  20. 05 Apr, 2016 1 commit
    • Jeffrey Lee's avatar
      Add SWI error pointer validation, SeriousErrorV hooks, and OS_ReadSysInfo 15 · b4cf3959
      Jeffrey Lee authored
        Resources/UK/Messages, hdr/KernelWS, s/Kernel - On return from a SWI with V set, do some basic validity checks on the error pointer in order to try and catch buggy SWIs that return bad pointers or invalid error blocks. If a bad pointer is found we'll substitute it with a pointer to a different error block, which has the SWI number in the error message, to allow the user to identify the source of the problem. (There's also a chance we'll crash when investigating a bad pointer, but crashing here in the kernel is preferable to crashing elsewhere because R12 should still contain the SWI number)
        hdr/OSMisc - Define SeriousErrorV reason codes and extended ROM footer entry IDs
        hdr/Options - Remove HangWatch integration flag, obsolete now that SeriousErrorV is available
        s/ArthurSWIs - Keep defaultvectab up to date with vector allocations
        s/Middle - Update serious error handling to call SeriousErrorV at several key points. This allows for accurate crash dumps to be obtained, along with a mechanism to warn low-level components such as RTSupport that the privileged mode stacks are being flattened.
        s/Middle - Add OS_ReadSysInfo 15, for enumerating extended ROM footer entries
        s/PMF/osbyte - Update InitNewFX0Error to use the ROM footer entry ID defined in hdr/OSMisc
        Tested on Pi 1B, 2B, 3B
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_313'
  21. 04 Apr, 2016 1 commit
  22. 27 Mar, 2016 1 commit
    • Jeffrey Lee's avatar
      Improve safety of OS_Memory 0 "make temporarily uncacheable" and *Cache off · 6eee32dd
      Jeffrey Lee authored
        s/MemInfo - Wrap OS_Memory 0 in some code which will temporarily claim the FIQ vector when making pages temporarily uncacheable, to avoid any issues caused by modern ARMs ignoring unexpected cache hits
        s/VMSAv6 - Claim FIQs when OS_MMUControl is asked to make a change to the SCTLR, to avoid similar issues on modern ARMs. Also make the stack temporarily uncacheable before disabling the cache, so that we don't run into any problems using the stack inbetween disabling the cache and completing the clean+invalidate.
        Tested on Pi 2B, 3B
        *Cache off now works reliably on Pi 2B, although there is sometimes a pause of a few seconds while things sort themselves out (USB?)
        *Cache off "works" on Pi 3B but everything will fall over soon afterwards due to the Cortex-A53 not supporting LDREX/STREX to non-cacheable pages (or when the page is effectively non-cacheable, i.e. cacheable page with cache disabled)
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_311'
  23. 25 Mar, 2016 1 commit
    • Jeffrey Lee's avatar
      New HAL device ID reservations · ff04e525
      Jeffrey Lee authored
        hdr/HALDevice - Reserve device IDs for BCM283x CPU clock device and GPU mailbox device
        Tested on Raspberry Pi 1B/2B/3B
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_310'
  24. 17 Mar, 2016 2 commits
  25. 12 Mar, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix crash when making SVC stack uncacheable. Fix poor Pi 3 memory benchmark performance · a941a778
      Jeffrey Lee authored
        s/MemInfo - To avoid cache coherency issues when the current SVC stack page is being made uncacheable, shift SP somewhere else by temporarily dropping into IRQ mode
        s/ARMops - Change default VMSAv6 cache policy to writeback, write allocate. Unlike other CPUs we've supported so far, Cortex-A53 suffers very badly from writes to read-allocate pages, with performance being roughly equivalent to writes to non-cacheable memory. Using a write (+read) allocate policy seems to be needed to get the expected performance, and may help boost other CPUs too.
        Tested on IGEPv5, Pi 3
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_307'
  26. 10 Mar, 2016 1 commit
    • Jeffrey Lee's avatar
      Cache maintenance fixes · b0682acb
      Jeffrey Lee authored
        This set of changes tackles two main issues:
        * Before mapping out a cacheable page or making it uncacheable, the OS performs a cache clean+invalidate op. However this leaves a small window where data may be fetched back into the cache, either accidentally (dodgy interrupt handler) or via agressive prefetch (as allowed for by the architecture). This rogue data can then result in coherency issues once the pages are mapped out or made uncacheable a short time later.
          The fix for this is to make the page uncacheable before performing the cache maintenance (although this isn't ideal, as prior to ARMv7 it's implementation defined whether address-based cache maintenance ops affect uncacheable pages or not - and on ARM11 it seems that they don't, so for that CPU we currently force a full cache clean instead)
        * Modern ARMs generally ignore unexpected cache hits, so there's an interrupt hole in the current OS_Memory 0 "make temporarily uncacheable" implementation where the cache is being flushed after the page has been made uncacheable (consider the case of a page that's being used by an interrupt handler, but the page is being made uncacheable so it can also be used by DMA). As well as affecting ARMv7+ devices this was found to affect XScale (and ARM11, although untested for this issue, would have presumably suffered from the "can't clean uncacheable pages" limitation)
          The fix for this is to disable IRQs around the uncache sequence - however FIQs are currently not being dealt with, so there's still a potential issue there.
        File changes:
        - Docs/HAL/ARMop_API, hdr/KernelWS, hdr/OSMisc - Add new Cache_CleanInvalidateRange ARMop
        - s/ARM600, s/VMSAv6 - BangCam updated to make the page uncacheable prior to flushing the cache. Add GetTempUncache macro to help with calculating the page flags required for making pages uncacheable. Fix abort in OS_MMUControl on Raspberry Pi - MCR-based ISB was resetting ZeroPage pointer to 0
        - s/ARMops - Cache_CleanInvalidateRange implementations. PL310 MMU_ChangingEntry/MMU_ChangingEntries refactored to rely on Cache_CleanInvalidateRange_PL310, which should be a more optimal implementation of the cache cleaning code that was previously in MMU_ChangingEntry_PL310.
        - s/ChangeDyn - Rename FastCDA_UpFront to FastCDA_Bulk, since the cache maintenance is no longer performed upfront. CheckCacheabilityR0ByMinusR2 now becomes RemoveCacheabilityR0ByMinusR2. PMP LogOp implementation refactored quite a bit to perform cache/TLB maintenance after making page table changes instead of before. One flaw with this new implementation is that mapping out large areas of cacheable pages will result in multiple full cache cleans while the old implementation would have (generally) only performed one - a two-pass approach over the page list would be needed to solve this.
        - s/GetAll - Change file ordering so GetTempUncache macro is available earlier
        - s/HAL - ROM decompression changed to do full MMU_Changing instead of MMU_ChangingEntries, to make sure earlier cached data is truly gone from the cache. ClearPhysRAM changed to make page uncacheable before flushing cache.
        - s/MemInfo - OS_Memory 0 interrupt hole fix
        - s/AMBControl/memmap - AMB_movepagesout_L2PT now split into cacheable+non-cacheable variants. Sparse map out operation now does two passes through the page list so that they can all be made uncacheable prior to the cache flush + map out.
        Tested on StrongARM, XScale, ARM11, Cortex-A7, Cortex-A9, Cortex-A15, Cortex-A53
        Appears to fix the major issues plaguing SATA on IGEPv5
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_306'
  27. 29 Feb, 2016 2 commits
    • Jeffrey Lee's avatar
      OS_Memory 13/14/15 fixes · eb908a1e
      Jeffrey Lee authored
        s/HAL - Change RISCOS_AccessPhysicalAddress & RISCOS_ReleasePhysicalAddress (aka OS_Memory 14 & 15) to use the MMU_ChangingUncached ARMop instead of TLB_InvalidateEntry, as on ARMv6+ the MMU version ensures the write has been flushed to be visible by the TLB, while the TLB invalidate call doesn't.
        Fix RISCOS_MapInIO (aka OS_Memory 13) not detecting regions which have already been mapped in due to L1_XN flag masking issue. Also issue DSB+ISB after the page table write(s) to ensure it's visible by the TLB hardware.
        Tested on IGEPv5
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_305'
    • Ben Avison's avatar
      Support for ARMv8 · 66b90f9d
      Ben Avison authored
        * Filled in CPU tables for publicly documented ARMv8 cores (Cortex-A53,57,72).
        * Recent ARM ARMs (e.g. section B1.9.2 of the ARMv7AR ARM) permit the core to
          take an undefined instruction exception upon encountering even not-taken
          conditional undefined instructions. This option is exercised by the
          Cortex-A53, unlike all ARMv7 cores previously supported by RISC OS. This
          unfortunately trips up a lot of kernel code that adapts to different
          architectures at runtime. These have now all been replaced with branches
          over the affected code on the opposite condition.
        * Fixed bug in HAL_InvalidateCache_ARMvF: for the main body of the loop,
          which was written as though to act on the CLIDR register, r8 actually
          contained the CTR register instead.
        Tested on Raspberry Pi 3
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_304'
  28. 28 Feb, 2016 2 commits
    • Robert Sprowson's avatar
      Define some extra platform feature flags · 96546b5a
      Robert Sprowson authored
      For disc based applications (ie. those that don't know the architecture at build time, like a ROM would) we have OS_PlatformFeatures to provide an abstract way of seeing when new chunks of instructions get added. Back at ARMv6 ARM deprecated SWP, but currently we have no way of knowing that at runtime without grubbing round the coprocessor registers.
      Add 3 new flags
      * One to say LDR/STREX is (not) available
      * One to say that SWP/SWPB is (not) available
      * One to say that CLREX and LDR/STREX[B|H|D] is (not) available
      shame it took a few goes for ARM to bring in these variants, requiring 3 flags not 1.
      Condition the exception on vector read code on No32bitCode, rather than just having it permanently disabled.
      Improve the HAL device docs.
      Tested on a StrongARM Risc PC, Model B Pi, and Titanium.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_303'
    • Robert Sprowson's avatar
      Change struct layouts for C module compatibility · d5669ff5
      Robert Sprowson authored
      The HAL device APIs are modelled around the C APCS, and furthermore can be implemented either in a HAL (with SB) or RISC OS module (with R12). Therefore, exporting SB or requiring its use as a function argument precludes implementing the device in a normal module.
      For examples of how to keep track of SB for the HAL case, see AudC or BMU or CPUClk or DMA or GPIO or IDE or Mixer or RTC or SDHCI or CacheC devices, which typically keep it in their HAL workspace referenced relative to the device pointer passed in a1/R0.
  29. 06 Jan, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix a couple of mode specifier/string conversion issues · 4ad692f9
      Jeffrey Lee authored
        s/vdu/vduswis - Fix conversion of mode specifier to mode string so that the X eigen value is only reported in the mode string if it was included in the mode specifier; previously was erroneously basing the decision on whether the Y eigen was specified, resulting in e.g. "EX4294967295" if only the Y eigen was included
        - Fix a stack imbalance causing the conversion of mode string to mode specifier crashing (typically with branch through zero) if an invalid eigen value is specified in the string (e.g. EX-1 as above)
        Tested on Raspberry Pi
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_302'