VMSAv6

; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
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;     http://www.apache.org/licenses/LICENSE-2.0
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; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > hdr:VMSAv6

; ********************
; *** Changes List ***
; ********************

; 18-Feb-09 JL  Created, using ARM600 as basis.

; Access privilege bits
; These comprise the AP and APX bits, which are luckily always in the same location relative to each other

AP_ROM  *       2_100010        ; user read-only,  svc read-only
AP_None *       2_000001        ; user no access,  svc read/write
AP_Read *       2_000010        ; user read-only,  svc read/write
AP_Full *       2_000011        ; user read/write, svc read/write

L1_APShift *     10        ; value to shift AP_ values by for L1 entry
L2_APShift *     4         ; value to shift AP_ values by for L2 entry

L1_APMult  * 1 :SHL: L1_APShift  ; value to multiply AP_ values by for L1 entry
L2_APMult  * 1 :SHL: L2_APShift  ; value to multiply AP_ values by for L2 entry
L2X_APMult * L2_APMult

L1_AP     *     2_100011 * L1_APMult ; masks for AP fields
L2_AP     *     2_100011 * L2_APMult

L1_DomainShift *   5            ; lowest bit position in L1 entry for domain number

L1_Fault *      4_0             ; translation fault specifier in L1 entry
L1_Page *       4_1             ; coarse page specifier in L1 entry
L1_Section *    4_2             ; section specifier in L1 entry
; supersections not supported ATM


L2_Fault *      4_0             ; translation fault specifier in L2 entry
L2_LargePage *  4_1             ; large page specifier in L2 entry
L2_SmallPage *  4_2             ; (extended) small page specifier in L2 entry
L2_ExtPage   *  L2_SmallPage

L1_TEXShift *   12
L1_TEX  *       2_111 :SHL: 12  ; Type Extension bits
L1_C    *       1 :SHL: 3       ; cacheable
L1_B    *       1 :SHL: 2       ; bufferable
L1_nG   *       1 :SHL: 17      ; 1=entry associated with ASID, 0=global
L1_XN   *       1 :SHL: 4       ; eXecute Never
L1_X    *       1 :SHL: 12      ; XScale - modifies meaning of C and B bits (is TEX bit 0)

L2L_TEXShift *  12              ; For large pages
L2_TEXShift *   6               ; For extended small pages
L2L_TEX *       2_111 :SHL: 12  ; Type Extension bits (large pages)
L2_TEX  *       2_111 :SHL: 6   ; Type Extension bits (tiny and extended pages)
L2_C    *       1 :SHL: 3       ; cacheable  bit in level 2 entry
L2_B    *       1 :SHL: 2       ; bufferable --------""----------
L2_nG   *       1 :SHL: 11      ; 1=entry associated with ASID, 0=global
L2L_XN  *       1 :SHL: 15      ; eXecute Never for large pages
L2_XN   *       1               ; eXecute Never for extended small pages
L2L_X   *       1 :SHL: 12      ; XScale - modifies meaning of C and B bits (large pages) (is TEX bit 0)
L2_X    *       1 :SHL: 6       ; XScale - modifies meaning of C and B bits (tiny and extended pages) (is TEX bit 0)

; CP15 control register bits
; Retaining MMUC_* naming for compatability with existing code

; Validity: 5 = ARMv5 or older, 6=ARMv6, K=ARMv6K, 7=ARMv7, !=Warning, bit reused
MMUC_M  *  1 :SHL: 0  ; 567 MMU enable
MMUC_A  *  1 :SHL: 1  ; 567 Alignment fault enable
MMUC_C  *  1 :SHL: 2  ; 567 Cache enable (or Data cache enable)
MMUC_W  *  1 :SHL: 3  ; 56  Write buffer enable
MMUC_P  *  1 :SHL: 4  ; 5   32-bit program space enable
MMUC_D  *  1 :SHL: 5  ; 5   32-bit data space enable
MMUC_L  *  1 :SHL: 6  ; 5   Late abort mode enable
MMUC_B  *  1 :SHL: 7  ; 56  Big-endian mode enable
MMUC_S  *  1 :SHL: 8  ; 5   S-mode enable
MMUC_R  *  1 :SHL: 9  ; 5   R-mode enable (ARM7 or later)
MMUC_F  *  1 :SHL: 10 ; 5!! Coprocessor frequency bit (ARM700 only)
MMUC_SW *  1 :SHL: 10 ; !!7 SWP/SWPB enable (ARMv7MP)
MMUC_Z  *  1 :SHL: 11 ; 567 Branch predictor enable
MMUC_I  *  1 :SHL: 12 ; 567 Instruction cache enable
MMUC_V  *  1 :SHL: 13 ; 567 High exception vectors
MMUC_RR *  1 :SHL: 14 ; 567 Round-robin/alternate cache replacement strategy
MMUC_L4 *  1 :SHL: 15 ; 56  Disable ARMv5 "load Thumb state with PC" behaviour
MMUC_HA *  1 :SHL: 17 ;  K7 Hardware access flag enable
MMUC_FI *  1 :SHL: 21 ;  67 Fast interrupt configuration enable
MMUC_U  *  1 :SHL: 22 ;  6  Unaligned data access operation
MMUC_XP *  1 :SHL: 23 ;  6  Extended page table config
MMUC_VE *  1 :SHL: 24 ;  6  Vectored interrupts
MMUC_EE *  1 :SHL: 25 ;  67 Exception Endian bit
MMUC_L2 *  1 :SHL: 26 ;  6  L2 unified cache enable
MMUC_NMFI * 1:SHL: 27 ;  67 Non-maskable FIQ (read-only)
MMUC_TRE * 1 :SHL: 28 ;  K7 TEX remap enable
MMUC_AFE * 1 :SHL: 29 ;  K7 Access Flag Enable (AP[0] remap)
MMUC_nF *  1 :SHL: 30 ; 5!! not FastBus (ie separate CPUCLK from MEMCLK)
MMUC_TE *  1 :SHL: 30 ; !67 Exceptions handled in Thumb mode
MMUC_iA *  1 :SHL: 31 ; 5   Asynchronous

; ARM600 MMU coprocessor number

Arm600Cop CP      15

; ARM600 coprocessor registers

CR_Dummy        CN      0
CR_ID           CN      0       ; read-only
CR_Control      CN      1       ; read/write
CR_TTabBase     CN      2       ; read/write
CR_Domains      CN      3       ; read/write
CR_FaultStatus  CN      5       ; read
CR_FaultAddress CN      6       ; read

; Cache type register fields
; NOTE - need to be kept in sync with hdr.MEMM.ARM600!

CT_ctype_pos    *       25
CT_ctype_mask   *       &F:SHL:CT_ctype_pos
CT_S_pos        *       24
CT_S            *       1:SHL:CT_S_pos
CT_Dsize_pos    *       12
CT_Dsize_mask   *       &FFF:SHL:CT_Dsize_pos
CT_Isize_pos    *       0
CT_Isize_mask   *       &FFF:SHL:CT_Isize_pos

CT_ctype_WT     *       0       ; write-through cache
CT_ctype_WB_Crd *       1       ; write-back, clean by reading data
CT_ctype_WB_CR7 *       2       ; write-back, clean with register 7
CT_ctype_WB_Cal_LD  *   5	; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDa *   6       ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb *   7       ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx *  8       ; write-back, clean with register 7, multiple cache levels

CT_size_pos     *       6
CT_size_mask    *       7:SHL:CT_size_pos
CT_assoc_pos    *       3
CT_assoc_mask   *       7:SHL:CT_assoc_pos
CT_M_pos        *       2
CT_M            *       1:SHL:CT_M_pos
CT_len_pos      *       0
CT_len_mask     *       3:SHL:CT_len_pos

CT_size_512     *       0
CT_size_1K      *       1
CT_size_2K      *       2
CT_size_4K      *       3
CT_size_8K      *       4
CT_size_16K     *       5
CT_size_32K     *       6
CT_size_64K     *       7
CT_size_768     *       0
CT_size_1536    *       1
CT_size_3K      *       2
CT_size_6K      *       3
CT_size_12K     *       4
CT_size_24K     *       5
CT_size_48K     *       6
CT_size_96K     *       7

CT_assoc_1      *       0
CT_assoc_2      *       1
CT_assoc_4      *       2
CT_assoc_8      *       3
CT_assoc_16     *       4
CT_assoc_32     *       5
CT_assoc_64     *       6
CT_assoc_128    *       7
CT_assoc_0      *       0
CT_assoc_3      *       1
CT_assoc_6      *       2
CT_assoc_12     *       3
CT_assoc_24     *       4
CT_assoc_48     *       5
CT_assoc_96     *       6
CT_assoc_192    *       7

CT_len_2        *       0
CT_len_4        *       1
CT_len_8        *       2
CT_len_16       *       3

CT_M_512        *       0
CT_M_1K         *       0
CT_M_2K         *       0
CT_M_4K         *       0
CT_M_8K         *       0
CT_M_16K        *       0
CT_M_32K        *       0
CT_M_64K        *       0
CT_M_768        *       1
CT_M_1536       *       1
CT_M_3K         *       1
CT_M_6K         *       1
CT_M_12K        *       1
CT_M_24K        *       1
CT_M_48K        *       1
CT_M_96K        *       1



        MACRO
        SetCop  $reg, $cop, $rm, $op2, $cc
      [ "$op2" = ""
        MCR$cc  Arm600Cop, 0, $reg, $cop, CR_Dummy
      |
        MCR$cc  Arm600Cop, 0, $reg, $cop, $rm, $op2
      ]
        MEND

        MACRO
        ReadCop $reg, $cop, $rm, $op2, $cc
      [ "$op2" = ""
        MRC$cc  Arm600Cop, 0, $reg, $cop, CR_Dummy
      |
        MRC$cc  Arm600Cop, 0, $reg, $cop, $rm, $op2
      ]
        MEND


        END