GitLab

Detail:
  MACFROMNVRAM was intended to force the Kernel to fetch the MAC
  address from NVRAM for Customer F 5. In practice it is not needed
  as its main purpose was to avoid getting the MAC address from
  the RawMachineID but this will not happen in Customer F 5 as
  RawMachineID will not be set.

Admin:
  Not tested.
  MACFROMNVRAM will be removed from HdrSrc.

Version 5.17. Tagged as 'Kernel-5_17'

  Ensured that M_Phoebe builds set UtilityModule version to 4.00
Detail:
  The softload utility relies on the existence of the extra reason codes
    to OS_ReadSysInfo introduced in Ursula.  The main kernel now supports
    these too (they are simply interfaces to read kernel capabilities and
    configuration - eg. addresses and sizes of UND and SVC mode stacks)
  Avoid OS_ReadSysInfo 9 - ROL have used it for reading the ROM personality
    information (and it's not in our kernel)
  Added some of the new macros into Copro15ops required by the ABT dump
    area code (returned by OS_ReadSysInfo 7) and added the code into ARM600
    to store abort information there.
Admin:
  Required by softload utility for Ursula builds.
  Tested on Risc PC.

Version 5.15. Tagged as 'Kernel-5_15'

  MACFROMNVRAM is set. This is set in HdrSrc for Customer F machines.

Detail:
  If MACFROMNVRAM is TRUE then OS_ReadSysInfo 4 will read the Ethernet MAC
  Address from bytes 0-13 of the NVRAM area, instead of trying to read it
  from anywhere else. (14 bytes are ysed to store 2 copies and 2
  checksums).

  This is intended for use with a 24LC128 device (which has no OTP area
  and no clock).

  Note that these are physical addresses within the device. Logical
  addresses &F0-&FF map to physical addresses &00-&0F.

  A SetMac utility is provided in Customer F 5 !Boot.Utils to enable the MAC
  address to be programmed for prototypes and development machines.

  Since it is dangerous to rely on the NVRAM to hold our MAC address when
  it is not protected in any way, we store two copies of it, each with
  their own checksum. At present only the first copy is used, but the
  plan is to check both copies and both checksums.

Admin:
  This version of the Kernel needs Programmer/HdrSrc v0.68 or later.

  If MACFROMNVRAM is enabled, ensure that the MACADDRESS tag in the
  NVRAM file is set to point at &F0 and that MACADDRESSCHECKSUM
  is set to point at &F6. Both should have options L and P to ensure
  they are protected from NVRAM resets and other writes.

Version 5.09. Tagged as 'Kernel-5_09'

OS_ReadSysInfo 2 now reports whether the IIC bus is fast (in bit 24 of R2), and whether I/O clocks should be stopped when idling the processor (bit 25).

OS_Byte 19 is a bit more careful in its use of Portable_Idle - an edge case
where the vsync interrupt was already pending now returns immediately.

Version 5.07. Tagged as 'Kernel-5_07'

If reassigned, ReadSysInfo3 returns &00x22200 in R0, to indicate that the
serial and parallel ports aren't compatible, and IDE and floppy are
unavailable.

Version 5.01. Tagged as 'Kernel-5_01'

This has been fixed. In addition, SMC669 and UMC669 chips are reported as
a different chip configuration by OS_ReadSysInfo 3 (values 4 and 5
respectively).
A few assertions added to catch the remaining cases where the RCMM stuff
won't work - those cases will involve a bit more reordering of hardware
initialisation.

Version 5.00. Tagged as 'Kernel-5_00'

ROM speed not taken from the Machine header file.  POST can now exist in a softloaded OS, since it searches for a zero word in the ROM instead of using one within the POST when trying to communicate with the POST adapter (the zero word must be in ROM).  Fixed to build on non-chrontel STB/NC products.  Lots of duplicate code merged in

MemSize.  MemSize copes better with the softload case, and is less
willing to use the region the OS occupies as video memory, or
page tables.  POST is now ON (memory tests disabled).
OS_ReadSysInfo 4 now uses the NVRAM module to access the ethernet
address in NVRAM/CMOS, so that the availability/location of the
MAC address can be changed.  CMOS location 0 is now unprotected on
STB/NC products to try to stop people poking the hardware directly.
Fixed a CMOS resetting problem on STBs where the value expected in a
location was different from the value written on a CMOS reset, so the
CMOS would be reset every time...

Version 4.69. Tagged as 'Kernel-4_69'

Not fully tested on all hardware permutations.