1. 06 Oct, 2000 1 commit
  2. 05 Oct, 2000 2 commits
    • Dan Ellis's avatar
      Added HAL NVRAM support · a89c776b
      Dan Ellis authored
      Detail:
        Added the HAL NVRAM entries.
        Modified i2cutils to use the HAL entries for NVRAM and behave sensibly if the HAL reports that there is no NVRAM, in which case there must be a forced reset_cmos call so that the cache gets set up sensibly.
      Admin:
        Tested under the RPC emulator and appears to be working correctly, although some calls to IIC are still being made in the no nvram case.
      
      Version 5.35, 4.79.2.8. Tagged as 'Kernel-5_35-4_79_2_8'
      a89c776b
    • Kevin Bracey's avatar
      More HAL work. IOMD HAL fleshed out somewhat - system gets most of the way through initialisation. · a18a8de5
      Kevin Bracey authored
      Version 5.35, 4.79.2.5. Tagged as 'Kernel-5_35-4_79_2_5'
      a18a8de5
  3. 02 Oct, 2000 1 commit
  4. 15 Sep, 2000 1 commit
    • Kevin Bracey's avatar
      * Converted to building with ObjAsm (but still a single object file using ORG). · 49836a59
      Kevin Bracey authored
      * Added ARM_IMB and ARM_IMBRange SWIs as recommended by ARMv5.
      * Some early prototype HAL bits popped in - a lot of source restructuring still
        to come.
      * New debug target creates an AIF image with debug information, and translates
        this into an ASCII object file for the 16702B logic analyser.
      
      Version 5.35, 4.79.2.1. Tagged as 'Kernel-5_35-4_79_2_1'
      49836a59
  5. 15 Aug, 2000 1 commit
    • Stewart Brodie's avatar
      Fixed minor bug in module initialisation. · efd9b01e
      Stewart Brodie authored
        Added common error cache.
      Detail:
        Fixed module header validation code which was broken in 5.22.  This
          shouldn't have caused much of a problem as it was only a bizarre
          check (SWI chunk looked valid but SWI handler was 0) that would
          have failed - but be reported as a valid set of SWI entries.
        Added common error message cache.  Several common errors (Buffer
          overflow; Number not recognised; Bad vector release; and a couple
          of others) are now cached the first time they are translated into
          a block of memory in the system heap.
      Admin:
        Tested in Ursula build - cacheing only active in Ursula build - change
          HdrSrc if you want it in your products too.
        Requires HdrSrc 0.94
      
      Version 5.31. Tagged as 'Kernel-5_31'
      efd9b01e
  6. 08 May, 2000 1 commit
    • Simon Forrest's avatar
      * Kernel failed to assemble on Lazarus builds. Single instruction change should cure this. · 8fd9657d
      Simon Forrest authored
      Detail:
      
        * Lazarus builds of the Kernel failed with the following error:
      
            Immediate value out of range at line 458 in file "s.NewReset"
                    ADR    R2, IRQ_Test_CTRL_or_R_Pressed
      
          This is due to the ADR going out of range.  Changed to use ADDR
          macro instead to rectify this.
      
      Admin:
      
        * Untested at time of check-in; to be verified in next Lazarus development
          build.
      
      Version 5.25. Tagged as 'Kernel-5_25'
      8fd9657d
  7. 13 Apr, 2000 1 commit
    • Kevin Bracey's avatar
      * Run-time emulator detection added (no need for separate images). Needs an · 36ba4cb5
      Kevin Bracey authored
        RPCEm update.
      * Register allocation in default ErrorV handler fixed - problems occured when
        callbacks were triggered on way out.
      * OS_Byte 19 didn't manipulate interrupt disable flag correctly in 26-bit
        builds.
      * Stray bit of debugging left in sprite code many years ago removed.
      
      Version 5.23. Not tagged
      36ba4cb5
  8. 04 Apr, 2000 1 commit
    • Kevin Bracey's avatar
      32-bit Kernel. · b4016e9c
      Kevin Bracey authored
      Details:
        The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
        set to TRUE.
        If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
        although some internal changes have taken place to minimise compile
        switches between the two cases. See Docs.32bit for more technical info.
      
        The hardest part was the flood-fill...
      
      Other changes:
        Pointer shape changes now take place on the next VSync, rather than actually
        WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
        down by 5% now :)
      
        Lots of really crusty pre-IOMD code removed.
      
      Admin:
        Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
        will need to see a lot of use to iron out difficulties. I'd like anyone who
        has a non-frozen project to at least attempt using this Kernel.
      
      Version 5.23. Tagged as 'Kernel-5_23'
      b4016e9c
  9. 29 Oct, 1999 1 commit
  10. 18 Oct, 1999 1 commit
  11. 29 Sep, 1999 1 commit
    • Kevin Bracey's avatar
      * Meaning of FEIOSpeedHalf was accidentally inverted. · fb297c9b
      Kevin Bracey authored
      * Wasn't allowing writes to most of EEPROM.
      * Old prototype OS_SetTime SWI code removed.
      * MPEGPoduleNTSCNotPALMask option support removed to simplify things a bit.
      * Now can cope with a system with a PAL/NTSC link, but no monitor detect line.
      * Default PAL & NTSC modes now always 12 & 46 respectively.
      * Kernel now knows about monitor type 8 (NTSC) - modes 44-46 (640x200) are
        available.
      * STB/NC CMOS test removed from POST pending further investigation.
      
      Version 4.90. Tagged as 'Kernel-4_90'
      fb297c9b
  12. 16 Sep, 1999 1 commit
    • Kevin Bracey's avatar
      Default RCLK mode now RCLK/2 rather than RCLK/1. · b28fe2e3
      Kevin Bracey authored
      Doesn't force CMOS setting of sync and monitortype on NCs/STBs.
      Accepts HClockSelect parameter (number 9) in VIDC lists. Uses this to
      determine whether to use HCLK or not, rather than abusing
      Service_MonitorLeadTranslation.
      If DontUseVCO flag is set, then VCLK will not be used - only RCLK (or HCLK if
      requested).
      
      Version 4.86. Tagged as 'Kernel-4_86'
      b28fe2e3
  13. 25 Feb, 1999 1 commit
  14. 09 Feb, 1999 1 commit
    • Neil Turton's avatar
      ROM speed not taken from the Machine header file. POST can now exist in a... · 417410eb
      Neil Turton authored
      ROM speed not taken from the Machine header file.  POST can now exist in a softloaded OS, since it searches for a zero word in the ROM instead of using one within the POST when trying to communicate with the POST adapter (the zero word must be in ROM).  Fixed to build on non-chrontel STB/NC products.  Lots of duplicate code merged in
      
      MemSize.  MemSize copes better with the softload case, and is less
      willing to use the region the OS occupies as video memory, or
      page tables.  POST is now ON (memory tests disabled).
      OS_ReadSysInfo 4 now uses the NVRAM module to access the ethernet
      address in NVRAM/CMOS, so that the availability/location of the
      MAC address can be changed.  CMOS location 0 is now unprotected on
      STB/NC products to try to stop people poking the hardware directly.
      Fixed a CMOS resetting problem on STBs where the value expected in a
      location was different from the value written on a CMOS reset, so the
      CMOS would be reset every time...
      
      Version 4.69. Tagged as 'Kernel-4_69'
      417410eb
  15. 30 Oct, 1998 1 commit
    • Kevin Bracey's avatar
      OS_Byte 129 0 255 now reports &A7 for STB build (because it _is_ a · 2392dd15
      Kevin Bracey authored
      RISC OS 3.7 generation kernel).
      CMOS no longer gets scrambled when reset in STB build.
      UpCall_KeyboardStatus now issued when OS_Byte 202 called or when keyboard
      status byte is changed by other means (such as pressing Caps Lock).
      
      Version 4.67. Tagged as 'Kernel-4_67'
      2392dd15
  16. 01 Oct, 1998 1 commit
    • Kevin Bracey's avatar
      Following changes folded in from the start of the Ursula branch: · 4a34da4f
      Kevin Bracey authored
      CPU type messages internationalised.
      "Unknown OS_PlatformFeatures reason code" internationalised.
      RunningOnEmul flag tweaked.
      MorrisIDString conditional removed.
      New modules added to SWI list at the end of the chain, on grounds that
      the first-registered modules are probably more important.
      *ChangeDynamicArea moved into UtilityModule from TaskManager.
      
      Version 4.65. Tagged as 'Kernel-4_65'
      4a34da4f
  17. 30 Sep, 1998 1 commit
    • Kevin Bracey's avatar
      Spinner branch merged. · 5ba3f5db
      Kevin Bracey authored
      Bandwidth limit for 7500FE fixed.
      RO371Timings flag set to :LNOT:STB
      
      Version 4.64. Tagged as 'Kernel-4_64'
      5ba3f5db
  18. 07 May, 1997 1 commit
  19. 01 May, 1997 1 commit
  20. 21 Jan, 1997 1 commit
  21. 21 Nov, 1996 1 commit
  22. 06 Nov, 1996 1 commit
  23. 05 Nov, 1996 1 commit