* Run-time emulator detection added (no need for separate images). Needs an

  RPCEm update.
* Register allocation in default ErrorV handler fixed - problems occured when
  callbacks were triggered on way out.
* OS_Byte 19 didn't manipulate interrupt disable flag correctly in 26-bit
  builds.
* Stray bit of debugging left in sprite code many years ago removed.

Version 5.23. Not tagged

VersionASM

@@ -9,6 +9,6 @@
 Module_MajorVersion     SETS    "5.23"
 Module_Version          SETA    523
 Module_MinorVersion     SETS    ""
-Module_Date             SETS    "04 Apr 2000"
+Module_Date             SETS    "13 Apr 2000"
 Module_FullVersion      SETS    "5.23"
                         END

VersionNum

@@ -5,11 +5,11 @@
  */
 #define Module_MajorVersion_CMHG        5.23
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                04 Apr 2000
+#define Module_Date_CMHG                13 Apr 2000
 
 #define Module_MajorVersion             "5.23"
 #define Module_Version                  523
 #define Module_MinorVersion             ""
-#define Module_Date                     "04 Apr 2000"
+#define Module_Date                     "13 Apr 2000"
 
 #define Module_FullVersion              "5.23"

s/ARM600

@@ -695,7 +695,10 @@ ClearPhysRAMspeedup SETL {TRUE}
 
 ClearPhysRAM ROUT
 
-    [ :LNOT: RunningOnEmul
+      [ EmulatorSupport
+        ARM_on_emulator r0
+        BEQ     CPR_skipped
+      ]
 
 ;StrongARM - We will make the logical representation of physical space for RAM temporarily bufferable
 ;            (on any ARM). This is small boost for ARM 6,7,8 but a big speed benefit for StrongARM (which
@@ -799,7 +802,7 @@ ClearPhysRAM ROUT
         TEQ     r12, r4                                 ; have we done all areas?
         BNE     %BT32
 
-    ] ;RunningOnEmul
+CPR_skipped
 
         LDR     r0, =OsbyteVars + :INDEX: LastBREAK
 

s/Copro15ops

@@ -121,6 +121,16 @@ C15 CN 15
         MOV      $num,$num,LSR #12
         MEND
 
+;check whether running on emulator - this is subject to change. ARMs before
+;ARM 920 ignore op2, and will definitely return something other than "1".
+;ARM 920 onwards use op2 0 and 1 - behaviour with other op2 values is as yet
+;unknown...
+        MACRO
+        ARM_on_emulator $tmp
+        MRC     ARM_config_cp,0,$tmp,ARM_ID_reg,C0,7
+        TEQ     $tmp,#1
+        MEND
+
 ;flush whole TLB (both data and instruction for StrongARM)
 ;trashes $temp
         MACRO

s/GetAll

@@ -40,10 +40,6 @@
 ; Using the STB switch this aggressively also help ensure that there's
 ; no unexpected code crossover in the initial merge.
 
-;whether compiling to run on (Risc PC) emulator
-                GBLL    RunningOnEmul
-RunningOnEmul   SETL    {FALSE}
-
 ; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 ; now the conditional flags for the version we want
 ; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -96,10 +92,6 @@ IncludeTestSrc  SETL    {TRUE}
 IncludeTestSrc  SETL    :LNOT: (MEMM_Type = "MEMC2") ; not on internal test versions
  ]
 
- [ RunningOnEmul
-IncludeTestSrc  SETL    {FALSE} :LAND: :LNOT: STB
- ]
-
 ;RISC OS 3.71 onwards assumed bus timings - if true, then ROM speeds atc are assumed according to IOMD ID regs. as follows:
 ;     if IOMD (Risc PC)     ROM ticks 5-3 (assumed bus 32 MHz)
 ;     if 7500 (A7000)       ROM ticks 5-3 (assumed bus 32 MHz), all clocks divide-by-1
@@ -112,6 +104,10 @@ RO371Timings    SETL    :LNOT: STB
                 GBLL    ParallelFlashUpgrade
 ParallelFlashUpgrade SETL {FALSE}
 
+;whether we support running on the (Risc PC) emulator
+                GBLL    EmulatorSupport
+EmulatorSupport SETL    {TRUE}
+
   [ :LNOT: RO371Timings
 
                 GBLL    NormalSpeedROMS

s/Kernel

@@ -695,8 +695,8 @@ ErrHandler ROUT
 
         BL      OscliTidy               ; close redirection, restore curr FS
 
-        MOV     r12, #0
-        LDR     r11, [r12, #ErrBuf]     ; Get pointer to error buffer
+        MOV     r10, #0
+        LDR     r11, [r10, #ErrBuf]     ; Get pointer to error buffer
 
   [ No26bitCode
         LDR     sp_svc, =SVCSTK-4*4     ; Just below top of stack
@@ -705,7 +705,7 @@ ErrHandler ROUT
   |
         LDR     sp_svc, =SVCSTK-5*4     ; Just below top of stack
         Pull    r14                     ; PSR will be on stack if error at top level
-        FakeLR  r10                     ; Fake up the PC+PSR
+        FakeLR  r12                     ; Fake up the PC+PSR
         STR     r14, [r11], #4
   ]
 
@@ -713,38 +713,38 @@ ErrHandler ROUT
         STR     r14, [r11], #4
 
         ; Copy error string - truncating at 252
-        MOV     r10, #256-4
+        MOV     r12, #256-4
 
 10      LDRB    r14, [r0], #1
-        SUBS    r10, r10, #1
+        SUBS    r12, r12, #1
         MOVLS   r14, #0
         STRB    r14, [r11], #1
         TEQ     r14, #0
         BNE     %BT10
 
-        LDR     r14, [r12, #ErrHan]     ; And go to error handler
+        LDR     r14, [r10, #ErrHan]     ; And go to error handler
   [ :LNOT: No26bitCode
         BIC     r14, r14, #ARM_CC_Mask
   ]
-        STR     r14, [r12, #Curr_Active_Object]
-        LDR     r0,  [r12, #ErrHan_ws]  ; r0 is his wp
+        STR     r14, [r10, #Curr_Active_Object]
+        LDR     r0,  [r10, #ErrHan_ws]  ; r0 is his wp
 
-        LDRB    r10, [r12, #CallBack_Flag]
-        CMP     r10, #0
+        LDRB    r11, [r10, #CallBack_Flag]
+        CMP     r11, #0
 
-        mrs    ,r10, CPSR
-        BIC     r10, r10, #I32_bit+F32_bit+&0F  ; USR26/32 mode, ARM, IRQs enabled
+        mrs    ,r12, CPSR
+        BIC     r12, r12, #I32_bit+F32_bit+&0F  ; USR26/32 mode, ARM, IRQs enabled
 
   [ :LNOT: NoSPSRcorruption
         msr EQ, CPSR_c, #I32_bit+SVC32_mode ; disable interrupts for SPSR use
   ]
-        msr     EQ, SPSR_cxsf, r10
+        msr EQ, SPSR_cxsf, r12
 
         Pull    "r10-r12", EQ
         MOVEQS  pc, r14                 ; USR mode, IRQs enabled
 
         Push    r14                     ; Stack return address
-        MOV     r14, r10                ; Put PSR in R14
+        MOV     r14, r12                ; Put PSR in R14
         B       Do_CallBack             ; Can't need postponement, r0,r14,stack
                                         ; such that callback code will normally
                                         ; call error handler

s/NewReset

@@ -427,9 +427,11 @@ vcofix_notMorris
         MOV     R13, R1                 ; R13 is now the RAM size
         MOV     R9, R2                  ; need this to set soft copy right
 
-   [ RunningOnEmul :LAND: :LNOT: STB
-        MOV     R7,#&80
-        ORR     R7,R7,#&3E00            ; r7 := &3E80 = 16000 (standard Risc PC value)
+   [ EmulatorSupport
+        ARM_on_emulator R7
+        MOVEQ   R7,#&80
+        ORREQ   R7,R7,#&3E00            ; r7 := &3E80 = 16000 (standard Risc PC value)
+        BLNE    TimeCPU                 ; r7 := CPU speed in kHz/MEMC1a flag
    |
         BL      TimeCPU                 ; r7 := CPU speed in kHz/MEMC1a flag
    ]
@@ -680,11 +682,7 @@ afterpokingaround_notSA
         MOV     R1, #32*1024*1024       ; nothing will be here!!
         STR     R1, [R0, #Curr_Active_Object]
 
-    [ RunningOnEmul :LAND: :LNOT: STB
-KeyWait *       1
-    |
 KeyWait * 200000                 ; 1/5 sec wait (in microseconds)
-    ]
 
     [ KeyWait <> 0
 ; Check for keyboard there every 1/5 sec. but give up after 2 secs.
@@ -693,7 +691,13 @@ KeyWait * 200000                 ; 1/5 sec wait (in microseconds)
         MOV     r4, #InitKbdWs
 kbdwait
         LDRB    r5, [r4, #KB_There_Flag]
+      [ EmulatorSupport
+        ARM_on_emulator r0
+        MOVEQ   r0, #2
+        LDRNE   r0, =KeyWait*2          ; Wait 1/5 second (give keys down a chance to come in).
+      |
         LDR     r0, =KeyWait*2          ; Wait 1/5 second (give keys down a chance to come in).
+      ]
         BL      DoMicroDelay
         TEQ     r5, #0                  ; If keyboard was there 1/5 second ago then
         BNE     kbdthere                ;   continue reset
@@ -1918,8 +1922,10 @@ SkipHardResetPart2                      ; code executed on all types of reset
 
         MOV     r3, #0
         LDR     r3, [r3, #MetroGnome]
- [ RunningOnEmul :LAND: :LNOT: STB
-        ADD     r3,r3,#1
+ [ EmulatorSupport
+        ARM_on_emulator r0
+        ADDEQ   r3, r3, #1
+        ADDNE   r3, r3, #10             ; Hang about for a little while
  |
         ADD     r3, r3, #10             ; Hang about for a little while
  ]
@@ -2155,9 +2161,11 @@ Hortoculture_Kicking
 
         MOV     r3, #0
         LDR     r3, [r3, #MetroGnome]
- [ RunningOnEmul :LAND: :LNOT: STB
-        ADD     r3,r3,#1
-        |
+ [ EmulatorSupport
+        ARM_on_emulator r1
+        ADDEQ   r3, r3, #1
+        ADDNE   r3, r3, #10             ; Hang about for a little while
+ |
         ADD     r3, r3, #10             ; Hang about for a little while
  ]
 

s/PMF/osbyte

@@ -621,7 +621,7 @@ Osbyte12 ROUT
 
 Osbyte13 ROUT
 
-        SavePSR R3                      ; Interrupts disabled at the moment
+        mrs    ,R3, CPSR                ; Interrupts disabled at the moment
 
         ; bug fix for MED-03165. Having a DPMS-blanked screen stopped printing.
         ; The reason is that HSyncs stop and VSyncs stop as a consequence,
@@ -654,13 +654,13 @@ Osbyte13 ROUT
         NOP
         NOP
  ]
-        RestPSR R3                      ; SEI
+        msr    ,CPSR_c, R3              ; SEI
         LDRB    R1, CFStime
         TEQ     R1, R2
         MyOsbyte NE
 
  [ StorkPowerSave
-; It is actually better to call Idle with interrupts disabled as it stops us the interrupt
+; It is actually better to call Idle with interrupts disabled as it stops the interrupt
 ; going off on the way through the SWI dispatch and accidentally waiting for the next
 ; interrupt... The Idle will return when an interrupt is pending - it will be handled when
 ; we branch back up and enable interrupts.

s/vdu/vdugrafi

@@ -219,13 +219,6 @@ FlipAboutYAxis ROUT
 
         MOV     R11, #1
         MOV     R9, #1
-;**************
-        Push    R0
-        MOV     R0, #&6000
-        STR     R9, [R0]
-        STR     R11, [R0, #4]
-        Pull    R0
-;**************
 
         MOV     R10, R9, ROR R11                ; mask for rightmost pixel