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Support supersection-mapped memory in OS_Memory 24
Ben Avison authored 
To achieve this:
* DecodeL1Entry and DecodeL2Entry return 64-bit physical addresses in
  r0 and r1, with additional return values shuffled up to r2 and r3
* DecodeL1Entry now returns the section size, so callers can distinguish
  section- from supersection-mapped memory
* PhysAddrToPageNo now accepts a 64-bit address (though since the physical
  RAM table is currently still all 32-bit, it will report any top-word-set
  addresses as being not in RAM)

Version 6.22. Tagged as 'Kernel-6_22'
bd294cf9
Name Last commit Last update
Dev Delete lots of old switches
Doc Kernel merged
Docs Support temporary mapping of IO above 4GB using supersections
Resources/UK Add support for shareable pages and additional access privileges
TestSrc Delete pre-HAL and 26bit code
h Header defs for Pi Compute module and IIC
hdr Support temporary mapping of IO above 4GB using supersections
o Clean reimport of hdr.RISCOS (real commit date 2008-03-28 by bavison), without any of the 3rd party allocations.
rm Clean reimport of hdr.RISCOS (real commit date 2008-03-28 by bavison), without any of the 3rd party allocations.
s Support supersection-mapped memory in OS_Memory 24
.gitattributes Added 'UnConv' error (see also HdrSrc).
BlackLog Initial revision
Changes Import from cleaned 360 CD
HelpStrs Adoption of *CONFIGURE/STATUS CACHE commands
LICENSE Clean reimport of hdr.RISCOS (real commit date 2008-03-28 by bavison), without any of the 3rd party allocations.
Makefile Merge in latest changes from main branch
MkClean,fd7 Mostly device stuff.
MkExport,fd7 Import from cleaned 360 CD
MkInstall,fd7 Added a disc install phase as an analogue of the export phase
MkRom,fd7 Makefile recreated from fragments
Version Nightly beta builds leapfrog RISC OS 5.26
VersionASM Support supersection-mapped memory in OS_Memory 24
VersionNum Support supersection-mapped memory in OS_Memory 24