Commit f655fcf6 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Delete lots of old switches

Detail:
  This change gets rid of the following switches from the source (picking appropriate code paths for a 32bit HAL build):
  * FixCallBacks
  * UseProcessTransfer
  * CanLiveOnROMCard
  * BleedinDaveBell
  * NewStyleEcfs
  * DoVdu23_0_12
  * LCDPowerCtrl
  * HostVdu
  * Print
  * EmulatorSupport
  * TubeInfo
  * AddTubeBashers
  * TubeChar, TubeString, TubeDumpNoStack, TubeNewlNoStack macros
  * FIQDebug
  * VCOstartfix
  * AssemblingArthur (n.b. still defined for safety with anything in Hdr: which uses it, but not used explicitly by the kernel)
  * MouseBufferFix
  * LCDInvert
  * LCDSupport
  * DoInitialiseMode
  * Interruptible32bitModes
  * MouseBufferManager
  * StrongARM (new CacheCleanerHack and InterruptDelay switches added to hdr/Options to cover some functionality that StrongARM previously covered)
  * SAcleanflushbroken
  * StrongARM_POST
  * IrqsInClaimRelease
  * CheckProtectionLink
  * GSWorkspaceInKernelBuffers
  * EarlierReentrancyInDAShrink
  * LongCommandLines
  * ECC
  * NoSPSRcorruption
  * RMTidyDoesNowt
  * RogerEXEY
  * StorkPowerSave
  * DebugForcedReset
  * AssembleKEYV
  * AssemblePointerV
  * ProcessorVectors
  * Keyboard_Type
  Assorted old files have also been deleted.
Admin:
  Identical binary to previous revision for IOMD & Raspberry Pi builds


Version 5.51. Tagged as 'Kernel-5_51'
parent 9a571a08
# Copyright 1997 Acorn Computers Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Makefile for IICTest
#
#
# Paths
#
EXP_HDR = <export$dir>
#
# Generic options:
#
MKDIR = cdir
AS = aasm
CP = copy
RM = remove
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend -Stamp -quit -module -To $@ -From
CPFLAGS = ~cfr~v
#
# Program specific options:
#
COMPONENT = IICTest
SOURCE = s.IICTest
TARGET = rm.IICTest
EXPORTS = ${EXP_HDR}.${COMPONENT}
#
# Generic rules:
#
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
export: ${EXPORTS}
@echo ${COMPONENT}: export complete
install_rom: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: rom module installed
clean:
${RM} ${TARGET}
@echo ${COMPONENT}: cleaned
resources:
# ${MKDIR} ${RESDIR}.${COMPONENT}
# ${CP} Resources.${LOCALE}.Messages ${RESDIR}.${COMPONENT}.Messages ${CPFLAGS}
# @echo ${COMPONENT}: resource files copied
${TARGET}: ${SOURCE}
${AS} ${ASFLAGS} ${SOURCE}
${EXP_HDR}.${COMPONENT}: hdr.${COMPONENT}
# ${CP} hdr.${COMPONENT} $@ ${CPFLAGS}
# Dynamic dependencies:
| Copyright 1997 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine clean
| Copyright 1997 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine rom
; Copyright 1997 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > s.IICTest
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetCPU
$GetIO
$GetMEMC
$GetMEMM
$GetVIDC
GBLL med_00001_debug
med_00001_debug SETL {FALSE}
AssemblingArthur SETL {TRUE}
GBLL Module
Module SETL {FALSE}
GBLL ChecksumCMOS
ChecksumCMOS SETL {TRUE}
GBLL CacheCMOSRAM ; Whether to keep a RAM copy of CMOS RAM for faster access
CacheCMOSRAM SETL MEMM_Type = "ARM600" :LAND: {TRUE} ; (Space only allocated on ARM600 versions)
GBLL ProtectStationID ; if TRUE, disallow OSBYTE &A2,0,n
ProtectStationID SETL {TRUE}
GBLL TestHarness
TestHarness SETL {TRUE}
GET Hdr:ModHand
GET Hdr:Proc
GET Hdr:CMOS
GET ^.^.hdr.PublicWS
GET ^.^.hdr.KernelWS
! 0, "NVRAMSize at ":CC::STR:(NVRamSize)
LEADR Module_LoadAddr
TAB * 9
; Module workspace allocation
^ 0, R12
i2cWorkSpace # 256
corruption_test # 4
NVSize # 1
NVSpeed # 1
RTCFlag # 1
NVBase # 1
IIC_WorkspaceSize * :INDEX: @
; **************** Module code starts here **********************
Module_BaseAddr
DCD 0
DCD IIC_Init -Module_BaseAddr
DCD IIC_Die -Module_BaseAddr
DCD IIC_Service -Module_BaseAddr
DCD IIC_Title -Module_BaseAddr
DCD IIC_HelpStr -Module_BaseAddr
DCD IIC_HC_Table-Module_BaseAddr
DCD 0
DCD 0
DCD 0
DCD 0 ; Code to manually decode swi name (not needed)
IIC_Title
DCB "IICTest",0
IIC_HelpStr
= "IICTest"
= TAB, TAB
= "0.01 (06 Mar 1997)", 0
ALIGN
; *****************************************************************************
IIC_HC_Table * Module_BaseAddr
IIC_Service * Module_BaseAddr
IIC_Init
ENTRY
LDR r2, [r12] ; Hard or soft init ?
TEQ r2, #0
BNE %FT00
; Hard init
LDR r3, =IIC_WorkspaceSize
TEQ r3, #0
BEQ %FT00
MOV r0, #ModHandReason_Claim
SWI XOS_Module
LDMVSIA sp!, {pc}
STR r2, [r12]
00 MOV r12, r2
LDR R0, =&5C5C5C5C
STR R0, corruption_test
[ CacheCMOSRAM
BL InitCMOSCache
]
BL ClaimByteV
EXIT
IIC_Die ENTRY
TEQ r12, #0
LDRNE r12, [r12]
BL ReleaseByteV
EXITS
; *****************************************************************************
; ByteV handling routines.
ClaimByteV
ENTRY "r1,r2"
MOV r0, #ByteV
ADR r1, ByteVHandler
MOV r2, r12
SWI XOS_Claim
EXIT
ReleaseByteV
ENTRY "r1,r2"
MOV r0, #ByteV
ADR r1, ByteVHandler
MOV r2, r12
SWI XOS_Release
EXIT
ByteVHandler
Push "r0,r1"
TEQ r0, #&A2
BEQ OsbyteA2
TEQ r0, #&A1
Pull "r0,r1",NE
MOVNES pc, lr
; If &A1 then drop through to...
; *****************************************************************************
; OS_Byte &A1 and &A2 handlers pulled from s.PMF.osbyte. We declare our own
; MyOsbyte macro to exit our handler by claiming the ByteV call.
MACRO
MyOsbyte $cond
Pull "r0,r1,pc",$cond,^
MEND
; Read CMOS RAM
OsbyteA1 ; R1 = address , R2 = result
CLRPSR I_bit, R0 ; this may take some time
MOV R0, R1
BL Read ; Read CMOS ram at address <R0>
MOV R2, R0 ; Result in R0, return in R2
MyOsbyte
; Write CMOS RAM
OsbyteA2
CLRPSR I_bit, R0 ; this may take some time
[ E2ROMSupport
MOVS R0, R1
|
ANDS R0, R1, #&FF ; only look at bottom byte
]
[ ProtectStationID
MyOsbyte EQ
]
; This bit is conditioned out to make life easier...
;
[ {FALSE}
; Protect machine address CMOS (if not corrupt)
ASSERT EtherCheckCMOS = EtherAddrCMOS+6
CMP r0, #EtherAddrCMOS
BLT %FT10
CMP r0, #EtherCheckCMOS
BGT %FT10
Push "r0,r1"
BL GetMachineAddressCMOS
Pull "r0,r1"
MyOsbyte EQ ; don't allow write if address is valid
10
]
MOV R1, R2
BL Write
MOV R1, R0 ; R1 is supposed to be preserved
MyOsbyte
; *****************************************************************************
; Include the i2cutils source file from the Kernel sources.
GET ^.^.s.PMF.i2cutils
END
......@@ -196,11 +196,9 @@ in the 32-bit case:
ADR R14, saveblock ; get address of saved registers
LDR R0, [R14, #16*4] ; get user PSR
[ :LNOT: NoSPSRcorruption
MRS R1, CPSR ; get current PSR
ORR R1, R1, #&80 ; disable interrupts to prevent
MSR CPSR_c, R1 ; SPSR_SVC corruption by IRQ code (yuck)
]
MSR SPSR_cxsf, R0 ; put it into SPSR_SVC
LDMIA R14, {R0-R14}^ ; load user registers
MOV R0, R0 ; no-op after forcing user mode
......
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
| > NewModes.Make
WimpSlot -min 1024k -max 1024k
AASM <Obey$Dir>.PSSrc <Obey$Dir>.PSModule -module -quit
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; general purpose mode macros
ClockShift * 9
SyncShift * 11
; pixel rate specifiers
CRPix_24000 * 3 :OR: (0 :SHL: ClockShift)
CRPix_16000 * 2 :OR: (0 :SHL: ClockShift)
CRPix_12000 * 1 :OR: (0 :SHL: ClockShift)
CRPix_8000 * 0 :OR: (0 :SHL: ClockShift)
CRPix_25175 * 3 :OR: (1 :SHL: ClockShift)
CRPix_36000 * 3 :OR: (2 :SHL: ClockShift)
MACRO
VIDC_List $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
LCLA sub
LCLA syncpol
[ $lbpp = 3
sub SETA 5
]
[ $lbpp = 2
sub SETA 7
]
[ $lbpp = 1
sub SETA 11
]
[ $lbpp = 0
sub SETA 19
]
[ "$sp"=""
syncpol SETA 0 :SHL: SyncShift ; normal sync polarity
|
ASSERT $sp<=3
syncpol SETA $sp :SHL: SyncShift
]
ASSERT ($hsync :AND: 1)=0
ASSERT ($hbpch :AND: 1)=1
ASSERT ($hlbdr :AND: 1)=0
ASSERT ($hdisp :AND: 1)=0
ASSERT ($hrbdr :AND: 1)=0
ASSERT ($hfpch :AND: 1)=1
[ (($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch) :AND: 3)<>0
! 0, "Warning: mode unsuitable for interlaced use"
]
; Horizontal
& (&80:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch -2 )/2) :SHL: 14) ; HCR
& (&84:SHL:24) :OR: ((($hsync -2 )/2) :SHL: 14) ; HSWR
& (&88:SHL:24) :OR: ((($hsync+$hbpch -1 )/2) :SHL: 14) ; HBSR
& (&8C:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr -sub)/2) :SHL: 14) ; HDSR
& (&90:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp -sub)/2) :SHL: 14) ; HDER
& (&94:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr -1 )/2) :SHL: 14) ; HBER
& (&9C:SHL:24) :OR: (((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch-2)/2+1)/2):SHL:14); HIR
; Vertical
& (&A0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr+$vfpch -1) :SHL: 14) ; VCR
& (&A4:SHL:24) :OR: (($vsync -1) :SHL: 14) ; VSWR
& (&A8:SHL:24) :OR: (($vsync+$vbpch -1) :SHL: 14) ; VBSR
& (&AC:SHL:24) :OR: (($vsync+$vbpch+$vlbdr -1) :SHL: 14) ; VDSR
& (&B0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp -1) :SHL: 14) ; VDER
& (&B4:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr -1) :SHL: 14) ; VBER
; Control Register
& (&E0:SHL:24) :OR: (CRPix_$pixrate) :OR: ($lbpp :SHL: 2) :OR: syncpol
& -1
MEND
MACRO
VIDC_WS $bpp,$hpix,$vpix,$multx,$multy, $dht
& VduExt_XWindLimit, $hpix-1
& VduExt_ScrRCol, ($hpix/8)-1
& VduExt_LineLength, $hpix*$bpp/8
[ "$dht" <> ""
& VduExt_ModeFlags, ModeFlag_DoubleVertical
& VduExt_ScrBRow, ($vpix/16)-1
|
& VduExt_ScrBRow, ($vpix/8)-1
]
& VduExt_YWindLimit, $vpix-1
& VduExt_ScreenSize, $hpix*$vpix*$bpp/8
& VduExt_XEigFactor, $multx
& VduExt_YEigFactor, $multy
MEND
VLN_0 VIDC_List 0, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 0
VLN_1 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 1
VLN_2 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 2
VLN_3 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 3
VLN_4 VIDC_List 0, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 4
VLN_5 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 5
VLN_6 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,22,250,19, 0, 8000,0 ; MODE 6
VLN_7 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,22,250,19, 0, 8000,0 ; MODE 7
VLN_8 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 8
VLN_9 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 9
VLN_10 VIDC_List 3, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 10
VLN_11 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 11
VLN_12 VIDC_List 2, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 12
VLN_13 VIDC_List 3, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 13
VLN_14 VIDC_List 2, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 14
VLN_15 VIDC_List 3, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 15
VLN_16 VIDC_List 2, 72,215, 46,1056, 46,101, 3,18,18,256,17, 0,24000,0 ; MODE 16
VLN_17 VIDC_List 2, 72,215, 46,1056, 46,101, 3,18,22,250,19, 0,24000,0 ; MODE 17
;VLN_18 VIDC_List 0, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 18
;VLN_19 VIDC_List 1, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 19
;VLN_20 VIDC_List 2, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 20
;VLN_21 VIDC_List 3, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 21
VLN_24 VIDC_List 3, 72,215, 46,1056, 46,101, 3,18,18,256,17, 0,24000,0 ; MODE 24
VLN_33 VIDC_List 3, 74,127, 0, 768, 0, 55, 3,18, 0,288, 0, 3,16000,0 ; MODE 33
VLN_34 VIDC_List 3, 74, 87, 0, 832, 0, 31, 3,18, 0,288, 0, 3,16000,0 ; MODE 34
VLM_0 VIDC_List 0, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 0
VLM_1 VIDC_List 1, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 1
VLM_2 VIDC_List 2, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 2
VLM_3 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 3
VLM_4 VIDC_List 0, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 4
VLM_5 VIDC_List 1, 36, 51, 24, 320, 24, 57, 3,16,17,256,17, 3, 8000,0 ; MODE 5
VLM_6 VIDC_List 1, 36, 33, 44, 320, 44, 35, 3,16,20,250,20, 3, 8000,0 ; MODE 6
VLM_7 VIDC_List 2, 36, 31, 44, 320, 44, 37, 3,18,22,250,16, 3, 8000,0 ; MODE 7
VLM_8 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 8
VLM_9 VIDC_List 2, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 9
VLM_10 VIDC_List 3, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 10
VLM_11 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 11
VLM_12 VIDC_List 2, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 12
VLM_13 VIDC_List 3, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 13
VLM_14 VIDC_List 2, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 14
VLM_15 VIDC_List 3, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 15
VLM_16 VIDC_List 2,112, 47,132,1056,132, 57, 3,16,17,256,17, 3,24000,0 ; MODE 16
VLM_17 VIDC_List 2,112, 47,132,1056,132, 57, 3,16,20,250,20, 3,24000,0 ; MODE 17
VLM_18 VIDC_List 0, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 18
VLM_19 VIDC_List 1, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 19
VLM_20 VIDC_List 2, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 20
VLM_21 VIDC_List 3, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 21
VLM_24 VIDC_List 3,112, 47,132,1056,132, 57, 3,16,17,256,17, 3,24000,0 ; MODE 24
VLM_25 VIDC_List 0, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 25
VLM_26 VIDC_List 1, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 26
VLM_27 VIDC_List 2, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 27
VLM_28 VIDC_List 3, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 28
VLM_31 VIDC_List 2, 72,129, 0, 800, 0, 23, 2,22, 0,600, 0, 1,36000,0 ; MODE 31
VLH_23 VIDC_List 2, 52, 47, 2, 288, 2, 1, 3,43, 4,896, 4, 0,24000,0 ; MODE 23
[ {FALSE} ; This mode not supported by VIDC, so not used
V32tab1
VIDC_List 0,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
]
V32tab2 ; MODES 1,5
VIDC_List 1,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V32tab2T ; MODE 6
VIDC_List 1,36,73,24,320,24,35, 3,18,22,250,19,0,8000,0
V32tab4 ; MODES 2,9
VIDC_List 2,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V32tab4T ; MODE 7
VIDC_List 2,36,73,24,320,24,35, 3,18,22,250,19,0,8000,0
V32tab8 ; MODES 10,13
VIDC_List 3,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V64tab1 ; MODES 0,4
VIDC_List 0,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab2 ; MODE 8
VIDC_List 1,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab2T ; MODES 3,11
VIDC_List 1,72,145,48,640,48,71, 3,18,22,250,19,0,16000,0
V64tab4 ; MODE 12
VIDC_List 2,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab4T ; MODE 14
VIDC_List 2,72,145,48,640,48,71, 3,18,22,250,19,0,16000,0
V64tab8 ; MODE 15
VIDC_List 3,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V132tab4 ; MODE 16
VIDC_List 2,72,215,46,1056,46,101, 3,18,18,256,17,0,24000,0
V132tab4T ; MODE 17
VIDC_List 2,72,215,46,1056,46,101, 3,18,22,250,19,0,24000,0
[ {TRUE}
V64tab1D ; MODE 18
VIDC_List 0,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab2D ; MODE 19
VIDC_List 1,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab4D ; MODE 20
VIDC_List 2,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab8D ; MODE 21 (NEW)
VIDC_List 3,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
[ {FALSE} ; not used any more
V128tab1 ; MODE 22
VIDC_List 2,54,39,2,320,2,7, 2,44,1,976,1,0,24000,0
]
V115tab1 ; MODE 23 new Unoid monitor style, 1152x896
; changed again 29-Jul-88 to give 64.4Hz
VIDC_List 2,52,47,2,288,2,1, 3,43,4,896,4,0,24000,0
|
V64tab1D ; MODE 18 (old)
VIDC_List 0,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V64tab2D ; MODE 19 (old)
VIDC_List 1,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V64tab4D ; MODE 20 (old)
VIDC_List 2,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V128tab1 ; MODE 22 (old)
VIDC_List 2,60,41,0,320,0,3, 2,44,1,976,1,0,24000,0
V115tab1 ; MODE 23
VIDC_List 2,60,41,16,288,16,3, 2,44,57,864,57,0,24000,0
]
V132tab8 ; MODE 24 (NEW)
VIDC_List 3,72,215,46,1056,46,101, 3,18,18,256,17,0,24000,0
[ {FALSE} ; This mode not supported by VIDC, so not used
V32tab1
& &803FC000
& &84044000
& &880D8000
& &8C0E4000
& &90364000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000030
& -1
]
V32tab2 ; MODES 1,5
& &803FC000
& &84044000
& &880D8000
& &8C0F4000
& &90374000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000034
& -1
V32tab2T ; MODE 6
& &803FC000
& &84044000
& &880D8000
& &8C0F4000
& &90374000