• Ben Avison's avatar
    Support for ARMv8 · 66b90f9d
    Ben Avison authored
      * Filled in CPU tables for publicly documented ARMv8 cores (Cortex-A53,57,72).
      * Recent ARM ARMs (e.g. section B1.9.2 of the ARMv7AR ARM) permit the core to
        take an undefined instruction exception upon encountering even not-taken
        conditional undefined instructions. This option is exercised by the
        Cortex-A53, unlike all ARMv7 cores previously supported by RISC OS. This
        unfortunately trips up a lot of kernel code that adapts to different
        architectures at runtime. These have now all been replaced with branches
        over the affected code on the opposite condition.
      * Fixed bug in HAL_InvalidateCache_ARMvF: for the main body of the loop,
        which was written as though to act on the CLIDR register, r8 actually
        contained the CTR register instead.
      Tested on Raspberry Pi 3
    Version 5.35, Tagged as 'Kernel-5_35-4_79_2_304'
VersionASM 1.02 KB