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Commit 115e6d35 authored by Ben Avison's avatar Ben Avison
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Fixed cache detection code 

Detail:
  The cache details were previously fixed in a look-up table based upon the
  CPU as determined from the Main ID register for "fancy" ARMv6 CPUs (that is,
  ARMv6K, ARMv6Z, ARMv6T2). So the details for the S3C6410 were being used
  for all ARM1176JZF-S CPUs, which isn't correct for the BCM2835, which has
  the same CPU. Adrian's original stopgap solution was to override the
  settings with a bunch of MOV instructions, which had the effect of making
  the kernel useless on any other CPU. Now the details are read from the ARM
  cache type register for fancy ARMv6 CPUs. This necessitated adding support
  for an extra cache type: writeback, with cache cleaning using R7, and cache
  lockdown format C. Since we don't actually do cache lockdown, this follows
  the same code path as cache lockdown type A, which was originally written
  for ARM9 CPUs.
Admin:
  Tested in a Raspberry Pi build

Version 5.35, 4.79.2.147.2.2. Tagged as 'Kernel-5_35-4_79_2_147_2_2'
parent f092f5f5
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Showing with 29 additions and 37 deletions
VersionASM
View file @ 115e6d35
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.147.2.1"
Module_Date SETS "10 May 2012"
Module_ApplicationDate SETS "10-May-12"
Module_MinorVersion SETS "4.79.2.147.2.2"
Module_Date SETS "14 May 2012"
Module_ApplicationDate SETS "14-May-12"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.147.2.1)"
Module_HelpVersion SETS "5.35 (10 May 2012) 4.79.2.147.2.1"
Module_FullVersion SETS "5.35 (4.79.2.147.2.2)"
Module_HelpVersion SETS "5.35 (14 May 2012) 4.79.2.147.2.2"
END
VersionNum
View file @ 115e6d35
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.147.2.1
#define Module_Date_CMHG 10 May 2012
#define Module_MinorVersion_CMHG 4.79.2.147.2.2
#define Module_Date_CMHG 14 May 2012
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.147.2.1"
#define Module_Date "10 May 2012"
#define Module_MinorVersion "4.79.2.147.2.2"
#define Module_Date "14 May 2012"
#define Module_ApplicationDate "10-May-12"
#define Module_ApplicationDate "14-May-12"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.147.2.1)"
#define Module_HelpVersion "5.35 (10 May 2012) 4.79.2.147.2.1"
#define Module_FullVersion "5.35 (4.79.2.147.2.2)"
#define Module_HelpVersion "5.35 (14 May 2012) 4.79.2.147.2.2"
#define Module_LibraryVersionInfo "5:35"
s/ARMops
View file @ 115e6d35
......@@ -221,12 +221,6 @@ FindARMloop
; others ...
WeirdARMPanic
! 0, "FIXME: temporary code"
;!!!
MOV ip,#&C0
STR a1,[ip,#&40]
STMIA ip,{a1-ip}
B WeirdARMPanic ; stiff :)
Analyse_ARMv3
......@@ -572,10 +566,6 @@ Analyse_WB_CR7_Lx
CMP a3, #14 ; Stop after level 7 (even though an 8th level might exist on some CPUs?)
ADD a2, a2, #4
BLT %BT10
! 0, "FIXME: temporary code"
;!!!
MOV a4,#32
MOV v2,#32
STRB a4, [v6, #ICache_LineLen] ; Store log2(line size)-2
STRB v2, [v6, #DCache_LineLen] ; log2(line size)-2
......@@ -760,9 +750,9 @@ KnownCPUTable
; Simplified CPUDesc table for ARMvF
; The cache size data is ignored for ARMv7.
KnownCPUTable_Fancy
CPUDesc Cortex_A8, &00C080, &00FFF0, ARMvF, WB_CR7_Lx, 1, 16K, 32, 16, 16K, 32, 16
CPUDesc Cortex_A9, &00C090, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32, 16, 32K, 32, 16
CPUDesc ARM1176JZF_S, &00B760, &00FFF0, ARMv6, WB_CR7_LDa, 1, 16K, 32, 16,16K, 32, 16
CPUDesc ARM1176JZF_S, &00B760, &00FFF0, ARMvF, WB_CR7_LDc, 1, 16K, 4, 8, 16K, 4, 8
CPUDesc Cortex_A8, &00C080, &00FFF0, ARMvF, WB_CR7_Lx, 1, 16K, 32,16, 16K, 32,16
CPUDesc Cortex_A9, &00C090, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
DCD -1
; Peculiar characteristics of individual ARMs not deducable otherwise. First field is
......@@ -840,20 +830,21 @@ ARM_Analyse_Fancy
BNE %FT25
; ARMv6 format cache type register.
; TODO - Use the cache type register to deduce the cache info.
; For now, just fall back on the values in the CPU table.
ASSERT CT_Isize_pos = 0
MOV a1, v2
; CPUs like the ARM1176JZF-S are available with a range of cache sizes,
; so it's not safe to rely on the values in the CPU table. Fortunately
; all ARMv6 CPUs implement the register (by contrast, for the "plain"
; ARM case, no ARMv3 CPUs, some ARMv4 CPUs and all ARMv5 CPUs, so it
; needs to drop back to the table in some cases).
ARM_read_cachetype v2
MOV a1, v2, LSR #CT_Isize_pos
ADD a2, v6, #ICache_Info
BL EvaluateCache
MOV a1, v2, LSR #CT_Dsize_pos
ADD a2, v6, #DCache_Info
BL EvaluateCache
;EvaluateCache isn't doing our job for us....assuming these flags are true! ;)
! 0, "FIXME: temporary code"
;!!!
ORR v5, v5, #CPUFlag_SynchroniseCodeAreas+CPUFlag_SplitCache
TST v2, #CT_S
ORRNE v5, v5, #CPUFlag_SynchroniseCodeAreas+CPUFlag_SplitCache
B %FT27
......@@ -933,17 +924,18 @@ ARM_Analyse_Fancy
TSTEQ v5, #CPUFlag_SplitCache
BEQ Analyse_WriteThroughUnified ; eg. ARM7TDMI derivative
TEQ a2, #CT_ctype_WB_CR7_LDa
BEQ Analyse_WB_CR7_LDa ; eg. ARM9
TEQ a2, #CT_ctype_WB_CR7_LDa ; eg. ARM9
TEQNE a2, #CT_ctype_WB_CR7_LDc ; eg. ARM1176JZF-S - differs only in cache lockdown
BEQ Analyse_WB_CR7_LDa
TEQ a2, #CT_ctype_WB_Crd
BEQ Analyse_WB_Crd ; eg. StrongARM
TEQ a2, #CT_ctype_WB_Cal_LD
TEQ a2, #CT_ctype_WB_Cal_LD ; warning, allocation clash with CT_ctype_WB_CR7_LDd
BEQ Analyse_WB_Cal_LD ; assume XScale
TEQ a2, #CT_ctype_WB_CR7_Lx
BEQ Analyse_WB_CR7_Lx
BEQ Analyse_WB_CR7_Lx ; eg. Cortex-A8, Cortex-A9
; others ...
......
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