diff --git a/VersionASM b/VersionASM
index 1762f4e61032e5aaa26eceef1360fb46e6d9ee3a..0a58d719a38b39944cd52e678d72af5704904752 100644
--- a/VersionASM
+++ b/VersionASM
@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
-Module_MinorVersion SETS "4.79.2.147.2.1"
-Module_Date SETS "10 May 2012"
-Module_ApplicationDate SETS "10-May-12"
+Module_MinorVersion SETS "4.79.2.147.2.2"
+Module_Date SETS "14 May 2012"
+Module_ApplicationDate SETS "14-May-12"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
-Module_FullVersion SETS "5.35 (4.79.2.147.2.1)"
-Module_HelpVersion SETS "5.35 (10 May 2012) 4.79.2.147.2.1"
+Module_FullVersion SETS "5.35 (4.79.2.147.2.2)"
+Module_HelpVersion SETS "5.35 (14 May 2012) 4.79.2.147.2.2"
END
diff --git a/VersionNum b/VersionNum
index 2f601e486b4bbfe7f794f30203318817b14f4b79..564e8a7484ac77b13257cc24afc476f084523660 100644
--- a/VersionNum
+++ b/VersionNum
@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
-#define Module_MinorVersion_CMHG 4.79.2.147.2.1
-#define Module_Date_CMHG 10 May 2012
+#define Module_MinorVersion_CMHG 4.79.2.147.2.2
+#define Module_Date_CMHG 14 May 2012
#define Module_MajorVersion "5.35"
#define Module_Version 535
-#define Module_MinorVersion "4.79.2.147.2.1"
-#define Module_Date "10 May 2012"
+#define Module_MinorVersion "4.79.2.147.2.2"
+#define Module_Date "14 May 2012"
-#define Module_ApplicationDate "10-May-12"
+#define Module_ApplicationDate "14-May-12"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
-#define Module_FullVersion "5.35 (4.79.2.147.2.1)"
-#define Module_HelpVersion "5.35 (10 May 2012) 4.79.2.147.2.1"
+#define Module_FullVersion "5.35 (4.79.2.147.2.2)"
+#define Module_HelpVersion "5.35 (14 May 2012) 4.79.2.147.2.2"
#define Module_LibraryVersionInfo "5:35"
diff --git a/s/ARMops b/s/ARMops
index b13c9297fcf19b219b0635822c82ea8188526af3..17786062dc47caff6c7ec8b7ec8376728d1bf528 100644
--- a/s/ARMops
+++ b/s/ARMops
@@ -221,12 +221,6 @@ FindARMloop
; others ...
WeirdARMPanic
- ! 0, "FIXME: temporary code"
-;!!!
- MOV ip,#&C0
- STR a1,[ip,#&40]
- STMIA ip,{a1-ip}
-
B WeirdARMPanic ; stiff :)
Analyse_ARMv3
@@ -572,10 +566,6 @@ Analyse_WB_CR7_Lx
CMP a3, #14 ; Stop after level 7 (even though an 8th level might exist on some CPUs?)
ADD a2, a2, #4
BLT %BT10
- ! 0, "FIXME: temporary code"
-;!!!
- MOV a4,#32
- MOV v2,#32
STRB a4, [v6, #ICache_LineLen] ; Store log2(line size)-2
STRB v2, [v6, #DCache_LineLen] ; log2(line size)-2
@@ -760,9 +750,9 @@ KnownCPUTable
; Simplified CPUDesc table for ARMvF
; The cache size data is ignored for ARMv7.
KnownCPUTable_Fancy
- CPUDesc Cortex_A8, &00C080, &00FFF0, ARMvF, WB_CR7_Lx, 1, 16K, 32, 16, 16K, 32, 16
- CPUDesc Cortex_A9, &00C090, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32, 16, 32K, 32, 16
- CPUDesc ARM1176JZF_S, &00B760, &00FFF0, ARMv6, WB_CR7_LDa, 1, 16K, 32, 16,16K, 32, 16
+ CPUDesc ARM1176JZF_S, &00B760, &00FFF0, ARMvF, WB_CR7_LDc, 1, 16K, 4, 8, 16K, 4, 8
+ CPUDesc Cortex_A8, &00C080, &00FFF0, ARMvF, WB_CR7_Lx, 1, 16K, 32,16, 16K, 32,16
+ CPUDesc Cortex_A9, &00C090, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32,16, 32K, 32,16
DCD -1
; Peculiar characteristics of individual ARMs not deducable otherwise. First field is
@@ -840,20 +830,21 @@ ARM_Analyse_Fancy
BNE %FT25
; ARMv6 format cache type register.
- ; TODO - Use the cache type register to deduce the cache info.
- ; For now, just fall back on the values in the CPU table.
- ASSERT CT_Isize_pos = 0
- MOV a1, v2
+ ; CPUs like the ARM1176JZF-S are available with a range of cache sizes,
+ ; so it's not safe to rely on the values in the CPU table. Fortunately
+ ; all ARMv6 CPUs implement the register (by contrast, for the "plain"
+ ; ARM case, no ARMv3 CPUs, some ARMv4 CPUs and all ARMv5 CPUs, so it
+ ; needs to drop back to the table in some cases).
+ ARM_read_cachetype v2
+ MOV a1, v2, LSR #CT_Isize_pos
ADD a2, v6, #ICache_Info
BL EvaluateCache
MOV a1, v2, LSR #CT_Dsize_pos
ADD a2, v6, #DCache_Info
BL EvaluateCache
-;EvaluateCache isn't doing our job for us....assuming these flags are true! ;)
- ! 0, "FIXME: temporary code"
-;!!!
- ORR v5, v5, #CPUFlag_SynchroniseCodeAreas+CPUFlag_SplitCache
+ TST v2, #CT_S
+ ORRNE v5, v5, #CPUFlag_SynchroniseCodeAreas+CPUFlag_SplitCache
B %FT27
@@ -933,17 +924,18 @@ ARM_Analyse_Fancy
TSTEQ v5, #CPUFlag_SplitCache
BEQ Analyse_WriteThroughUnified ; eg. ARM7TDMI derivative
- TEQ a2, #CT_ctype_WB_CR7_LDa
- BEQ Analyse_WB_CR7_LDa ; eg. ARM9
+ TEQ a2, #CT_ctype_WB_CR7_LDa ; eg. ARM9
+ TEQNE a2, #CT_ctype_WB_CR7_LDc ; eg. ARM1176JZF-S - differs only in cache lockdown
+ BEQ Analyse_WB_CR7_LDa
TEQ a2, #CT_ctype_WB_Crd
BEQ Analyse_WB_Crd ; eg. StrongARM
- TEQ a2, #CT_ctype_WB_Cal_LD
+ TEQ a2, #CT_ctype_WB_Cal_LD ; warning, allocation clash with CT_ctype_WB_CR7_LDd
BEQ Analyse_WB_Cal_LD ; assume XScale
TEQ a2, #CT_ctype_WB_CR7_Lx
- BEQ Analyse_WB_CR7_Lx
+ BEQ Analyse_WB_CR7_Lx ; eg. Cortex-A8, Cortex-A9
; others ...