GitLab

Detail:
  s.PMF.i2cutils line 454: this LDR of byte values was harmless (bits 8
    upwards are discarded later) but slower than an LDRB on ARMv6 or later.
  s.PMF.i2cutils line 556: should have loaded RTCFitted using LDRB. Looks
    like effect would have been to reduce utilisation of CMOS cache.
  s.vdu.vduswis line 1500: mistakenly accessing ExternalFramestore using LDR.
    I don't think the intention was to prevent the screen DA being resized
    while screen memory was claimed, but that was the effect.
  s.vdu.vduwrch line 3106: this LDR of a 1-byte variable was harmless (only
    used for testing bit 4) but slower than an LDRB on ARMv6 or later.
  CPU version is no longer specified in the makefile - it's better to inherit
  it from the build environment now that we actually set it appropriately.
Admin:
  Built and briefly tested.

Version 5.35, 4.79.2.98.2.9. Tagged as 'Kernel-5_35-4_79_2_98_2_9'

Detail:
 * Stopped calling the broken abort fixup code when running under VMSAv6.
   Might be desirable to update it, possibly farmed out to a separate module -
   still need to think about this.
 * Unaligned load optimisations can now be disabled by the global NoUnaligned
   flag for testing purposes.
 * Extended OS_ReadUnsigned to permit reading of 64-bit unsigned integers.
   See Docs.ReadUnsigned for more details. Also sped it up by using MLA
   (or UMLAL) for most digits rather than repeated addition.
 * Bugfix is OS_GSRead: an uninitialised r0 was being passed to
   OS_ReadUnsigned, causing undesirable effects on rare occasions.
Admin:
  Tested on a rev B7 beagleboard.

Version 5.35, 4.79.2.98.2.8. Tagged as 'Kernel-5_35-4_79_2_98_2_8'

Detail:
  s/vdu/vduwrch - Modify PageTest to never use paged scrolling when DebugTerminal is true (since serial terminals aren't able to send shift up/down messages)
Admin:
  Tested on rev C2 beagleboard.


Version 5.35, 4.79.2.98.2.7. Tagged as 'Kernel-5_35-4_79_2_98_2_7'

Detail:
  Having scanned the kernel source for unaligned load code fragments which
  would abort on ARMv6 and v7 and not having found any, I took the opportunity
  to give them build-time switches to use unaligned LDR((S)H)/STR(H)
  instructions if built for a new enough platform. Also added a couple of
  cases of LDRSB that will benefit v4 CPUs and a few instances of the v6
  SXTH instruction, but since objasm doesn't yet understand it (and when it
  does, not everyone will have upgraded) they are currently written as
  DCI statements.
  Most of the changes are to OS_Word handlers, which are notorious in that
  their input/output block is not word-aligned.
Admin:
  Not tested, but it should at least build.

Version 5.35, 4.79.2.98.2.6. Tagged as 'Kernel-5_35-4_79_2_98_2_6'

Detail:
  s/ARMops - Fix IMB_Range_WB_CR7_Lx to clean the correct number of cache lines
  s/HAL - Change CP15 control register flags so unaligned loads are enabled on ARMv6 (to simplify support for ARMv7 where unaligned loads are always enabled, and to match the behaviour expected by the example code in Hdr:CPU.Arch)
  s/AMBControl/memmap - Make AMB_LazyFixUp use the correct L2PT protection flags depending on ARM600/VMSAv6 MMU model. Also guard against problems caused by future L2PT flag changes.
  s/vdu/vdugrafj - Fix previously undiscovered 32bit incompatability in GetSprite (OS_SpriteOp 14/16)
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.5. Tagged as 'Kernel-5_35-4_79_2_98_2_5'

Detail:
  s/ARMops - Fix set/way-based cache ops for cache type WB_CR7_Lx to iterate sets/ways/cache levels properly
  s/HAL - Fix HAL_InvalidateCache_ARMvF to iterate sets/ways/cache levels properly
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.4. Tagged as 'Kernel-5_35-4_79_2_98_2_4'

Detail:
  s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
  s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
  s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
  s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
  s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
  s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
  hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
Admin:
  Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.


Version 5.35, 4.79.2.98.2.3. Tagged as 'Kernel-5_35-4_79_2_98_2_3'

Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate, use CPU feature registers to identify CPU capabilities.

Detail:
  s/ARMops - Support for Cortex multi-level cache (CT_ctype_WB_CR7_Lx). New ARM_Analyse_Fancy to identify CPU capabilities using feature registers.
  s/HAL - Modify pre-ARMop cache code to handle Cortex-syle caches.
  s/MemInfo - Replace ARM_flush_TLB macro call with appropriate ARMop to provide Cortex compatability
  hdr/ARMops - Update list of ARM architectures
  hdr/CoPro15ops - Deprecate ARM_flush_* macros for HAL kernels, as they are no longer capable of flushing all cache types. ARMops should be used instead.
  hdr/KernelWS - Add storage space for multi-level cache properties required for new cache cleaning code.
Admin:
  Tested under qemu-omap3. Still unable to verify on real hardware due to lack of appropriate MMU code. However new OMAP3 HAL code that uses similar cache management functions appears to work fine on real hardware.


Version 5.35, 4.79.2.98.2.2. Tagged as 'Kernel-5_35-4_79_2_98_2_2'

Detail:
  hdr/ARMops - Added Cortex_A8 processor type, new ARM architecture number
  hdr/Options - Enabled various kernel debug options
  s/ARMops - Added Cortex-A8/OMAP3530 to known CPUs list. Ignore cache type register for ARM architecture &F.
  s/NewIRQs - Increase MaxInterrupts to 96
Admin:
  Brief testing under qemu-omap3.



Version 5.35, 4.79.2.98.2.1. Tagged as 'Kernel-5_35-4_79_2_98_2_1'

Detail:
  * Added some documentation on previously undocumented HAL calls
  * Corrected NVMemoryFlag_Provision bitmask to match documentation
  * Bugfix: NVMemoryFlag_ProtectAtEnd flag was being ignored
Admin:
  Not tested

Version 5.35, 4.79.2.98. Tagged as 'Kernel-5_35-4_79_2_98'

Version 5.35, 4.79.2.97. Tagged as 'Kernel-5_35-4_79_2_97'

Detail:
  Updated GraphicsV documentation
  Upped ROM version number - currently matches latest Castle release (5.13)
Admin:
  No code change

Version 5.35, 4.79.2.96. Tagged as 'Kernel-5_35-4_79_2_96'

Detail:

Admin:


Version 5.35, 4.79.2.95. Tagged as 'Kernel-5_35-4_79_2_95'

Detail:
Admin:


Version 5.35, 4.79.2.94. Tagged as 'Kernel-5_35-4_79_2_94'

Detail:

Admin:	needed for changed module


Version 5.35, 4.79.2.93. Tagged as 'Kernel-5_35-4_79_2_93'

Detail:

Admin:


Version 5.35, 4.79.2.92. Tagged as 'Kernel-5_35-4_79_2_92'

	no other changes
Detail:
Admin:


Version 5.35, 4.79.2.91. Tagged as 'Kernel-5_35-4_79_2_91'

OS_ReadSysInfo 6 (subreason code is 23 for IRQsema). This will
be useful if zero page is ever protected and the IRQ semaphore
moved.

Version 5.35, 4.79.2.90. Tagged as 'Kernel-5_35-4_79_2_90'

Detail:
  Internationalisation of *Help code (ie probably dating back to RISC OS 3.1)
  broke the Escape condition checking. This is particularly nasty if you
  do *Help . on a machine with slow hardware scrolling!
Admin:
  Not tested.

Version 5.35, 4.79.2.89. Tagged as 'Kernel-5_35-4_79_2_89'

Detail:
Admin:


Version 5.35, 4.79.2.88. Tagged as 'Kernel-5_35-4_79_2_88'

Version 5.35, 4.79.2.87. Tagged as 'Kernel-5_35-4_79_2_87'

Detail:
Admin:


Version 5.35, 4.79.2.86. Tagged as 'Kernel-5_35-4_79_2_86'

Version 5.35, 4.79.2.85. Tagged as 'Kernel-5_35-4_79_2_85'

Version 5.35, 4.79.2.84. Tagged as 'Kernel-5_35-4_79_2_84'

Detail:
  Tightened up BBE resources export, to exclude in appropriate files (this
  component has a non-standard resources directory structure).
Admin:
  Tested in a Tungsten BBE build.

Retagged, since this won't affect any existing builds.

Detail:
Admin:


Version 5.35, 4.79.2.83. Tagged as 'Kernel-5_35-4_79_2_83'

Detail: Kevin work, in response to D Ellis fault find
Admin:
      Castle IP


Version 5.35, 4.79.2.82. Tagged as 'Kernel-5_35-4_79_2_82'

     1: default ticker based vsync generated whenever no device present to do so
     2: graphicsv handling and spec updated to use the hi 8 bits in the
        reason code (R4) to define the display number. Kernel only knows
        of display 0
Detail:
Admin:
     tested castle  castle added ip


Version 5.35, 4.79.2.81. Tagged as 'Kernel-5_35-4_79_2_81'

Detail:
Admin:


Version 5.35, 4.79.2.80. Tagged as 'Kernel-5_35-4_79_2_80'

        HAL_Video_IIC_Op
Detail:
Admin:
     JB  Castle IP

Version 5.35, 4.79.2.79. Tagged as 'Kernel-5_35-4_79_2_79'

Detail:
  * I noticed in passing that the default exception handlers were broken for
    non-IOMD machines if the exception was raised in FIQ mode - unless you
    had a very large application slot, then the machine would lock up. Now
    properly HAL-ised.
  * Added a new event number, allocated for PRISM use back in June.
Admin:
  Not tested. However, it can't make the situation any worse!

Version 5.35, 4.79.2.78. Tagged as 'Kernel-5_35-4_79_2_78'

Detail:
  Previously, UnthreadV was only called when the IRQsema chain was empty, the
  link for the just-completed interrupt having just been removed. However,
  the information in the link is necessary to allow OS_Heap to be called from
  UnthreadV context, and patching up IRQsema within the UnthreadV handler
  prevents the implementation of a prioritised threading scheme. As a result,
  we must call UnthreadV every time the interrupt dispatch unthreads, and
  leave it up to the UnthreadV handler to distinguish between return to
  thread context and return from a nested interrupt handler.
Admin:
  Will require some sort of patch to enable heap-safe prioritised threading
  on RISC OS-STB 5.0.0 or RISC OS 5.07, the only two released OSes with the
  previous UnthreadV behaviour.

Version 5.35, 4.79.2.77. Tagged as 'Kernel-5_35-4_79_2_77'

Detail:
Admin:
  castle IP


Version 5.35, 4.79.2.76. Tagged as 'Kernel-5_35-4_79_2_76'

   Tungsten HAL IIC_Transfer not initialising the checksum
Detail:

Admin:
   tested at castle.. again!
   castle added IP


Version 5.35, 4.79.2.75. Tagged as 'Kernel-5_35-4_79_2_75'

Detail:
   CheckSumBlock called IIC_OpV to checksum byte 0 of CMOS, but read back the
   resultant checksum from the wrong offset (#20.. new R1 value)..  now
   corrected to #24 as the correct offset (approx line 997).

Admin:
   tested at castle in iyonix
   castle added IP


Version 5.35, 4.79.2.74. Tagged as 'Kernel-5_35-4_79_2_74'

Detail:

Admin:
  Tested in ROM at Castle


Version 5.35, 4.79.2.73. Tagged as 'Kernel-5_35-4_79_2_73'

Version 5.35, 4.79.2.72. Tagged as 'Kernel-5_35-4_79_2_72'

* Added use of CDVPoduleIRQs (from Hdr:Machine)
* Fixed checksum corruption in OS_NVMemory block writes ending just below
  the checksum byte.
* Fixed R4 corruption by OS_Byte 162 with certain HALs.

Version 5.35, 4.79.2.71. Tagged as 'Kernel-5_35-4_79_2_71'

Detail:
  Event numbers greater than 31 are possible, it's just that OS_GenerateEvent
  doesn't bother cheking the event semaphores for them. However, the value
  returned in R1 from these OS_Bytes always indicated that such events were
  disabled. This suggests that OS_GenerateEvent was not always so, but the
  initials in comments there suggest the change was about RISC OS 3.0.
  The OS_Bytes now correctly reflect OS_GenerateEvent behaviour.
  Another bug fix is that once the event semaphores had saturated at 255,
  OS_Byte 13 was still happy to decrement the semaphore, so for example 256
  enables followed by 255 disables would have disabled the event.
Admin:
  Not tested.

Version 5.35, 4.79.2.70. Tagged as 'Kernel-5_35-4_79_2_70'

Added UnthreadV (vector &2B). Called near the end of despatch of the outermost interrupt, in IRQ32/26 mode with IRQs disabled, just before transient and non-transient callback checking is performed. Suitable for implementing a CBAI replacement.

Version 5.35, 4.79.2.69. Tagged as 'Kernel-5_35-4_79_2_69'