1. 18 Sep, 2012 1 commit
    • Jeffrey Lee's avatar
      Fix addresses sent to GraphicsV_SetDMAAddress when external framestore in use.... · 5c0a0186
      Jeffrey Lee authored
      Fix addresses sent to GraphicsV_SetDMAAddress when external framestore in use. Add ID for BCM2835 VDU HAL device.
      
      Detail:
        hdr/KernelWS, s/vdu/vdudriver, s/vdu/vduwrch - Fixed wrong addresses being sent to GraphicsV_SetDMAAddress when an external framestore is in use. Previously VideoPhysAddr was being treated as if it was the base of screen memory, but that's only the case if an internal framestore is in use. Since VideoPhysAddr is part of PhysRamTable it's not possible to change it to point to an external framestore, so a new workspace variable, TrueVideoPhysAddr, is used instead.
        hdr/HALDevice - Added device ID for BCM2835 VDU device
        s/PMF/IIC - Corrected an incorrect comment in IICDoOp
      Admin:
        Tested on Raspberry Pi with high processor vectors
      
      
      Version 5.35, 4.79.2.147.2.22. Tagged as 'Kernel-5_35-4_79_2_147_2_22'
      5c0a0186
  2. 07 Sep, 2012 1 commit
    • Jeffrey Lee's avatar
      Clean up remaining kernel hacks · ef670f73
      Jeffrey Lee authored
      Detail:
        Docs/RPiNotes - Deleted, contents no longer relevant
        s/HAL, s/Kernel, s/vdu/vduswis, s/pmf/key - Cleaned up debug code
        s/NewIRQs - No need to piggy back on timer 0 IRQ to generate a fake VSync; PushModeInfo already claims/releases TickerV as appropriate if video driver doesn't provide a VSync IRQ.
        s/NewReset - Re-enable LookForHALRTC call, the stack imbalance bug was fixed before the Pi changes were merged in
        s/vdu/vducursoft - Streamline PostWrchCursor a bit by only preserving R14 around RestorePointer if the software pointer is in use
        s/vdu/vdudriver - Amend ModeChangeSub improvements to ensure old external framestore handling logic is used if driver doesn't support framestore growth/realloc
      Admin:
        Tested on Raspberry Pi with high processor vectors
        Kernel now looks to be in a good state for merging back into HAL branch
        Note - Software mouse pointer support in vducursoft only checks HALVideoFeatures, so doesn't take into account the capabilities of any GraphicsV driver that may be in use.
      
      
      Version 5.35, 4.79.2.147.2.20. Tagged as 'Kernel-5_35-4_79_2_147_2_20'
      ef670f73
  3. 10 May, 2012 1 commit
    • Ben Avison's avatar
      Merge of Raspberry Pi support code against latest kernel · f092f5f5
      Ben Avison authored
      Detail:
        This is a new branch from the current tip of the HAL branch, incorporating
        the changes received from Adrian Lees. The same caveats apply - this is a
        work in progress and will not work on any other platform at present.
      Admin:
        Builds, but not tested.
      
      Version 5.35, 4.79.2.147.2.1. Tagged as 'Kernel-5_35-4_79_2_147_2_1'
      f092f5f5
  4. 25 Mar, 2012 1 commit
    • Robert Sprowson's avatar
      Tighten up time conversions. · 1cd6a8f2
      Robert Sprowson authored
      Convrsions.s:
      Don't trash R4 in OS_ConvertDateAndTime
      Reject buffer sizes > 2G (seems reasonable for a time string, and allows us to claw back a flag bit).
      PMF/osword.s:
      Just call Territory_ConvertDateAndTime directly since that's all OS_ConvertDateAndTime does.
      Trim some now irrelevant comments and switched out code.
      
      Version 5.35, 4.79.2.144. Tagged as 'Kernel-5_35-4_79_2_144'
      1cd6a8f2
  5. 19 Mar, 2012 1 commit
  6. 25 Feb, 2012 1 commit
    • Jeffrey Lee's avatar
      Add compressed ROM support. Make more use of ARMv5+ instructions. Other misc tweaks. · 538f3c24
      Jeffrey Lee authored
      Detail:
        hdr/OSEntries, s/HAL, s/Kernel - Add compressed ROM support.
        With the current scheme, a compressed ROM will have everything except the HAL and kernel compressed.
        During the keyboard scan period the kernel will allocate some temporary decompression workspace and call the decompression stub that was appended to the ROM.
        The decompression stub is expected to perform in-place decompression of the ROM. Once decompression is complete the workspace will be freed and the page tables updated to make the ROM image readonly.
        It's the HAL's responsibility to make sure any compressed ROM is located in an area of physically contiguous RAM large enough to hold the uncompressed image.
        More info here: http://www.riscosopen.org/wiki/documentation/show/Compressed%20ROMs
        Makefile, h/OSEntries - Add C export of hdr/OSEntries
        hdr/HALDevice - Add device ID for Tungsten video device. Convert tabs to spaces for consistency.
        hdr/HALEntries, s/NewReset - Moved KbdFlag_* definitions to hdr/HALEntries so HALs can use them in their keyboard scan code
        s/ArthurSWIs, S/HAL, s/HeapSort, s/Kernel, s/MemInfo, s/Middle, s/NewIRQs, s/TickEvents, s/vdu/vdugrafb - Make use of BLX, BFI and long multiplies if the CPU supports them. Don't support SWI calls from thumb mode if the CPU doesn't support thumb.
        s/HAL - Made the LDMIA in Init_MapInRAM more sensible (register order was backwards). The old code did work, but wasn't doing what the comments described. Removed unused/unfinished HAL_Write0 function. Improve RISCOS_LogToPhys to check L1PT for any section mappings if the logical_to_physical call fails
        s/ModHand - Save one instruction by using ADR instead of MOV+ADD to compute lr
        s/NewReset, s/PMF/key - Pass L1PT to HAL_Reset to allow machines without hardware reset (e.g. IOMD) to perform resets by manually disabling the MMU and restarting the ROM
        s/vdu/vdudriver, s/vdu/vdugrafv - Use GVEntry macro borrowed from NVidia module for setting up the GraphicsV jump table. Make GraphicsV_ReadPaletteEntry call HAL_Video_ReadPaletteEntry if left unclaimed. Fixup GV_Render to only call HAL_Video_Render if the HAL call is implemented.
      Admin:
        Tested with OMAP3, IOMD & Tungsten ROMs/softloads.
      
      
      Version 5.35, 4.79.2.138. Tagged as 'Kernel-5_35-4_79_2_138'
      538f3c24
  7. 09 Feb, 2012 1 commit
  8. 27 Nov, 2011 3 commits
    • Robert Sprowson's avatar
      Rationalise some old switches. · 189b92c1
      Robert Sprowson authored
      Export less in hdr:RISCOS.
      Delete unused GetDecimalPair routine.
      Move CheckYear with other RTC stuff out of PMF/osword.
      Hide DebugROMInit and DebugROMErrors in release (even numbered) versions.
      
      Version 5.35, 4.79.2.127. Tagged as 'Kernel-5_35-4_79_2_127'
      189b92c1
    • Robert Sprowson's avatar
      Conversions rationalisation. · 0d73c680
      Robert Sprowson authored
      Delete pmf/convdate, moved to conversions.
      Moved OS_BinaryToDecimal to conversions.
      Remove OS_ConvertHex16 and friends.
      Add OS_ConvertVariform skeleton.
      Tidied conversions.
      
      Version 5.35, 4.79.2.125. Tagged as 'Kernel-5_35-4_79_2_125'
      0d73c680
    • Robert Sprowson's avatar
      Reindent Arthur2. · 2d883d8d
      Robert Sprowson authored
      Expand tabs.
      Swap DCI for instructions now Objasm 4 is out.
      Symbols for FSControl_CAT/RUN/OPT changed to non Arthur definitions.
      Still boots on IOMD class, no other testing.
      
      Version 5.35, 4.79.2.124. Tagged as 'Kernel-5_35-4_79_2_124'
      2d883d8d
  9. 24 Sep, 2011 1 commit
    • Jeffrey Lee's avatar
      Fix objasm 4 warnings · 6d052230
      Jeffrey Lee authored
      Detail:
        s/Arthur3, s/ChangeDyn, s/HAL, s/HeapMan, s/Middle, s/MoreSWIs, s/NewIRQs, s/Utility, s/VMSAv6, s/PMF/key, s/PMF/osbyte, s/PMF/osword, s/vdu/vdudecl, s/vdu/vdudriver, s/vdu/vduplot, s/vdu/vduwrch - Tweaked lots of LDM/STM instructions in order to get rid of the depracation/performance warnings
      Admin:
        Tested on rev A2 BB-xM
      
      
      Version 5.35, 4.79.2.98.2.53. Tagged as 'Kernel-5_35-4_79_2_98_2_53'
      6d052230
  10. 08 Aug, 2011 1 commit
    • Jeffrey Lee's avatar
      Add zero page relocation support · 2247d8e9
      Jeffrey Lee authored
      Detail:
        A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
        At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
        There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
        * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
        * ShareFS needs unplugging/removing since it can't cope with it yet
        * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
        * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
        The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
        Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
        File changes:
        - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
        - hdr/Copro15ops - Corrected $quick handling in myISB macro
        - hdr/Options - Added ideal setting for us to use for HiProcVecs
        - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
        - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
        - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
        - s/KbdResPC - Disable compilation of dead code
        - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
      Admin:
        Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
        High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.
      
      
      Version 5.35, 4.79.2.98.2.48. Tagged as 'Kernel-5_35-4_79_2_98_2_48'
      2247d8e9
  11. 31 Jul, 2011 2 commits
    • Jeffrey Lee's avatar
      Update the method the HAL kernel uses to determine the UtilityModule & ROM dates · e249f5da
      Jeffrey Lee authored
      Detail:
        Three main changes:
        * On odd-numbered (i.e. development) versions of the module, the UtilityModule will now take its date from the VersionNum file instead of using a hard-coded date
        * All build versions now look for the new "extended ROM footer" (as created by romlinker 0.04+) at the end of the ROM image and use it to determine the ROM build date for return by OS_ReadSysInfo 9,2. Failing to find the build date in the footer will cause OS_ReadSysInfo 9,2 to return 0.
        * On odd-numbered versions, OS_Byte 0 will now use the ROM build date (as found in the extended footer) to generate the error block that's returned to the user. This seems OK as the PRM describes OS_Byte 0 as returning the "creation date of the operating system". Plus it's a convenient way of getting the ROM build date into the Switcher, since the switcher uses OS_Byte 0. If the extended footer can't be found (or if the string isn't initialised yet, e.g. before Service_PostInit) the code falls back to a hard-coded string containing the date from the VersionNum file.
        File changes:
        Makefile - Updated to not create the obsolete Time+Date file (previously used for the ROM build date)
        Version - Use date from VersionNum file for development builds
        hdr/Options - New UseNewFX0Error variable/option to make it easy to check which OS_Byte 0 variant should be enabled
        hdr/KernelWS - Added new string buffers & extended ROM footer pointer to workspace
        s/Middle - Updated OS_ReadSysInfo 9 code, and added utility functions for searching the extended ROM footer for certain tags
        s/NewReset - Added a couple of calls to initialise the new string buffers just prior to Service_PostInit. This is required since OS_Byte/OS_ReadSysInfo shouldn't enable interrupts, but date conversion relies on the Territory module, which may enable interrupts.
        s/PMF/osbyte - Updated OS_Byte 0 code
      Admin:
        Tested in Tungsten ROM, with and without the extended footer present.
      
      
      Version 5.35, 4.79.2.115. Tagged as 'Kernel-5_35-4_79_2_115'
      e249f5da
    • Jeffrey Lee's avatar
      Update the method the Cortex kernel uses to determine the UtilityModule & ROM dates · daa8607f
      Jeffrey Lee authored
      Detail:
        Three main changes:
        * On odd-numbered (i.e. development) versions of the module, the UtilityModule will now take its date from the VersionNum file instead of using a hard-coded date.
        * All build versions now look for the new "extended ROM footer" (as created by romlinker 0.04+) at the end of the ROM image and use it to determine the ROM build date for return by OS_ReadSysInfo 9,2. Failing to find the build date in the footer will cause OS_ReadSysInfo 9,2 to return 0.
        * On odd-numbered versions, OS_Byte 0 will now use the ROM build date (as found in the extended footer) to generate the error block that's returned to the user. This seems OK as the PRM describes OS_Byte 0 as returning the "creation date of the operation system". Plus it's a convenient way of getting the ROM build date into the Switcher, since the switcher uses OS_Byte 0. If the extended footer can't be found (or if the string hasn't been initialised yet, e.g. before Service_PostInit) the code falls back to a hard-coded string containing the date from the VersionNum file.
        File changes:
        Makefile - Updated to not create the obsolete Time+Date file (previously used for the ROM build date)
        Version - Use date from VersionNum file for development builds
        hdr/Options - New UseNewFX0Error variable/option to make it easy to check which OS_Byte 0 variant should be enabled
        hdr/KernelWS - Added new string buffers & extended ROM footer pointer to workspace
        s/Middle - Updated OS_ReadSysInfo 9 code, and added utility functions for searching the extended ROM footer for certain tags
        s/NewReset - Added a couple of calls to initialise the new string buffers just prior to Service_PostInit. This is required since OS_Byte/OS_ReadSysInfo shouldn't enable interrupts, but date conversion relies on the Territory module, which may enable interrupts.
        s/PMF/osbyte - Updated OS_Byte 0 code
      Admin:
        Tested in OMAP ROM, with and without the extended footer present.
      
      
      Version 5.35, 4.79.2.98.2.41. Tagged as 'Kernel-5_35-4_79_2_98_2_41'
      daa8607f
  12. 19 Mar, 2011 1 commit
    • Jeffrey Lee's avatar
      Add ID's for CPUClk HAL device. Trim dead code. · 2f8b5459
      Jeffrey Lee authored
      Detail:
        hdr/HALDevice - Added device type & ID for new CPUClk device, as used by the new OMAP3 HAL/PortableHAL versions.
        s/PMF/osinit - Disable a block of dead code that was getting compiled in.
      Admin:
        Tested on rev C2 BB, rev A2 BB-xM, rev C1 TouchBook
        These changes are needed by the latest OMAP3 HAL & PortableHAL versions.
      
      
      Version 5.35, 4.79.2.98.2.36. Tagged as 'Kernel-5_35-4_79_2_98_2_36'
      2f8b5459
  13. 20 Feb, 2011 2 commits
    • Jeffrey Lee's avatar
      Tweak HAL_ExtMachineID to take the buffer pointer in R0 instead of R1 · 23c9ffec
      Jeffrey Lee authored
      Detail:
        s/Middle, s/PMF/osinit - Kernel now passes the buffer pointer to the HAL in R0 instead of R1, for ATPCS compliance.
      Admin:
        Tested on rev A2 BB-xM
      
      
      Version 5.35, 4.79.2.98.2.35. Tagged as 'Kernel-5_35-4_79_2_98_2_35'
      23c9ffec
    • Jeffrey Lee's avatar
      Add OS_ReadSysInfo reason codes 11 (read debug info) & 12 (read extended machine ID) · e42119c8
      Jeffrey Lee authored
      Detail:
        OS_ReadSysInfo 10 is left unimplemented since it's a bit fiddly for us.
        OS_ReadSysInfo 11 is compatible with ROL's implementation, exposing HAL_DebugTX and HAL_DebugRX if the HAL provides them.
        See here for 10,11 docs: http://select.riscos.com/prm/core/osreadsysinfo.html
        OS_ReadSysInfo 12 is a new call to return the 'extended machine ID', to allow the HAL to specify the format & validity of the ID.
        If the HAL responds to the new HAL_ExtMachineID call then it's assumed that no old-style machine ID is present. The Kernel will generate an old-style ID using the contents of the extended ID, and use that with OS_ReadSysInfo 2/5.
        New software should use OS_ReadSysInfo 12 in preference to 2/5.
        s/Middle - Updated OS_ReadSysInfo SWI
        s/PMF/osinit - New old-style machine ID initialisation code
        hdr/HALEntries - Added new HAL_ExtMachineID entry
      Admin:
        Tested on rev A2 BB-xM
      
      
      Version 5.35, 4.79.2.98.2.34. Tagged as 'Kernel-5_35-4_79_2_98_2_34'
      e42119c8
  14. 19 Feb, 2011 1 commit
    • Jeffrey Lee's avatar
      Update OS_IICOp to support multiple IIC buses · 327d3980
      Jeffrey Lee authored
      Detail:
        OS_IICOp (and in turn, RISCOS_IICOpV) now treat the top byte of R1 as containing the IIC bus number, allowing multiple buses to be used.
        hdr/KernelWS - Changed workspace a bit so that the kernel can support up to IICBus_Count buses (currently 3), each with its own IICBus_* block.
        s/HAL - Update Reset_IRQ_Handler to cope with interrupts from all IIC buses instead of just the first. Fix/update RISCOS_IICOpV description.
        s/NewIRQs - Update InitialiseIRQ1Vtable to set up interrupt handlers for all IRQ-supporting IIC buses
        s/NewReset - Get rid of the IICAbort call that was just before IICInit. IICInit now calls IICAbort itself.
        s/PMF/IIC - Bulk of the changes. Code now uses the IICBus_ structures instead of the IICStatus and IICType variables. Re-entrancy code has been updated to take into account the possiblity of multiple buses; when OS_IICOp calls are nested, the IIC transfers will be added to bus-specific queues instead of all going in the same queue. However only one queue will be processed at a time.
        s/ChangeDyn - Workspace shuffling means a couple of MOV's needed to be swapped with LDR's when getting immediate constants
      Admin:
        Tested with OMAP & IOMD ROM builds.
        Both high & low-level bus types seem to work OK, along with re-entrancy, both on the same bus and on a different bus.
      
      
      Version 5.35, 4.79.2.98.2.33. Tagged as 'Kernel-5_35-4_79_2_98_2_33'
      327d3980
  15. 20 Feb, 2010 2 commits
    • Jeffrey Lee's avatar
      Fix detection of Philips RTC/NVRAM when MaybeIIC is in use (Cortex branch) · 114948c8
      Jeffrey Lee authored
      Detail:
        s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
      Admin:
        Not tested; however it's identical to the fix applied to the HAL branch
      
      
      Version 5.35, 4.79.2.98.2.23. Tagged as 'Kernel-5_35-4_79_2_98_2_23'
      114948c8
    • Jeffrey Lee's avatar
      Fix detection of Philips RTC/NVRAM when MaybeIIC is in use · a6492b14
      Jeffrey Lee authored
      Detail:
        s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
      Admin:
        Tested in IOMD HAL build on development version of RPCEmu.
      
      
      Version 5.35, 4.79.2.110. Tagged as 'Kernel-5_35-4_79_2_110'
      a6492b14
  16. 02 Feb, 2010 2 commits
    • Jeffrey Lee's avatar
      Fix bug in InitCMOSCache that could cause CMOS to be erroneously reset if... · 2b35d8c2
      Jeffrey Lee authored
      Fix bug in InitCMOSCache that could cause CMOS to be erroneously reset if NVRAM is of type 'MaybeIIC' (Cortex branch)
      
      Detail:
        s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and then fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
      Admin:
        Fix tested in HAL branch in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.
      
      
      Version 5.35, 4.79.2.98.2.22. Tagged as 'Kernel-5_35-4_79_2_98_2_22'
      2b35d8c2
    • Jeffrey Lee's avatar
      Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if... · ed3cc555
      Jeffrey Lee authored
      Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if NVRAM is of type 'MaybeIIC'
      
      Detail:
        s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
      Admin:
        Tested in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.
      
      
      Version 5.35, 4.79.2.109. Tagged as 'Kernel-5_35-4_79_2_109'
      ed3cc555
  17. 24 Jan, 2010 1 commit
    • Jeffrey Lee's avatar
      Migrate 2012 RTC fix to Cortex branch of kernel · 73eefecf
      Jeffrey Lee authored
      Detail:
        s/PMF/osword - Migrate the 2012 RTC fix from the HAL branch to the Cortex branch, plus apply similar fix to the code that handles HAL RTC devices (via new YearLOIsGood flag)
        s/PMF/i2cutils - Update HAL RTC year handling to correctly treat YearLO as either 2-bit int or 2-digit BCD
        hdr/RTCDevice - Add YearLOIsGood flag, revise NeedsYearHelp description
      Admin:
        Tested on rev C2 beagleboard. Code seems to behave as intended.
      
      
      Version 5.35, 4.79.2.98.2.21. Tagged as 'Kernel-5_35-4_79_2_98_2_21'
      73eefecf
  18. 18 Jan, 2010 1 commit
    • John Ballance's avatar
      modified s.PMF.osword to cope with the iyonix RTC operating in BCD · 23e2c1e0
      John Ballance authored
      Also upissued to RISC OS 5.16 to release this in ROM
      Detail:
        (list files and functions that have changed)
      Admin:
      tested at Castle (JB)
        (highlight level of testing that has taken place)
        (bugfix number if appropriate)
      
      
      Version 5.35, 4.79.2.107. Tagged as 'Kernel-5_35-4_79_2_107'
      23e2c1e0
  19. 30 Sep, 2009 1 commit
    • Jeffrey Lee's avatar
      Update Cortex kernel to cope correctly with HAL RTC errors · d08aa9dc
      Jeffrey Lee authored
      Detail:
        The kernel will now attempt to cope with errors returned by HAL RTC devices - For RTC read operations, instead of just loading random garbage, the bad result will now be ignored and the soft 5-byte time left unaltered.
      Admin:
        Tested on rev C2 beagleboard. Year now correctly defaults to 1970 instead of 1900 if the OMAP3 RTC driver returns an error because the RTC isn't running yet.
      
      
      Version 5.35, 4.79.2.98.2.13. Tagged as 'Kernel-5_35-4_79_2_98_2_13'
      d08aa9dc
  20. 23 Jul, 2009 1 commit
    • Jeffrey Lee's avatar
      Add HAL RTC support to Cortex branch of kernel, clean up RTCSupport code · 7f21e480
      Jeffrey Lee authored
      Detail:
        HAL kernels (on the Cortex branch at least) now support HALDevice-based RTCs. If the kernels own RTC code is disabled or fails to detect an RTC, then after HAL_InitDevices is called the HALDevice list will be scanned for any HAL-resident RTC devices.
        Additionally, the RTCSupport flag (in Hdr:Machine.Machine), which was previously TRUE for all HAL kernels, can now be set to FALSE in HAL kernels to disable the kernels own IIC RTC code. This allows the unwanted legacy RTC code to be disabled for machines which are known to use HAL RTCs instead.
        hdr/RTCDevice - new header describing data structures used for HAL RTC device
        hdr/HALDevice - added RTCDevice device type, IIC serial bus type
        hdr/KernelWS - upgraded RTCFitted from a 1 byte field to 4 byte. It now stores either a null value (for no RTC), a value <2048 for an IIC RTC address, or a value >= 2048 for a RTCDevice ptr
        Makefile - added header export of hdr/RTCDevice
        s/GetAll - include hdr/RTCDevice
        s/NewReset - initialise HAL RTC after HAL_InitDevices if required
        s/PMF/i2cutils, s/PMF/osinit, s/PMF/osword - modifications to allow use of HAL RTC (and disallow use of builtin IIC RTC)
      Admin:
        Tested on rev C2 beagleboard
      
      
      Version 5.35, 4.79.2.98.2.11. Tagged as 'Kernel-5_35-4_79_2_98_2_11'
      7f21e480
  21. 17 Jul, 2009 1 commit
  22. 15 Jun, 2009 1 commit
    • Ben Avison's avatar
      Fix bugs and inefficiencies revealed by unaligned data audit · 8a9e694c
      Ben Avison authored
      Detail:
        s.PMF.i2cutils line 454: this LDR of byte values was harmless (bits 8
          upwards are discarded later) but slower than an LDRB on ARMv6 or later.
        s.PMF.i2cutils line 556: should have loaded RTCFitted using LDRB. Looks
          like effect would have been to reduce utilisation of CMOS cache.
        s.vdu.vduswis line 1500: mistakenly accessing ExternalFramestore using LDR.
          I don't think the intention was to prevent the screen DA being resized
          while screen memory was claimed, but that was the effect.
        s.vdu.vduwrch line 3106: this LDR of a 1-byte variable was harmless (only
          used for testing bit 4) but slower than an LDRB on ARMv6 or later.
        CPU version is no longer specified in the makefile - it's better to inherit
        it from the build environment now that we actually set it appropriately.
      Admin:
        Built and briefly tested.
      
      Version 5.35, 4.79.2.98.2.9. Tagged as 'Kernel-5_35-4_79_2_98_2_9'
      8a9e694c
  23. 17 May, 2009 1 commit
    • Ben Avison's avatar
      Miscellaneous v6-related updates · 9d9aa41b
      Ben Avison authored
      Detail:
       * Stopped calling the broken abort fixup code when running under VMSAv6.
         Might be desirable to update it, possibly farmed out to a separate module -
         still need to think about this.
       * Unaligned load optimisations can now be disabled by the global NoUnaligned
         flag for testing purposes.
       * Extended OS_ReadUnsigned to permit reading of 64-bit unsigned integers.
         See Docs.ReadUnsigned for more details. Also sped it up by using MLA
         (or UMLAL) for most digits rather than repeated addition.
       * Bugfix is OS_GSRead: an uninitialised r0 was being passed to
         OS_ReadUnsigned, causing undesirable effects on rare occasions.
      Admin:
        Tested on a rev B7 beagleboard.
      
      Version 5.35, 4.79.2.98.2.8. Tagged as 'Kernel-5_35-4_79_2_98_2_8'
      9d9aa41b
  24. 10 May, 2009 1 commit
    • Ben Avison's avatar
      Unaligned loads/stores optimised for ARMv6+ · 70865f8b
      Ben Avison authored
      Detail:
        Having scanned the kernel source for unaligned load code fragments which
        would abort on ARMv6 and v7 and not having found any, I took the opportunity
        to give them build-time switches to use unaligned LDR((S)H)/STR(H)
        instructions if built for a new enough platform. Also added a couple of
        cases of LDRSB that will benefit v4 CPUs and a few instances of the v6
        SXTH instruction, but since objasm doesn't yet understand it (and when it
        does, not everyone will have upgraded) they are currently written as
        DCI statements.
        Most of the changes are to OS_Word handlers, which are notorious in that
        their input/output block is not word-aligned.
      Admin:
        Not tested, but it should at least build.
      
      Version 5.35, 4.79.2.98.2.6. Tagged as 'Kernel-5_35-4_79_2_98_2_6'
      70865f8b
  25. 22 Dec, 2008 1 commit
    • Ben Avison's avatar
      Minor kernel updates · ab08ee91
      Ben Avison authored
      Detail:
        * Added some documentation on previously undocumented HAL calls
        * Corrected NVMemoryFlag_Provision bitmask to match documentation
        * Bugfix: NVMemoryFlag_ProtectAtEnd flag was being ignored
      Admin:
        Not tested
      
      Version 5.35, 4.79.2.98. Tagged as 'Kernel-5_35-4_79_2_98'
      ab08ee91
  26. 21 Mar, 2005 1 commit
  27. 02 Nov, 2004 1 commit
    • John Ballance's avatar
      several mode: · 208da9fd
      John Ballance authored
           1: default ticker based vsync generated whenever no device present to do so
           2: graphicsv handling and spec updated to use the hi 8 bits in the
              reason code (R4) to define the display number. Kernel only knows
              of display 0
      Detail:
      Admin:
           tested castle  castle added ip
      
      
      Version 5.35, 4.79.2.81. Tagged as 'Kernel-5_35-4_79_2_81'
      208da9fd
  28. 08 Sep, 2004 1 commit
  29. 06 Sep, 2004 1 commit
    • John Ballance's avatar
      fix for invalid cmos checksum computation on iyonix new version date for 5.07 · 83827e89
      John Ballance authored
      Detail:
         CheckSumBlock called IIC_OpV to checksum byte 0 of CMOS, but read back the
         resultant checksum from the wrong offset (#20.. new R1 value)..  now
         corrected to #24 as the correct offset (approx line 997).
      
      Admin:
         tested at castle in iyonix
         castle added IP
      
      
      Version 5.35, 4.79.2.74. Tagged as 'Kernel-5_35-4_79_2_74'
      83827e89
  30. 25 Jun, 2004 1 commit
    • Kevin Bracey's avatar
      * Changed some STB switches to Embedded_UI · 0731377c
      Kevin Bracey authored
      * Added use of CDVPoduleIRQs (from Hdr:Machine)
      * Fixed checksum corruption in OS_NVMemory block writes ending just below
        the checksum byte.
      * Fixed R4 corruption by OS_Byte 162 with certain HALs.
      
      Version 5.35, 4.79.2.71. Tagged as 'Kernel-5_35-4_79_2_71'
      0731377c
  31. 21 Jun, 2004 1 commit
    • Ben Avison's avatar
      Bugfixes to OS_Bytes 13 and 14. · 799120d5
      Ben Avison authored
      Detail:
        Event numbers greater than 31 are possible, it's just that OS_GenerateEvent
        doesn't bother cheking the event semaphores for them. However, the value
        returned in R1 from these OS_Bytes always indicated that such events were
        disabled. This suggests that OS_GenerateEvent was not always so, but the
        initials in comments there suggest the change was about RISC OS 3.0.
        The OS_Bytes now correctly reflect OS_GenerateEvent behaviour.
        Another bug fix is that once the event semaphores had saturated at 255,
        OS_Byte 13 was still happy to decrement the semaphore, so for example 256
        enables followed by 255 disables would have disabled the event.
      Admin:
        Not tested.
      
      Version 5.35, 4.79.2.70. Tagged as 'Kernel-5_35-4_79_2_70'
      799120d5
  32. 06 May, 2004 1 commit
    • Kevin Bracey's avatar
      * HAL can choose to limit amount of screen memory to allocate · 0f6941a8
      Kevin Bracey authored
        [Not fully implemented - for now leaves at least 16MB free if only
        one RAM area; was 1MB].
      * Added HAL_USBControllerInfo, HAL_MonitorLeadID and HAL_Video_Render.
      * Added HAL->OS call OS_IICOpV.
      * OS_MMUControl now allows independent control of I and C bits.
      * Added facility to deactivate keyboard debounce (magic word "NoKd" in
        R2 in KeyV 0).
      * Fixed problem with RAM amounts not a multiple of 4MB.
      * Supremacy bit (in VDU 19) now sets all 8 bits of supremacy.
      * Added PaletteV 14 (reads gamma tables).
      * Added Supremacy transfer functions (like gamma correction, but for
        supremacy). Allows easy global supremacy effects in a mode-independent
        fashion. Controlled with PaletteV 15,16.
      * Added modes 50-53 (320x240, 1,2,4,8bpp). Intended for small LCD.
      * Added 13.5kHz versions of TV modes (selected by Hdr:Machine).
      * Upped desktop version to 5.06.
      
      Version 5.35, 4.79.2.66. Tagged as 'Kernel-5_35-4_79_2_66'
      0f6941a8
  33. 02 Dec, 2003 1 commit
    • Ben Avison's avatar
      Fixed bug in KeyV handling: if it was called before the keyboard handler was... · 4248980f
      Ben Avison authored
      Fixed bug in KeyV handling: if it was called before the keyboard handler was installed, it would abort reading from an address that used to be in the logical copy of physical space on an IOMD machine. This manifested itself during software-initiated resets as an abort during ROM init, leaving you with an apparently dead machine.
      
      Version 5.35, 4.79.2.61. Tagged as 'Kernel-5_35-4_79_2_61'
      4248980f
  34. 02 Mar, 2003 1 commit
    • Kevin Bracey's avatar
      OSDelink/RelinkApp now work on the list in opposite orders so that the order... · d5916783
      Kevin Bracey authored
      OSDelink/RelinkApp now work on the list in opposite orders so that the order of vector claims doesn't get toggled.
      
      Fix for *FX5 not working due to a TST having been swapped for CMP.
      Checkprotectionlink option added to HAL version so CMOS lock is
      implemented.
      Updated HAL docs.
      
      Version 5.35, 4.79.2.58. Tagged as 'Kernel-5_35-4_79_2_58'
      d5916783