Review use of StrongARM switch.

Was being used to conditionalise things which aren't really StrongARM related, now should be read as "support split I+D caches" switch.

Version 5.65. Tagged as 'RISC_OSLib-5_65'

VersionASM

@@ -11,13 +11,13 @@
                         GBLS    Module_HelpVersion
                         GBLS    Module_ComponentName
                         GBLS    Module_ComponentPath
-Module_MajorVersion     SETS    "5.64"
-Module_Version          SETA    564
+Module_MajorVersion     SETS    "5.65"
+Module_Version          SETA    565
 Module_MinorVersion     SETS    ""
-Module_Date             SETS    "12 Nov 2011"
-Module_ApplicationDate  SETS    "12-Nov-11"
+Module_Date             SETS    "26 Nov 2011"
+Module_ApplicationDate  SETS    "26-Nov-11"
 Module_ComponentName    SETS    "RISC_OSLib"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Lib/RISC_OSLib"
-Module_FullVersion      SETS    "5.64"
-Module_HelpVersion      SETS    "5.64 (12 Nov 2011)"
+Module_FullVersion      SETS    "5.65"
+Module_HelpVersion      SETS    "5.65 (26 Nov 2011)"
                         END

VersionNum

-/* (5.64)
+/* (5.65)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        5.64
+#define Module_MajorVersion_CMHG        5.65
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                12 Nov 2011
+#define Module_Date_CMHG                26 Nov 2011
 
-#define Module_MajorVersion             "5.64"
-#define Module_Version                  564
+#define Module_MajorVersion             "5.65"
+#define Module_Version                  565
 #define Module_MinorVersion             ""
-#define Module_Date                     "12 Nov 2011"
+#define Module_Date                     "26 Nov 2011"
 
-#define Module_ApplicationDate          "12-Nov-11"
+#define Module_ApplicationDate          "26-Nov-11"
 
 #define Module_ComponentName            "RISC_OSLib"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Lib/RISC_OSLib"
 
-#define Module_FullVersion              "5.64"
-#define Module_HelpVersion              "5.64 (12 Nov 2011)"
-#define Module_LibraryVersionInfo       "5:64"
+#define Module_FullVersion              "5.65"
+#define Module_HelpVersion              "5.65 (26 Nov 2011)"
+#define Module_LibraryVersionInfo       "5:65"

c/armsys

@@ -931,8 +931,8 @@ void _backtrace(int why, int *address, _kernel_unwindblock *uwb)
         _kernel_swi_regs r;
         if (lang[0]=='C' && lang[1]==0) {
             z = (int *)(fp[0] &~ psr_mask);
-/* Note that when I save pc in a STM instruction it points 12 beyond the */
-/* instruction, not just 8! Unless it's a StrongARM or similar.          */
+/* Check that when I save pc in a STM instruction it could save PC+8 or  */
+/* PC+12 beyond the instruction.                                         */
             r.r[0] = 0;
             if (!_kernel_swi(OS_PlatformFeatures, &r, &r) && (r.r[0] & 8))
                 z -= 2;

kernel/s/k_body

@@ -1907,15 +1907,14 @@ default_unwind_handler Keep
 
         LDR     a3, [a4, #frame_entrypc]
         RemovePSRFromReg a3, v1
-        [ StrongARM
+
         STMFD   sp!, {a1-a2}
         MOV     a1, #0
         SWI     XOS_PlatformFeatures
         MOVVS   a1, #0
-        TST     a1, #8
+        TST     a1, #8                  ; Is it PC+8 or PC+12?
         ADDNE   a3, a3, #4
         LDMFD   sp!, {a1-a2}
-        ]
         LDR     v1, [a3, #-12]
 
         ; check that the save mask instruction is indeed the right sort of STM
@@ -2723,18 +2722,16 @@ alloc_return_block
 ; v1 is save area in old frame... will be temp sp in old frame
         ADD     a1, v1, #4*4            ; temp fp in old frame
         LDMDA   fp, {v3-v6}             ; old fp, sp,lr, pc
-        [ StrongARM
+
         STMFD   sp!,{a1-a2}
         MOV     a1,#0
         SWI     XOS_PlatformFeatures
         MOVVS   a1,#0
-        TST     a1,#8
+        TST     a1,#8                   ; Stores PC+8 or PC+12?
         ADREQ   v6, StkOvfPseudoEntry+12
         ADRNE   v6, StkOvfPseudoEntry+8
         LDMFD   sp!,{a1-a2}
-        |
-        ADR     v6, StkOvfPseudoEntry+12
-        ]
+
         STMDA   a1, {v3-v6}             ; new return frame in old chunk...
         ADR     lr, StackOverflowExit
         MOV     a2, sp                  ; saved sp in old frame = NEW sp
@@ -2808,17 +2805,15 @@ DoneArgumentCopy
         STMFD   sp!, {a1, a2, v2-v6}    ; 1st 7 copied frame regs
         LDMDA   v1!, {a1, a2, v2-v6}    ; and the 2nd 7 regs
         STMFD   sp!, {a1, a2, v2-v6}    ; copied to the new frame
+
 ; Now adjust the PC value saved in the old chunk to say "no registers"
-        [ StrongARM
         MOV     a1,#0
         SWI     XOS_PlatformFeatures
         MOVVS   a1,#0
-        TST     a1,#8
+        TST     a1,#8                   ; PC+8 or PC+12?
         ADREQ   v2, StkOvfPseudoEntry+12
         ADRNE   v2, StkOvfPseudoEntry+8
-        |
-        ADR     v2, StkOvfPseudoEntry+12
-        ]
+
         STR     v2, [v1, #26*4]
 ; Set the SP to be FP - requiredFrameSize and return by reloading regs
 ; from where they were saved in the old chunk on entry to STKOVF/N

s/h_StrongA

-; Copyright 1996 Acorn Computers Ltd
-;
-; Licensed under the Apache License, Version 2.0 (the "License");
-; you may not use this file except in compliance with the License.
-; You may obtain a copy of the License at
-;
-;     http://www.apache.org/licenses/LICENSE-2.0
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-
-	GET	Hdr:ListOpts
-	GET	Hdr:Machine.<Machine>
-	GET	Hdr:CPU.Generic26
-	GET	Hdr:Macros
-	GET	Hdr:SWIs
-	GET	Hdr:RISCOS
-
-        GBLL    StrongARM
-	GBLL	SASTMhatbroken
-
-StrongARM	SETL :DEF: AMBKernel
-SASTMhatbroken	SETL {TRUE} :LAND: StrongARM
-
-  [ StrongARM
-        ;macro to synchronise to $Ncodewords words of code on (FD) stack
-        MACRO
-        SyncStackCode $Ncodewords
-        STMFD  sp!,{r0-r2,lr}
-        MOV    r0,#1                    ;means range specified in r1,r2
-        ADD    r1,sp,#4*4               ;start address (allowing for stacked r0-r2,lr)
-        ADD    r2,r1,#($Ncodewords-1)*4 ;end address (inclusive) for $Ncodewords words of code
-        SWI    XOS_SynchroniseCodeAreas ;do the necessary
-        LDMFD  sp!,{r0-r2,lr}
-        MEND
-  ]
-
-        END

s/h_brazil

@@ -36,23 +36,14 @@ LibraryVersionNumber            *       6
 
         GBLL    StrongARM
         GBLL    SASTMhatbroken
-
-StrongARM       SETL :DEF: AMBKernel
+; This switch should be read as the "maybe split caches, don't do dynamic
+; code" switch *only*, other StrongARM things like storing PC+8/PC+12
+; differences must be deduced at run time. In 'kernel.s.swiv' this results
+; in use of OS_CallASWI so as a result the CallASWI module must be loaded
+; for pre RISC OS 3.70 use, and there are a few XOS_SynchroniseCodeAreas too.
+StrongARM       SETL {TRUE}
 SASTMhatbroken  SETL {TRUE} :LAND: StrongARM
 
-  [ StrongARM
-        ;macro to synchronise to $Ncodewords words of code on (FD) stack
-        MACRO
-        SyncStackCode $Ncodewords
-        STMFD  sp!,{r0-r2,lr}
-        MOV    r0,#1                    ;means range specified in r1,r2
-        ADD    r1,sp,#4*4               ;start address (allowing for stacked r0-r2,lr)
-        ADD    r2,r1,#($Ncodewords-1)*4 ;end address (inclusive) for $Ncodewords words of code
-        SWI    XOS_SynchroniseCodeAreas ;do the necessary
-        LDMFD  sp!,{r0-r2,lr}
-        MEND
-  ]
-
 X               EQU     1:SHL:17
 
 ; SWIs common to Brazil and Arthur