GitLab

Detail:
  hdr/Options - ARM6support and GetKernelMEMC values are now derived from the value of MEMM_Type
  s/ARMops, s/HAL - Code to detect and handle ARMv7 CPUs is now only enabled when using VMSAv6 MMU model. Saves us from having to deal with lack of myIMB, myDSB, etc. implementations on pre-ARMv6.
  s/HAL - Removed some debug code
  s/NewReset - Fix bug spotted by Tom Walker where R12 wasn't being restored by LookForHALRTC if a non-HAL RTC had already been found
  s/AMBControl/memmap - correct the assert clause that was checking that &FFE are the correct L2PT protection bits for non-VMSAv6 machines
Admin:
  Tested this kernel on a rev C2 beagleboard & Iyonix softload. Also compiled it into an IOMD ROM, but didn't try running it.


Version 5.35, 4.79.2.98.2.32. Tagged as 'Kernel-5_35-4_79_2_98_2_32'

Detail:
  s/VMSAv6 - The code in DAbPreVeneer that checks for aborting MVA-based cache/TLB ops is now re-entrant.
  This is to cope with the "strange but true" case where a data abort was being triggered by a load/store
  instruction that itself was in an unmapped page.
Admin:
  Tested on rev C2 beagleboard. Fixes issue with StrongED crashing on load (see http://www.riscosopen.org/forum/forums/5/topics/453)
  Still need to work out why CPU was able to execute code from the unmapped page without triggering a prefetch abort (stale cache entries?)


Version 5.35, 4.79.2.98.2.31. Tagged as 'Kernel-5_35-4_79_2_98_2_31'

Detail:
  s/ARMops - Fixed an instance of 'invalidate branch predictor entry' that should have been 'invalidate all branch predictors'
  s/ChangeDyn - Avoid cleaning the Nowhere page when reallocating memory, to avoid incurring the performance hit of the abort handler, and to avoid AMBControl screwing things up by mapping in pages that we're trying to modify
  s/VMSAv6 - Move MVA cache/TLB abort handler to before ChocolateAMB code, to ensure AMBControl doesn't try mapping in pages for harmless cache/TLB op aborts. Also tweaked code to be a little bit faster.
Admin:
  Tested on rev C2 beagleboard. No more lockups when moving screen memory around, for now at least.


Version 5.35, 4.79.2.98.2.30. Tagged as 'Kernel-5_35-4_79_2_98_2_30'

Version 5.35, 4.79.2.98.2.29. Tagged as 'Kernel-5_35-4_79_2_98_2_29'

Detail:
  s/ARMops - previous version of MMU_ChangingEntries_WB_CR7_Lx would behave improperly if cleaning the last page of the address map by neglecting to flush any more than one TLB entry
Admin:
  Untested!


Version 5.35, 4.79.2.98.2.28. Tagged as 'Kernel-5_35-4_79_2_98_2_28'

Update Cortex kernel to use correct instruction/memory barriers and to perform branch target predictor maintenance. Plus tweak default CMOS settings.

Detail:
  hdr/Copro15ops - Added myISB, myDSB, myDMB macros to provide barrier functionality on ARMv6+
  s/ARMops, s/HAL, s/VMSAv6, s/AMBControl/memmap - Correct barrier operations are now performed on ARMv6+ following CP15 writes. Branch predictors are now also maintained properly.
  s/NewReset - Change default CMOS settings so number of CDFS drives is 0 in Cortex builds. Fixes rogue CDFS icon on iconbar.
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.27. Tagged as 'Kernel-5_35-4_79_2_98_2_27'

Detail:
  s/NewReset - boot filing system now defaults to SCSIFS for the CortexA8 machine type. BeagleBoards, etc. should now be able to run their boot sequence if one is placed on a USB mass storage device.
Admin:
  Tested on rev C2 beagleboard.


Version 5.35, 4.79.2.98.2.26. Tagged as 'Kernel-5_35-4_79_2_98_2_26'

Detail:
  hdr/HALDevice, h/HALDevice - inserted the new 'ClearIRQ' entry point into one of the reserved areas.
  Once the RISC OS-side driver has serviced the device's IRQ the ClearIRQ entry point should be called to allow the HAL device to clear any latched interrupt states in intermediate IRQ controllers (e.g. when using GPIO IRQs on OMAP)
  Since this entry point is new, support for it in existing device drivers isn't guaranteed; HAL device implementations of existing APIs must make sure the use a new major version number to indicate that they require ClearIRQ to be called.
  hdr/HALDevice - added some new bus types to represent the GPMC & L3/L4 interconnects in the OMAP.
  hdr/HALDevice - added ethernet NIC device type & IDs for SMSC9221 & DM9000 NICs
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.25. Tagged as 'Kernel-5_35-4_79_2_98_2_25'

Update VDU HAL device for new OMAPVideo driver, fix MVA-based cache/TLB maintenance ops aborting on ARMv7, add warning to VDU driver about inconsistent state variables during screen mode changes

Detail:
  hdr/VideoDevice - removed Address2 and Device2 fields as it makes more sense for them to be in the device specific field (which for OMAP3 is a pointer to an OMAP3-specific struct)
  s/VMSAv6 - Modify data abort handler to ignore aborts that are generated by MVA-based cache/TLB maintenance ops. Unlike earlier ARM architectures, MVA-based ops can abort under ARMv7 if the page has no mapping to a physical address.
  s/vdu/vdudriver - Add a warning about VDU driver state variables (particularly CursorAddr) being left in invalid states during the execution of mode changes. This can cause problems if any attempt is made to output to the screen during the mode change (e.g. as a result of an abort)
Admin:
  Tested on rev C2 beagleboard. Video device changes mean that OMAP3 HAL 0.23 will be needed for ROM compilation to succeed.


Version 5.35, 4.79.2.98.2.24. Tagged as 'Kernel-5_35-4_79_2_98_2_24'

Detail:
  s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
Admin:
  Not tested; however it's identical to the fix applied to the HAL branch


Version 5.35, 4.79.2.98.2.23. Tagged as 'Kernel-5_35-4_79_2_98_2_23'

Fix bug in InitCMOSCache that could cause CMOS to be erroneously reset if NVRAM is of type 'MaybeIIC' (Cortex branch)

Detail:
  s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and then fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
Admin:
  Fix tested in HAL branch in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.


Version 5.35, 4.79.2.98.2.22. Tagged as 'Kernel-5_35-4_79_2_98_2_22'

Detail:
  s/PMF/osword - Migrate the 2012 RTC fix from the HAL branch to the Cortex branch, plus apply similar fix to the code that handles HAL RTC devices (via new YearLOIsGood flag)
  s/PMF/i2cutils - Update HAL RTC year handling to correctly treat YearLO as either 2-bit int or 2-digit BCD
  hdr/RTCDevice - Add YearLOIsGood flag, revise NeedsYearHelp description
Admin:
  Tested on rev C2 beagleboard. Code seems to behave as intended.


Version 5.35, 4.79.2.98.2.21. Tagged as 'Kernel-5_35-4_79_2_98_2_21'

Version 5.35, 4.79.2.98.2.20. Tagged as 'Kernel-5_35-4_79_2_98_2_20'

Version 5.35, 4.79.2.98.2.19. Tagged as 'Kernel-5_35-4_79_2_98_2_19'

Detail:
  LookForHALRTC wasn't initialising R12 to point to the OS Byte workspace before calling CheckYear, and instead relying on the previous value. This resulted in the RTC initialisation breaking once HAL_InitDevices started doing things to corrupt R12.
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.18. Tagged as 'Kernel-5_35-4_79_2_98_2_18'

Detail:
  Makefile rule was missing for VideoDevice header export, preventing it from being exported
Admin:
  Tested on rev C2 beagleboard. (No, really, I mean it this time!)


Version 5.35, 4.79.2.98.2.17. Tagged as 'Kernel-5_35-4_79_2_98_2_17'

Detail:
  hdr/VideoDevice, Makefile - Add initial version of header for video HAL devices
  hdr/HALDevice - Add device IDs for OMAP3 DMA & video devices.
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.16. Tagged as 'Kernel-5_35-4_79_2_98_2_16'

Fix bug when creating code variables via OS_SetVarVal, remove errant line from s.ARM600, automatically enable alignment exceptions if NoUnaligned is TRUE (Cortex branch)

Detail:
  s/ARM600 - Removed an errant line that could have caused problems if the ARM600 MMU model was used with the WB_CR7_Lx cache type
  s/Arthur2 - OS_SetVarVal was failing to call XOS_SynchroniseCodeAreas after copying the code variables code block into the system heap. This has now been fixed.
  s/HAL - Alignment exceptions are now automatically enabled when the kernel is built with the NoUnaligned option turned on.
Admin:
  Tested on rev C2 beagleboard. OS_SetVarVal fix means the Debugger module now shows the right register names instead of ofla!


Version 5.35, 4.79.2.98.2.15. Tagged as 'Kernel-5_35-4_79_2_98_2_15'

Fix error handling for sparse dynamic area resize operations, increase Cortex kernel version number to 5.15

Detail:
  s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encountered during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
  Version - Update kernel version/date to 5.15, to match current HAL version. This change is to allow modules to properly detect whether the kernel has the sparse dynamic area fix - it does not (yet) mean that the Cortex kernel contains all the features of the current development HAL kernel!
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.14. Tagged as 'Kernel-5_35-4_79_2_98_2_14'

Detail:
  The kernel will now attempt to cope with errors returned by HAL RTC devices - For RTC read operations, instead of just loading random garbage, the bad result will now be ignored and the soft 5-byte time left unaltered.
Admin:
  Tested on rev C2 beagleboard. Year now correctly defaults to 1970 instead of 1900 if the OMAP3 RTC driver returns an error because the RTC isn't running yet.


Version 5.35, 4.79.2.98.2.13. Tagged as 'Kernel-5_35-4_79_2_98_2_13'

Detail:
  The host-mode driver for the MUSB OTG controller is now working, so there's no longer any reason to have the DebugTerminal enabled by default.
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.12. Tagged as 'Kernel-5_35-4_79_2_98_2_12'

Detail:
  HAL kernels (on the Cortex branch at least) now support HALDevice-based RTCs. If the kernels own RTC code is disabled or fails to detect an RTC, then after HAL_InitDevices is called the HALDevice list will be scanned for any HAL-resident RTC devices.
  Additionally, the RTCSupport flag (in Hdr:Machine.Machine), which was previously TRUE for all HAL kernels, can now be set to FALSE in HAL kernels to disable the kernels own IIC RTC code. This allows the unwanted legacy RTC code to be disabled for machines which are known to use HAL RTCs instead.
  hdr/RTCDevice - new header describing data structures used for HAL RTC device
  hdr/HALDevice - added RTCDevice device type, IIC serial bus type
  hdr/KernelWS - upgraded RTCFitted from a 1 byte field to 4 byte. It now stores either a null value (for no RTC), a value <2048 for an IIC RTC address, or a value >= 2048 for a RTCDevice ptr
  Makefile - added header export of hdr/RTCDevice
  s/GetAll - include hdr/RTCDevice
  s/NewReset - initialise HAL RTC after HAL_InitDevices if required
  s/PMF/i2cutils, s/PMF/osinit, s/PMF/osword - modifications to allow use of HAL RTC (and disallow use of builtin IIC RTC)
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.11. Tagged as 'Kernel-5_35-4_79_2_98_2_11'

Detail:
  s/PMF/IIC - IICIRQ now calls HAL_IRQClear after HAL_IICMonitorTransfer, in order to make sure the IRQ controller is restarted.
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.10. Tagged as 'Kernel-5_35-4_79_2_98_2_10'

Detail:
  s.PMF.i2cutils line 454: this LDR of byte values was harmless (bits 8
    upwards are discarded later) but slower than an LDRB on ARMv6 or later.
  s.PMF.i2cutils line 556: should have loaded RTCFitted using LDRB. Looks
    like effect would have been to reduce utilisation of CMOS cache.
  s.vdu.vduswis line 1500: mistakenly accessing ExternalFramestore using LDR.
    I don't think the intention was to prevent the screen DA being resized
    while screen memory was claimed, but that was the effect.
  s.vdu.vduwrch line 3106: this LDR of a 1-byte variable was harmless (only
    used for testing bit 4) but slower than an LDRB on ARMv6 or later.
  CPU version is no longer specified in the makefile - it's better to inherit
  it from the build environment now that we actually set it appropriately.
Admin:
  Built and briefly tested.

Version 5.35, 4.79.2.98.2.9. Tagged as 'Kernel-5_35-4_79_2_98_2_9'

Detail:
 * Stopped calling the broken abort fixup code when running under VMSAv6.
   Might be desirable to update it, possibly farmed out to a separate module -
   still need to think about this.
 * Unaligned load optimisations can now be disabled by the global NoUnaligned
   flag for testing purposes.
 * Extended OS_ReadUnsigned to permit reading of 64-bit unsigned integers.
   See Docs.ReadUnsigned for more details. Also sped it up by using MLA
   (or UMLAL) for most digits rather than repeated addition.
 * Bugfix is OS_GSRead: an uninitialised r0 was being passed to
   OS_ReadUnsigned, causing undesirable effects on rare occasions.
Admin:
  Tested on a rev B7 beagleboard.

Version 5.35, 4.79.2.98.2.8. Tagged as 'Kernel-5_35-4_79_2_98_2_8'

Detail:
  s/vdu/vduwrch - Modify PageTest to never use paged scrolling when DebugTerminal is true (since serial terminals aren't able to send shift up/down messages)
Admin:
  Tested on rev C2 beagleboard.


Version 5.35, 4.79.2.98.2.7. Tagged as 'Kernel-5_35-4_79_2_98_2_7'

Detail:
  Having scanned the kernel source for unaligned load code fragments which
  would abort on ARMv6 and v7 and not having found any, I took the opportunity
  to give them build-time switches to use unaligned LDR((S)H)/STR(H)
  instructions if built for a new enough platform. Also added a couple of
  cases of LDRSB that will benefit v4 CPUs and a few instances of the v6
  SXTH instruction, but since objasm doesn't yet understand it (and when it
  does, not everyone will have upgraded) they are currently written as
  DCI statements.
  Most of the changes are to OS_Word handlers, which are notorious in that
  their input/output block is not word-aligned.
Admin:
  Not tested, but it should at least build.

Version 5.35, 4.79.2.98.2.6. Tagged as 'Kernel-5_35-4_79_2_98_2_6'

Detail:
  s/ARMops - Fix IMB_Range_WB_CR7_Lx to clean the correct number of cache lines
  s/HAL - Change CP15 control register flags so unaligned loads are enabled on ARMv6 (to simplify support for ARMv7 where unaligned loads are always enabled, and to match the behaviour expected by the example code in Hdr:CPU.Arch)
  s/AMBControl/memmap - Make AMB_LazyFixUp use the correct L2PT protection flags depending on ARM600/VMSAv6 MMU model. Also guard against problems caused by future L2PT flag changes.
  s/vdu/vdugrafj - Fix previously undiscovered 32bit incompatability in GetSprite (OS_SpriteOp 14/16)
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.5. Tagged as 'Kernel-5_35-4_79_2_98_2_5'

Detail:
  s/ARMops - Fix set/way-based cache ops for cache type WB_CR7_Lx to iterate sets/ways/cache levels properly
  s/HAL - Fix HAL_InvalidateCache_ARMvF to iterate sets/ways/cache levels properly
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.4. Tagged as 'Kernel-5_35-4_79_2_98_2_4'

Detail:
  s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
  s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
  s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
  s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
  s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
  s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
  hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
Admin:
  Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.


Version 5.35, 4.79.2.98.2.3. Tagged as 'Kernel-5_35-4_79_2_98_2_3'

Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate, use CPU feature registers to identify CPU capabilities.

Detail:
  s/ARMops - Support for Cortex multi-level cache (CT_ctype_WB_CR7_Lx). New ARM_Analyse_Fancy to identify CPU capabilities using feature registers.
  s/HAL - Modify pre-ARMop cache code to handle Cortex-syle caches.
  s/MemInfo - Replace ARM_flush_TLB macro call with appropriate ARMop to provide Cortex compatability
  hdr/ARMops - Update list of ARM architectures
  hdr/CoPro15ops - Deprecate ARM_flush_* macros for HAL kernels, as they are no longer capable of flushing all cache types. ARMops should be used instead.
  hdr/KernelWS - Add storage space for multi-level cache properties required for new cache cleaning code.
Admin:
  Tested under qemu-omap3. Still unable to verify on real hardware due to lack of appropriate MMU code. However new OMAP3 HAL code that uses similar cache management functions appears to work fine on real hardware.


Version 5.35, 4.79.2.98.2.2. Tagged as 'Kernel-5_35-4_79_2_98_2_2'

Detail:
  hdr/ARMops - Added Cortex_A8 processor type, new ARM architecture number
  hdr/Options - Enabled various kernel debug options
  s/ARMops - Added Cortex-A8/OMAP3530 to known CPUs list. Ignore cache type register for ARM architecture &F.
  s/NewIRQs - Increase MaxInterrupts to 96
Admin:
  Brief testing under qemu-omap3.



Version 5.35, 4.79.2.98.2.1. Tagged as 'Kernel-5_35-4_79_2_98_2_1'

Detail:
  * Added some documentation on previously undocumented HAL calls
  * Corrected NVMemoryFlag_Provision bitmask to match documentation
  * Bugfix: NVMemoryFlag_ProtectAtEnd flag was being ignored
Admin:
  Not tested

Version 5.35, 4.79.2.98. Tagged as 'Kernel-5_35-4_79_2_98'

Version 5.35, 4.79.2.97. Tagged as 'Kernel-5_35-4_79_2_97'

Detail:
  Updated GraphicsV documentation
  Upped ROM version number - currently matches latest Castle release (5.13)
Admin:
  No code change

Version 5.35, 4.79.2.96. Tagged as 'Kernel-5_35-4_79_2_96'

Detail:

Admin:


Version 5.35, 4.79.2.95. Tagged as 'Kernel-5_35-4_79_2_95'

Detail:
Admin:


Version 5.35, 4.79.2.94. Tagged as 'Kernel-5_35-4_79_2_94'

Detail:

Admin:	needed for changed module


Version 5.35, 4.79.2.93. Tagged as 'Kernel-5_35-4_79_2_93'

Detail:

Admin:


Version 5.35, 4.79.2.92. Tagged as 'Kernel-5_35-4_79_2_92'

	no other changes
Detail:
Admin:


Version 5.35, 4.79.2.91. Tagged as 'Kernel-5_35-4_79_2_91'