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Commit e718080c authored by Jeffrey Lee's avatar Jeffrey Lee
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Fix some issues preventing the Cortex kernel from being used on non-Cortex machines 

Detail:
  hdr/Options - ARM6support and GetKernelMEMC values are now derived from the value of MEMM_Type
  s/ARMops, s/HAL - Code to detect and handle ARMv7 CPUs is now only enabled when using VMSAv6 MMU model. Saves us from having to deal with lack of myIMB, myDSB, etc. implementations on pre-ARMv6.
  s/HAL - Removed some debug code
  s/NewReset - Fix bug spotted by Tom Walker where R12 wasn't being restored by LookForHALRTC if a non-HAL RTC had already been found
  s/AMBControl/memmap - correct the assert clause that was checking that &FFE are the correct L2PT protection bits for non-VMSAv6 machines
Admin:
  Tested this kernel on a rev C2 beagleboard & Iyonix softload. Also compiled it into an IOMD ROM, but didn't try running it.


Version 5.35, 4.79.2.98.2.32. Tagged as 'Kernel-5_35-4_79_2_98_2_32'
parent 9aa05feb
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Showing with 41 additions and 51 deletions
VersionASM
View file @ e718080c
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.31"
Module_Date SETS "02 Sep 2010"
Module_ApplicationDate SETS "02-Sep-10"
Module_MinorVersion SETS "4.79.2.98.2.32"
Module_Date SETS "04 Oct 2010"
Module_ApplicationDate SETS "04-Oct-10"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.31)"
Module_HelpVersion SETS "5.35 (02 Sep 2010) 4.79.2.98.2.31"
Module_FullVersion SETS "5.35 (4.79.2.98.2.32)"
Module_HelpVersion SETS "5.35 (04 Oct 2010) 4.79.2.98.2.32"
END
VersionNum
View file @ e718080c
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.31
#define Module_Date_CMHG 02 Sep 2010
#define Module_MinorVersion_CMHG 4.79.2.98.2.32
#define Module_Date_CMHG 04 Oct 2010
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.31"
#define Module_Date "02 Sep 2010"
#define Module_MinorVersion "4.79.2.98.2.32"
#define Module_Date "04 Oct 2010"
#define Module_ApplicationDate "02-Sep-10"
#define Module_ApplicationDate "04-Oct-10"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.31)"
#define Module_HelpVersion "5.35 (02 Sep 2010) 4.79.2.98.2.31"
#define Module_FullVersion "5.35 (4.79.2.98.2.32)"
#define Module_HelpVersion "5.35 (04 Oct 2010) 4.79.2.98.2.32"
#define Module_LibraryVersionInfo "5:35"
hdr/Options
View file @ e718080c
......@@ -219,7 +219,7 @@ SAcleanflushbroken SETL {TRUE} :LAND: StrongARM
SASTMhatbroken SETL {TRUE} :LAND: StrongARM
StrongARM_POST SETL {TRUE} :LAND: StrongARM
ARM6support SETL {FALSE} ; Needs updating for VMSAv6 compatability
ARM6support SETL (MEMM_Type = "ARM600") ; Needs updating for VMSAv6 compatability
XScaleMiniCache SETL {FALSE}
......@@ -406,7 +406,7 @@ GetFlashROM SETS ""
GBLS GetPalette
GBLS GetMemInfo
GBLS GetHAL
GetKernelMEMC SETS "GET s.VMSAv6"
GetKernelMEMC SETS "GET s." :CC: MEMM_Type
GetMemInfo SETS "GET s.MemInfo"
GetPalette SETS "GET s.vdu.vdupalxx"
......
s/AMBControl/memmap
View file @ e718080c
......@@ -109,10 +109,11 @@ AMB_LazyFixUp ROUT
LDR r2,AMBPhysBin
; Calculate the L2PT protection bits in a nice way that won't produce broken code if we change MMU model
; This should match the AP_Full entry from the PPLTrans table that gets used by BangCam (plus C+B bits)
[ MEMM_Type = "VMSAv6"
MOV r3,#(AP_Full*L2X_APMult)+L2_ExtPage+L2_C+L2_B
|
ASSERT (AP_Full*L2X_APMult)+L2_ExtPage+L2_C+L2_B = &FFE
ASSERT (AP_Full*L2_APMult)+L2_SmallPage+L2_C+L2_B = &FFE
MOV r3,#&FF0
ORR r3,r3,#&E
]
......
s/ARMops
View file @ e718080c
......@@ -65,8 +65,10 @@ ARM_Analyse
MOV a2, lr
BL Init_ARMarch
MOV lr, a2
[ MEMM_Type = "VMSAv6"
CMP a1, #ARMvF
BEQ ARM_Analyse_Fancy ; New ARM; use the feature regs to perform all the setup
]
Push "v1,v2,v5,v6,v7,lr"
ARM_read_ID v1
ARM_read_cachetype v2
......@@ -517,6 +519,7 @@ Analyse_WB_Cal_LD
B %FT90
[ MEMM_Type = "VMSAv6"
Analyse_WB_CR7_Lx
TST v5, #CPUFlag_SplitCache
BEQ WeirdARMPanic ; currently, only support harvard caches here
......@@ -612,6 +615,7 @@ Analyse_WB_CR7_Lx
MCR p15, 0, a1, c1, c0, 1
B %FT90
] ; MEMM_Type = "VMSAv6"
90
Pull "v1,v2,v5,v6,v7,pc"
......@@ -742,14 +746,13 @@ KnownCPUFlags
DCD CPUFlag_XScale, 0 ; X80321
DCD CPUFlag_ExtendedPages, 0 ; Cortex_A8
[ MEMM_Type = "VMSAv6"
; --------------------------------------------------------------------------
; ----- ARM_Analyse_Fancy --------------------------------------------------
; --------------------------------------------------------------------------
;
; Although I don't have a copy of the ARMv7 ARM to check, I suspect that all
; ARMs with an architecture of &F implement the feature registers described
; in the Cortex-A8 TRM. Thus, for these new ARMs, we shall use the feature
; registers to discover what the CPU is like.
; For ARMv7 ARMs (arch=&F), we can detect everything via the feature registers
; TODO - There's some stuff in here that can be tidied up/removed
; Things we need to set up:
; ProcessorType (as listed in hdr.ARMops)
......@@ -871,6 +874,7 @@ ARM_Analyse_Fancy
; others ...
B WeirdARMPanic ; stiff :)
] ; MEMM_Type = "VMSAv6"
; --------------------------------------------------------------------------
; ----- ARMops -------------------------------------------------------------
......@@ -1819,6 +1823,7 @@ MMU_ChangingUncachedEntries_WB_Cal_LD ROUT
CPWAIT
MOV pc, lr
[ MEMM_Type = "VMSAv6" ; Need appropriate myIMB, etc. implementations if this is to be removed
; --------------------------------------------------------------------------
; ----- ARMops for Cortex-A8 and the like ----------------------------------
......@@ -2219,6 +2224,8 @@ MMU_ChangingUncachedEntries_WB_CR7_Lx ROUT
myISB
MOV pc, lr
] ; MEMM_Type = "VMSAv6"
; --------------------------------------------------------------------------
......
s/HAL
View file @ e718080c
......@@ -82,10 +82,12 @@ RISCOS_InitARM
; In case it wasn't a hard reset
MOV a2, #0
[ MEMM_Type = "VMSAv6"
CMP a1, #ARMvF
; Assume that all ARMvF ARMs have multi-level caches and thus no single MCR op for invalidating all the caches
MCRNE ARM_config_cp,0,a2,ARMv4_cache_reg,C7 ; invalidate I+D caches
BLEQ HAL_InvalidateCache_ARMvF
]
CMP a1, #ARMv3
MCREQ ARM_config_cp,0,a2,ARMv3_TLBflush_reg,C0 ; flush TLBs
MCRNE ARM_config_cp,0,a2,ARMv4_TLB_reg,C7 ; flush TLBs
......@@ -706,16 +708,19 @@ MMUon_instr
MOVEQ sp, v5
MSREQ CPSR_c, #F32_bit+I32_bit+SVC32_mode
[ MEMM_Type = "VMSAv6"
CMP ip, #ARMvF
MOV lr, #0 ; junk MMU-off contents of I-cache
MCRNE ARM_config_cp,0,lr,ARMv4_cache_reg,C7 ; (works on ARMv3)
MCREQ p15, 0, lr, c7, c5, 0 ; invalidate instruction cache
MCREQ p15, 0, lr, c8, c7, 0 ; invalidate TLBs
MCREQ p15, 0, lr, c7, c5, 6 ; invalidate branch predictor
[ MEMM_Type = "VMSAv6"
myISB ; Ensure below branch works
]
BLEQ HAL_InvalidateCache_ARMvF ; invalidate data cache (and instruction+TLBs again!)
|
MOV lr, #0 ; junk MMU-off contents of I-cache
MCR ARM_config_cp,0,lr,ARMv4_cache_reg,C7 ; (works on ARMv3)
]
MOV ip, #4_0000000000000001 ; domain 0 client only
ARM_MMU_domain ip
......@@ -1041,6 +1046,7 @@ MMUon_nol1ptoverlap
LTORG
[ MEMM_Type = "VMSAv6"
HAL_InvalidateCache_ARMvF
; Cache invalidation for ARMs with multiple cache levels, used before ARMop initialisation
; This function gets called before we have a stack set up, so we've got to preserve as many registers as possible
......@@ -1101,7 +1107,7 @@ HAL_InvalidateCache_ARMvF
MSR CPSR_c, #F32_bit+I32_bit+SVC32_mode
MSR CPSR_cxsf, ip
MOV pc, lr
] ; MEMM_Type = "VMSAv6"
CountPageTablePages ROUT
MOV a1, #ZeroPage
......@@ -1711,9 +1717,13 @@ Init_PageTablesChanged
MOV ip, #0
MCREQ ARM_config_cp,0,ip,ARMv3_TLBflush_reg,C0
MCRNE ARM_config_cp,0,ip,ARMv4_TLB_reg,C7
[ MEMM_Type = "VMSAv6"
CMP a1, #ARMvF
MCRNE ARM_config_cp,0,ip,ARMv4_cache_reg,C7 ; works on ARMv3
BLEQ HAL_InvalidateCache_ARMvF
|
MCR ARM_config_cp,0,ip,ARMv4_cache_reg,C7 ; works on ARMv3
]
MOV pc, a3
......@@ -1923,34 +1933,6 @@ InitProcVecs
InitProcVec_FIQ
DCD 0
InitProcVecsEnd
; Debug InitProcVecs - on an exception they output the PC to a UART
; GET ADFS::4.$.work.riscos.omap3dev.riscos.sources.hal.omap3.hdr.UART
;InitProcVecs
; NOP ; Reset
; NOP ; Undefined instruction
; NOP ; SWI
; NOP ; Prefetch abort
; NOP ; data abort
; NOP ; address exception
; NOP ; IRQ
; NOP ; FIQ
; ADR a3,hextab
; LDR a2,[a3],#4
; MOV a4, #8
;10
; LDRB v1, [a2, #UART_LSR]
; TST v1, #THRE
; BEQ %BT10
; LDRB v1, [a3, lr, LSR #28]
; STRB v1, [a2, #UART_THR]
; MOV lr, lr, LSL #4
; SUBS a4, a4, #1
; BNE %BT10
;20
; B %BT20
;hextab DCD &49020000 ; UART address
; DCB "0123456789abcdef"
;InitProcVecsEnd
;
; In: a1 = flags (L1_B,L1_C,L1_AP,L1_APX)
......
s/NewReset
View file @ e718080c
......@@ -2364,7 +2364,7 @@ LookForHALRTC
MOV R0, #0
LDR R0, [R0, #RTCFitted]
CMP R0, #0
Pull "R0-R2,R8,PC",NE ; We already have an RTC
Pull "R0-R2,R8,R12,PC",NE ; We already have an RTC
LDR R0, =(0:SHL:16)+HALDeviceType_SysPeri+HALDeviceSysPeri_RTC
MOV R1, #0
MOV R8, #4
......
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