1. 07 Jun, 2017 1 commit
    • Jeffrey Lee's avatar
      Initial support for the ExtraBytes VIDC control list item · 90cc1d38
      Jeffrey Lee authored
      Detail:
        The ExtraBytes control list item can be used to add padding between framebuffer rows.
        When the kernel sees a VIDC list containing this item, it will now adjust the LineLength and ScreenSize mode variables accordingly, with the end result that the correct amount of memory will be allocated for the framebuffer and the OS will render into it correctly.
        Files changed:
        - hdr/KernelWS - Add DisplayLineLength variable to allow the correct LineLength value to be preserved when screen output is redirected to a sprite
        - s/vdu/vdudriver - Make ModeChangeSub initialise DisplayLineLength before calling SwitchOutputToSprite. Update PushModeInfo to take ExtraBytes into account when calculating LineLength and ScreenSize.
        - s/vdu/vdugrafl - Adjust SwitchOutputToSprite to use DisplayLineLength when restoring screen output
        - s/vdu/vduwrch - Fix full-screen CLS to not write to the padding bytes
      Admin:
        Tested on Raspberry Pi 3
      
      
      Version 5.82. Tagged as 'Kernel-5_82'
      90cc1d38
  2. 03 Jun, 2017 1 commit
  3. 05 Mar, 2017 1 commit
    • ROOL's avatar
      Extend MonitorType configure keyword · 4d017eb3
      ROOL authored
      Detail:
        Accept a monitortype of 'EDID' (as distinct from 'Auto', which uses the ID pins) to force the kernel, via ScrModes, to use the native screen mode prior to executing the boot sequence.
        Required for discless boot, this also helps if the boot sequence fails, the desktop will be entered in the monitor's native resolution, or a fallback if GraphicsV rejects that.
        The allocation of the EDID monitor type has been carefully selected to degrade to 'Auto' when used with an older OS. That way the configuration in CMOS is safe to use with softloads on top of older physical ROMs.
        When OS_ScreenMode is queried return the 'Auto' type, ie. at an API level there's no distinction.
      Admin:
        Requires HdrSrc-2_67.
        Submission for the EDID bounty.
      
      Version 5.80. Tagged as 'Kernel-5_80'
      4d017eb3
  4. 17 Feb, 2017 1 commit
    • Jeffrey Lee's avatar
      Streamline PL310 ARMops · 79699513
      Jeffrey Lee authored
      Detail:
        Some closer examination of the PL310 TRM reveals that there's no need to poll for completion of maintenance operations if we only use atomic ops.
        Since there's no particular need for us to use the background ops, just rewrite everything to use the atomic ops and get rid of the polling.
        This should also avoid the need for any costly locking in SMP setups.
        File changes:
        - s/ARMops - Updated as above
      Admin:
        Tested on Pandaboard, iMx6
      
      
      Version 5.79. Tagged as 'Kernel-5_79'
      79699513
  5. 11 Feb, 2017 1 commit
    • Jeffrey Lee's avatar
      Fix incorrect OS_SynchroniseCodeAreas call · f1802d76
      Jeffrey Lee authored
      Detail:
        s/Arthur2 - When installing a code system variable, a register fumble resulted in OS_SynchroniseCodeAreas being called with a bogus address range. Fix it.
      Admin:
        Tested on Pandaboard
      
      
      Version 5.78. Tagged as 'Kernel-5_78'
      f1802d76
  6. 09 Feb, 2017 1 commit
    • Robert Sprowson's avatar
      Expose CLREX via OS_PlatformFeatures · a7892833
      Robert Sprowson authored
      To account for ARM changing their minds about how to clear the exclusive lock on different architectures, provide a function pointer with a known good implementation. This is similar to the run of NOPs returned by OS_PlatformFeatures 0 for those that need it.
      If in the future any errata or similar are needed, then there's only 1 place to change it, plus clients don't need their own CPU type detection logic.
      
      Version 5.77. Tagged as 'Kernel-5_77'
      a7892833
  7. 11 Jan, 2017 1 commit
  8. 17 Dec, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix screen redirection when in teletext modes. Fix *ScreenLoad buffer overflow. · 06079048
      Jeffrey Lee authored
      Detail:
        s/vdu/vdugrafl, s/vdu/vduttx - Adjust initialisation & shutdown of TTX workspace to fix workspace being erroneously freed/reinitialised when redirecting output to a sprite
        s/vdu/vdugrafk - If ScreenLoad needs to load one row at a time (e.g. when graphics window width != sprite width), allocate a block from the RMA instead of assuming that ScrLoaBuffer is large enough
        hdr/KernelWS - Get rid of ScrLoaBuffer, and shrink LargeCommon to a suitable size. Frees about 2K of VDU workspace.
        s/GetAll - Move Hdr:Sprite earlier in list of GETs
      Admin:
        Tested on Raspberry Pi
      
      
      Version 5.75. Tagged as 'Kernel-5_75'
      06079048
  9. 15 Dec, 2016 2 commits
    • Jeffrey Lee's avatar
      Teletext fixes · 89fa2c01
      Jeffrey Lee authored
      Detail:
        s/vdu/vdudriver, s/vdu/vdumodes - Re-introduce TTX256 so that 8bpp teletext will be used if no MDF is loaded
        s/vdu/vdudriver - If the video driver didn't support the native mode 7 colour depth, ModePromoTable was swapping it for another mode number, preventing the AltTTX code in FindOKMode from operating. So, skip the ModePromoTable check for mode 7.
        s/vdu/vduswis - Minor correction to alternate teletext mode search; 1<<5 = 32bpp, so stop search at log2bpp of 6
      Admin:
        Tested on Raspberry Pi
      
      
      Version 5.74. Retagged as 'Kernel-5_74'
      89fa2c01
    • Jeffrey Lee's avatar
      Add support for custom teletext modes · 92e90b01
      Jeffrey Lee authored
      Detail:
        This set of changes:
        * Adds support for the T, TX and TY mode string elements (as per RISCOS Ltd)
        * Adds support for entering arbitrary-resolution teletext modes by using mode selector blocks with the Teletext mode flag set
        * ScrRCol and ScrBRow mode variables can be provided in the mode selector in order to restrict the number of text rows/columns in teletext modes (as per RISCOS Ltd)
        * If the rows / columns are restricted in this manner then the text window will be centered on the screen, to try and avoid things looking too ugly (no variable text scaling implemented)
        * For HiResTTX, all colour depths >= 4bpp are now supported by teletext. This essentially makes the TTX256 switch obsolete.
        * If the "native" mode 7 is unavailable then the kernel will try a series of fallback resolutions & colour depths in an effort to find a combination that works
        Known bugs/issues:
        * Teletext column count has a max limit of 255 due to TTXDoubleCounts being a byte array
        * If there's a border around the text window, the border will not be refreshed when changing transparency modes using a VDU 23,18,0 sequence
        * ScreenLoad looks like it can overflow the LargeCommon buffer (no buffer size check) - needs fixing before LargeCommon can be safely shrunk below (Old)TTXMapSize
        File changes:
        - hdr/KernelWS - Make CharWidth non-conditional. Adjust handling of teletext workspace; it's now allocated from the system heap to allow it to cope with arbitrary screen sizes
        - s/vdu/vdu23 - Make CharWidth non-conditional
        - s/vdu/vducursoft - Make CursorTeletext cope with arbitrary colour depths, make CharWidth non-conditional, remove hard-coded teletext values
        - s/vdu/vdudriver - Deal with teletext workspace allocation during ModeChangeSub. Deal with selecting teletext modes (and validating colour depth) in GenerateModeSelectorVars.
        - s/vdu/vdugrafl - Make CharWidth non-conditional. Calculate offset required for text window centering.
        - s/vdu/vdumodes - Remove TTX256
        - s/vdu/vduswis - Try other teletext modes if native mode 7 not available. Extend OS_ScreenMode reason codes to cope with teletext mode strings.
        - s/vdu/vduttx - Update to use dynamic workspace. Replace various hardcoded values with variable lookups. Update character plotting + colour/palette selection to work with true-colour modes if HiResTTX.
        - s/vdu/vduwrch - Move some useful code into a subroutine. Update FastCLS to cope with true-colour teletext. Update AddressR0R1 to cope with text window centering offset. Make CharWidth non-conditional.
      Admin:
        Tested on Raspberry Pi, BB-xM
        VDU 23,18,0 in 256-colour teletext now works correctly (previously 64-colour mode was in use, causing palette update to be ruined by VIDC1-mangling)
      
      
      Version 5.74. Tagged as 'Kernel-5_74'
      92e90b01
  10. 13 Dec, 2016 8 commits
    • Jeffrey Lee's avatar
      Disable public use of new ARMops until ready · 5cfe8f63
      Jeffrey Lee authored
      Detail:
        hdr/OSMisc, s/ARMops - Don't expose the new ARMops via OS_MMUControl 2, they haven't been fully tested/developed yet
      Admin:
        Builds, untested
      
      
      Version 5.73. Tagged as 'Kernel-5_73'
      5cfe8f63
    • Jeffrey Lee's avatar
      Implement some ARM11 errata workarounds · bfd65b5c
      Jeffrey Lee authored
      Detail:
        s/ARMops, s/HAL - Add workarounds for some of the scary errata that were previously weren't dealing with (720013, 716151, 714068)
      Admin:
        Tested on Raspberry Pi 1
      
      
      Version 5.72. Tagged as 'Kernel-5_72'
      bfd65b5c
    • Jeffrey Lee's avatar
      Implement support for cacheable pagetables · 65fa6a28
      Jeffrey Lee authored
      Detail:
        Modern ARMs (ARMv6+) introduce the possibility for the page table walk hardware to make use of the data cache(s) when performing memory accesses. This can significantly reduce the cost of a TLB miss on the system, and since the accesses are cache-coherent with the CPU it allows us to make the page tables cacheable for CPU (program) accesses also, improving the performance of page table manipulation by the OS.
        Even on ARMs where the page table walk can't use the data cache, it's been measured that page table manipulation operations can still benefit from placing the page tables in write-through or bufferable memory.
        So with that in mind, this set of changes updates the OS to allow cacheable/bufferable page tables to be used by the OS + MMU, using a system-appropriate cache policy.
        File changes:
        - hdr/KernelWS - Allocate workspace for storing the page flags that are to be used by the page tables
        - hdr/OSMem - Re-specify CP_CB_AlternativeDCache as having a different behaviour on ARMv6+ (inner write-through, outer write-back)
        - hdr/Options - Add CacheablePageTables option to allow switching back to non-cacheable page tables if necessary. Add SyncPageTables var which will be set {TRUE} if either the OS or the architecture requires a DSB after writing to a faulting page table entry.
        - s/ARM600, s/VMSAv6 - Add new SetTTBR & GetPageFlagsForCacheablePageTables functions. Update VMSAv6 for wider XCBTable (now 2 bytes per element)
        - s/ARMops - Update pre-ARMv7 MMU_Changing ARMops to drain the write buffer on entry if cacheable pagetables are in use (ARMv7+ already has this behaviour due to architectural requirements). For VMSAv6 Normal memory, change the way that the OS encodes the cache policy in the page table entries so that it's more compatible with the encoding used in the TTBR.
        - s/ChangeDyn - Update page table page flag handling to use PageTable_PageFlags. Make use of new PageTableSync macro.
        - s/Exceptions, s/AMBControl/memmap - Make use of new PageTableSync macro.
        - s/HAL - Update MMU initialisation sequence to make use of PageTable_PageFlags + SetTTBR
        - s/Kernel - Add PageTableSync macro, to be used after any write to a faulting page table entry
        - s/MemInfo - Update OS_Memory 0 page flag conversion. Update OS_Memory 24 to use new symbol for page table access permissions.
        - s/MemMap2 - Use PageTableSync. Add routines to enable/disable cacheable pagetables
        - s/NewReset - Enable cacheable pagetables once we're fully clear of the MMU initialision sequence (doing earlier would be trickier due to potential double-mapping)
      Admin:
        Tested on pretty much everything currently supported
        Delivers moderate performance benefits to page table ops on old systems (e.g. 10% faster), astronomical benefits on some new systems (up to 8x faster)
        Stats: https://www.riscosopen.org/forum/forums/3/topics/2728?page=2#posts-58015
      
      
      Version 5.71. Tagged as 'Kernel-5_71'
      65fa6a28
    • Jeffrey Lee's avatar
      Make MMU_Changing ARMops perform the sub-operations in a sensible order · 9a96263a
      Jeffrey Lee authored
      Detail:
        For a while we've known that the correct way of doing cache maintenance on ARMv6+ (e.g. when converting a page from cacheable to non-cacheable) is as follows:
        1. Write new page table entry
        2. Flush old entry from TLB
        3. Clean cache + drain write buffer
        The MMU_Changing ARMops (e.g. MMU_ChangingEntry) implement the last two items, but in the wrong order. This has caused the operations to fall out of favour and cease to be used, even in pre-ARMv6 code paths where the effects of improper cache/TLB management perhaps weren't as readily visible.
        This change re-specifies the relevant ARMops so that they perform their sub-operations in the correct order to make them useful on modern ARMs, updates the implementations, and updates the kernel to make use of the ops whereever relevant.
        File changes:
        - Docs/HAL/ARMop_API - Re-specify all the MMU_Changing ARMops to state that they are for use just after a page table entry h...
      9a96263a
    • Jeffrey Lee's avatar
      Place restrictions on the use of cacheable doubly-mapped DAs · 2704c756
      Jeffrey Lee authored
      Detail:
        The kernel has always allowed software to create cacheable doubly-mapped DAs, despite the fact that the VIVT caches used on ARMv5 and below would have no way of keeping both of the mappings coherent
        This change places restrictions the following restrictions on doubly-mapped areas, to ensure that cache settings which can't be supported by the cache architecture of the CPU can't be selected:
        * On ARMv6 and below, cacheable doubly-mapped areas aren't supported.
          * Although ARMv6 has VIPT data caches, it's also subject to page colouring constraints which would require us to force the DA size to be a multiple of 16k. So for now keep things simple and disallow cacheable doubly-mapped areas on ARMv6.
        * On ARMv7 and above, cacheable doubly-mapped areas are allowed, but only if they are marked non-executable
          * The blocker to allowing executable cacheable doubly-mapped areas are the VIPT instruction caches; OS_SynchroniseCodeAreas (or callers of it) would need to know that a doubly-mapped area is in use so that they can flush both mappings from the I-cache. Although some chips do have PIPT instruction caches, again it isn't really worth supporting executable cacheable doubly-mapped areas at the moment.
        These changes also allow us to get rid of the expensive 'sledgehammer' logic when dealing with doubly-mapped areas
        File changes:
        - s/ARM600, s/VMSAv6 - Remove the sledgehammer logic, only perform cache/TLB maintenance for the required areas
        - s/ChangeDyn - Implement the required checks
        - s/MemMap2 - Move some cache maintenance logic into RemoveCacheabilityR0ByMinusR2, which previously would have had to be performed by the caller due to the sledgehammer paranoia
      Admin:
        Cacheable doubly-mapped DAs tested on iMx6 (tried making screen memory write-through cacheable; decent performance gain seen)
        Note OS_Memory 0 "make temporarily uncacheable" doesn't work on doubly-mapped areas, so cacheable doubly-mapped areas are not yet safe for general DMA
      
      
      Version 5.69. Tagged as 'Kernel-5_69'
      2704c756
    • Jeffrey Lee's avatar
      Add new ARMops. Add macros which map the ARMv7/v8 cache/TLB maintenance... · 48485eee
      Jeffrey Lee authored
      Add new ARMops. Add macros which map the ARMv7/v8 cache/TLB maintenance mnemonics (as featured in recent ARM ARMs) to MCR ops.
      
      Detail:
        - Docs/HAL/ARMop_API - Document the new ARMops. These ops are intended to help with future work (DMA without OS_Memory 0 "make temp uncacheable", and minimising cache maintenance when unmapping pages) and aren't in use just yet.
        - hdr/Copro15ops - Add new macros for ARMv7+ which map the mnemonics seen in recent ARM ARMs to the corresponding MCR ops. This should make things easier when cross-referencing docs and reduce the risk of typos.
        - hdr/KernelWS - Shuffle kernel workspace a bit to make room for the new ARMops
        - hdr/OSMisc - Expose new ARMops via OS_MMUControl 2
        - s/ARMops - Implement the new ARMops. Change the ARMv7+ ARMops to use the new mnemonic macros. Also get rid of myDSB / myISB usage from ARMv7+ code paths; use DSB/ISB/etc. directly to ensure correct behaviour
        - s/HAL - Mnemonic + ISB/DSB updates. Change software RAM clear to do 16 bytes at a time for kernel workspace instead of 32 to allow the kernel workspace tweaks to work.
      Admin:
        Binary diff shows that mnemonics map to the original MCR ops correctly
        Note: Raspberry Pi builds will now emit lots of warnings due to increased DSB/ISB instruction use. However it should be safe to ignore these as they should only be present in v7+ code paths.
        Note: New ARMops haven't been tested yet, will be disabled (or at least hidden from user code) in a future checkin
      
      
      Version 5.68. Tagged as 'Kernel-5_68'
      48485eee
    • Jeffrey Lee's avatar
      Make s/ChangeDyn slightly more readable by splitting some routines out into a separate file · 4a6150dc
      Jeffrey Lee authored
      Detail:
        s/MemMap2 - New file containing assorted low-level memory mapping routines taken from s/ChangeDyn. N.B. There's no special significance to this being named "MemMap2", it's just a name that stuck due to some earlier (abandoned) changes which added a file named "MemMap".
        s/ChangeDyn - Remove the routines/chunks of code that were moved to s/MemMap2. Also some duplicate code removal (Regular DA grow code and DoTheGrowNotSpecified are now rely on the new DoTheGrowCommon routine for doing the actual grow)
        s/GetAll - GET s/MemMap2 at an appropriate time
      Admin:
        Tested on pretty much everything currently supported
      
      
      Version 5.67. Tagged as 'Kernel-5_67'
      4a6150dc
    • Jeffrey Lee's avatar
      Reimplement AMBControl ontop of the PMP system · cefb4815
      Jeffrey Lee authored
      Detail:
        With this set of changes, each AMB node is now the owner of a fake DANode which is linked to a PMP.
        From a user's perspective the behaviour of AMBControl is the same as before, but rewriting it to use PMPs internally offers the following (potential) benefits:
        * Reduction in the amount of code which messes with the CAM & page tables, simplifying future work/maintenance. Some of the AMB ops (grow, shrink) now just call through to OS_ChangeDynamicArea. However all of the old AMB routines were well-optimised, so to avoid a big performance hit for common operations not all of them have been removed (e.g. mapslot / mapsome). Maybe one day these optimal routines will be made available for use by regular PMP DAs.
        * Removal of the slow Service_MemoryMoved / Service_PagesSafe handlers that had to do page list fixup after the core kernel had reclaimed/moved pages. Since everything is a PMP, the kernel will now deal with this on behalf of AMB.
        * Removal of a couple of other slow code paths (e.g. Do_AMB_MakeUnsparse calls from OS_ChangeDynamicArea)
        * Potential for more flexible mapping of application space in future, e.g. sparse allocation of memory to the wimp slot
        * Simpler transition to an ASID-based task swapping scheme on ARMv6+?
        Other changes of note:
        * AMB_LazyMapIn switch has been fixed up to work correctly (i.e. turning it off now disables lazy task swapping and all associated code instead of producing a build error)
        * The DANode for the current app should be accessed via the GetAppSpaceDANode macro. This will either return the current AMB DANode, or AppSpaceDANode (if e.g. pre-Wimp). However be aware that AppSpaceDANode retains the legacy behaviour of having a base + size relative to &0, while the AMB DANodes (identifiable via the PMP flag) are sane and have their base + size relative to &8000.
        * Mostly-useless DebugAborts switch removed
        * AMBPhysBin (page number -> phys addr lookup table) removed. Didn't seem to give any tangible performance benefit, and was imposing hidden restrictions on memory usage (all phys RAM fragments in PhysRamTable must be multiple of 512k). And if it really was a good optimisation, surely it should have been applied to all areas of the kernel, not just AMB!
        Other potential future improvements:
        * Turn the fake DANodes into real dynamic areas, reducing the amount of special code needed in some places, but allow the DAs to be hidden from OS_DynamicArea 3 so that apps/users won't get too confused
        * Add a generic abort trapping system to PMPs/DAs (lazy task swapping abort handler is still a special case)
        File changes:
        - s/ARM600, s/VMSAv6, s/ExtraSWIs - Remove DebugAborts
        - s/ArthurSWIs - Remove AMB service call handler dispatch
        - s/ChangeDyn - AMB_LazyMapIn switch fixes. Add alternate internal entry points for some PMP ops to allow the DANode to be specified (used by AMB)
        - s/Exceptions - Remove DebugAborts, AMB_LazyMapIn switch fixes
        - s/Kernel - Define GetAppSpaceDANode macro, AMB_LazyMapIn switch fix
        - s/MemInfo - AMB_LazyMapIn switch fixes
        - s/AMBControl/AMB - Update GETs
        - s/AMBControl/Memory - Remove block size quantisation, AMB_BlockResize (page list blocks are now allocated by PMP code)
        - s/AMBControl/Options - Remove PhysBin definitions, AMBMIRegWords (moved to Workspace file), AMB_LimpidFreePool switch. Add AMB_Debug switch.
        - s/AMBControl/Workspace - Update AMBNode to contain an embedded DANode. Move AMBMIRegWords here from Options file.
        - s/AMBControl/allocate - Fake DA node initialisation
        - s/AMBControl/deallocate - Add debug output
        - s/AMBControl/growp, growshrink, mapslot, mapsome, shrinkp - Rewrite to use PMP ops where possible, add debug output
        - s/AMBControl/main - Remove PhysBin initialisation. Update the enumerate/mjs_info call.
        - s/AMBControl/memmap - Low-level memory mapping routines updated or rewritten as appropriate.
        - s/AMBControl/readinfo - Update to cope with DANode
        - s/AMBControl/service - Remove old service call handlers
        - s/AMBControl/handler - DA handler for responding to PMP calls from OS_ChangeDynamicArea; just calls through to growpages/shrinkpages as appropriate.
      Admin:
        Tested on pretty much everything currently supported
      
      
      Version 5.66. Tagged as 'Kernel-5_66'
      cefb4815
  11. 04 Dec, 2016 1 commit
  12. 25 Nov, 2016 1 commit
    • Robert Sprowson's avatar
      Issue Service_ModulePostInit when really post init · fc32d45b
      Robert Sprowson authored
      Previously, the service call was sent when the module was in the service call chain/command table hash/SWI table hash, but not actually in the list of modules - so any recipient trying to look something up with OS_Module would get denial that the module existed.
      Move the service call issue step to *after* it's linked into the module list.
      
      Version 5.64. Tagged as 'Kernel-5_64'
      fc32d45b
  13. 26 Oct, 2016 1 commit
  14. 17 Oct, 2016 1 commit
    • Jeffrey Lee's avatar
      Prevent disabling of the D-cache on Cortex-A53. Other OS_MMUControl 0 fixes. · d7299988
      Jeffrey Lee authored
      Detail:
        On Cortex-A53, a load/store exclusive instruction will abort if it targets non-cacheable memory or if the D-cache is disabled. Since the correct operation of these instructions is important to the OS and apps, it makes sense to prevent *Cache Off / OS_MMUControl 0 from being able to disable the D-cache on such systems.
        hdr/OSMisc, s/ARMops - Add new OS_PlatformFeatures 0 flag to indicate when disabling of the D-cache isn't allowed
        s/VMSAv6 - Update MMUControl_ModifyControl to force the D-cache to always be on when the "unsafe to disable D-cache" PlatformFeatures flag is set. Also, disallow mismatched I+D cache settings if we have an L2 cache (causes issues due to IMB ops only flushing to PoU), and fix dangerous D-cache invalidation when it's only the I-cache which is being disabled
        s/ARM600 - Clean up MMUControl_ModifyControl a bit so that it's a closer match to the VMSAv6 version, and fix the dangerous D-cache invalidation.
      Admin:
        Tested on ARM11, Cortex-A7, Cortex-A53
      
      
      Version 5.62. Tagged as 'Kernel-5_62'
      d7299988
  15. 09 Oct, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix wrong XCBTable being used for pre-rev T StrongARMs. Update HAL UART API docs. · fe59a83a
      Jeffrey Lee authored
      Detail:
        s/ARMops - Fix pre-rev T StrongARMs using the wrong XCBTable, causing invalid page flags to be used for the write-through cache policy
        Docs/HAL/Serial - Update HAL UART API docs. Mostly filling in some blanks, but also correcting a couple of things, and documenting new Features bit 4, LineStatus bit 8, and the effect on InterruptID.
      Admin:
        Tested on pre-rev T StrongARM RiscPC
      
      
      Version 5.61. Tagged as 'Kernel-5_61'
      fe59a83a
  16. 13 Sep, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix CAM indexing in DoTheGrowPageUnavailable · f6403cd5
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn - A routine that was missed during the upgrade from 8 byte CAM entries to 16 byte CAM entries, DoTheGrowPageUnavailable was using still using the old CAM entry size, potentially corrupting the CAM whenever it was called (i.e. if a DA grow requested a page that had already been claimed for exclusive use by someone else)
      Admin:
        Tested on BB-xM
      
      
      Version 5.60. Tagged as 'Kernel-5_60'
      f6403cd5
  17. 08 Sep, 2016 1 commit
    • Jeffrey Lee's avatar
      Build fix · 4443154d
      Jeffrey Lee authored
      Detail:
        s/ARM600 - Update ARM600 version of GetTempUncache to not check $temp constraints if $temp not supplied
      Admin:
        Tungsten/IOMD kernel now builds OK
      
      
      Version 5.59. Retagged as 'Kernel-5_59'
      4443154d
  18. 07 Sep, 2016 1 commit
    • Jeffrey Lee's avatar
      Misc memory management fixes · 2f224a37
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn - Fix register corruption in PMP_LogOp when mapping a page into a location that already contains a page. Fix excessive TLB flush in AreaShrink.
        s/ARM600, s/VMSAv6 - Add asserts to GetTempUncache to detect invalid register combinations
      Admin:
        Tested on BB-xM
      
      
      Version 5.59. Tagged as 'Kernel-5_59'
      2f224a37
  19. 23 Aug, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix stack imbalance and incorrect return value in OS_DynamicArea 23 (PMP resize) · d181963e
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn - When OS_DynamicArea 23 returned an error, R2 wasn't being set to zero correctly, incorrectly suggesting that a change had been made. And when a non-error resize of zero was being performed, registers were being pulled twice, resulting in a stack imbalance and crash.
      Admin:
        Tested on BB-xM
      
      
      Version 5.58. Tagged as 'Kernel-5_58'
      d181963e
  20. 18 Aug, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix OS_FindMemMapEntries · d5e09872
      Jeffrey Lee authored
      Detail:
        s/ChangeDyn - Since the introduction of the 16 byte CAM entry format, OS_FindMemMapEntries has contained a bug where requesting the details for an address which does not have an L2PT page allocated for it (e.g. a location in ROM) would result in a misaligned CAM entry pointer being generated, resulting in either a crash or incorrect data being returned
      Admin:
        Tested on Raspberry Pi 2
        Fixes issue reported on forums:
        https://www.riscosopen.org/forum/forums/4/topics/6393
      
      
      Version 5.57. Tagged as 'Kernel-5_57'
      d5e09872
  21. 08 Aug, 2016 1 commit
  22. 02 Aug, 2016 2 commits
    • Jeffrey Lee's avatar
      Add support for shareable pages and additional access privileges · 9cd4cbe4
      Jeffrey Lee authored
      Detail:
        This set of changes:
        * Refactors page table entry encoding/decoding so that it's (mostly) performed via functions in the MMU files (s.ARM600, s.VMSAv6) rather than on an ad-hoc basis as was the case previously
        * Page table entry encoding/decoding performed during ROM init is also handled via the MMU functions, which resolves some cases where the wrong cache policy was in use on ARMv6+
        * Adds basic support for shareable pages - on non-uniprocessor systems all pages will be marked as shareable (however, we are currently lacking ARMops which broadcast cache maintenance operations to other cores, so safe sharing of cacheable regions isn't possible yet)
        * Adds support for the VMSA XN flag and the "privileged ROM" access permission. These are exposed via RISC OS access privileges 4 and above, taking advantage of the fact that 4 bits have always been reserved for AP values but only 4 values were defined
        * Adds OS_Memory 17 and 1...
      9cd4cbe4
    • Robert Sprowson's avatar
      Remove a dead function · 72a424b7
      Robert Sprowson authored
      CheckBits is a hangover from when the kernel used to read the monitor ID lines on a Risc PC, no longer called with a HAL.
      72a424b7
  23. 24 Jul, 2016 1 commit
    • Robert Sprowson's avatar
      Resolve 2x header clashes · 8cfe216b
      Robert Sprowson authored
      hdr/AHCIDevice:
        Remove this, since it clashes with the (differing API version number) copy exported by SATADriver. Post merging the Kernel back to the trunk the newer file datestamp has meant the wrong one gets exported during any ROM build which includes both components. Since the Kernel doesn't need AHCIDevice itself, it is left to the respective client (SATADriver or AHCIDriver in this case) to export them.
      hdr/ModHand:
        Resolve the longstanding clash of Module_Title with the same named symbol that CMHG uses. There are very few assembler needing to look at the module header (Kernel, FileCore, Debugger, Podule) directly, but every C module which uses CMHG and wants one of the ModHandReason values ends up with a duplicate define.
        Obsolete Arthur era Module_LoadAddr value.
      ArthurSWIs.s/MoreComms.s/NewReset.s/SWINaming.s/SysComms.s/Utility.s:
        Module_Title->Module_TitleStr.
      ModHand.s:
        Module_Title->Module_TitleStr.
        Recode Module_LoadAddr using the file type from Hdr:FileTypes.
      GetAlls.s:
        Drop unused NVRAM and PortMan headers. Add Hdr:FileTypes.
      
      Version 5.54. Tagged as 'Kernel-5_54'
      8cfe216b
  24. 15 Jul, 2016 1 commit
    • Robert Sprowson's avatar
      Improve handling of *DUMPing a stream · cf929f7e
      Robert Sprowson authored
      The checks in *DUMP tried to spot a stream (ie. a file that can be opened with OS_Find but that OS_File 5 doesn't think is there), but in doing so never set the address or offset, so the hex values shown on the left of the screen would be whatever junk was in r2 & r3.
      Reorder the tests so it starts at 0 and runs until EOF.
      Make use of OSFile_ReadWithType rather than trying to deduce if it's an untyped file ourselves.
      Tested with
        *DUMP random:
      from SystemDevs-1_33.
      
      Version 5.53. Tagged as 'Kernel-5_53'
      cf929f7e
  25. 30 Jun, 2016 5 commits
    • Jeffrey Lee's avatar
      Tidy things up a bit · 055b24c3
      Jeffrey Lee authored
      Detail:
        hdr/Options - Reduce the scope of SASTMhatbroken and InterruptDelay switches so that they're only enabled when we're building for ARMv4 targets
        s/ARM600, s/VMSAv6, s/ExtraSWIs, s/Exceptions - Move duplicate code out of s/ARM600 & s/VMSAv6 and into shared locations. OS_UpdateMEMC, the bulk of OS_MMUControl, and OS_SynchroniseCodeAreas are now located in s/ExtraSWIs. Meanwhile the data & prefetch abort veneers have been moved to the new file s/Exceptions. s/ARM600 and s/VMSAv6 are now almost purely to do with the different page table formats.
        s/GetAll - GET s/Exceptions
      Admin:
        Tested on Raspberry Pi
      
      
      Version 5.52. Tagged as 'Kernel-5_52'
      055b24c3
    • Jeffrey Lee's avatar
      Delete lots of old switches · f655fcf6
      Jeffrey Lee authored
      Detail:
        This change gets rid of the following switches from the source (picking appropriate code paths for a 32bit HAL build):
        * FixCallBacks
        * UseProcessTransfer
        * CanLiveOnROMCard
        * BleedinDaveBell
        * NewStyleEcfs
        * DoVdu23_0_12
        * LCDPowerCtrl
        * HostVdu
        * Print
        * EmulatorSupport
        * TubeInfo
        * AddTubeBashers
        * TubeChar, TubeString, TubeDumpNoStack, TubeNewlNoStack macros
        * FIQDebug
        * VCOstartfix
        * AssemblingArthur (n.b. still defined for safety with anything in Hdr: which uses it, but not used explicitly by the kernel)
        * MouseBufferFix
        * LCDInvert
        * LCDSupport
        * DoInitialiseMode
        * Interruptible32bitModes
        * MouseBufferManager
        * StrongARM (new CacheCleanerHack and InterruptDelay switches added to hdr/Options to cover some functionality that StrongARM previously covered)
        * SAcleanflushbroken
        * StrongARM_POST
        * IrqsInClaimRelease
        * CheckProtectionLink
        * GSWorkspaceInKernelBuffers
        * EarlierReentrancyInDAShrink
        * LongCommandLines
        * ECC
        * NoSPSRcorruption
        * RMTidyDoesNowt
        * RogerEXEY
        * StorkPowerSave
        * DebugForcedReset
        * AssembleKEYV
        * AssemblePointerV
        * ProcessorVectors
        * Keyboard_Type
        Assorted old files have also been deleted.
      Admin:
        Identical binary to previous revision for IOMD & Raspberry Pi builds
      
      
      Version 5.51. Tagged as 'Kernel-5_51'
      f655fcf6
    • Jeffrey Lee's avatar
      Delete STB code · 9a571a08
      Jeffrey Lee authored
      Detail:
        This change gets rid of the following switches from the source (picking appropriate code paths for a desktop build):
        * STB
        * RO371Timings
        * NormalSpeedROMS
        * AutoSpeedROMS
        * RISCPCBurstMode
        * InterlacedPointer
        * ParallelFlashUpgrade (and s/FlashROM file)
        * Embedded_UI
        Some of the deleted code might be worth revisiting in future:
        * OS_ReadSysInfo 4 support for storing the MAC in alternate CMOS locations (including 2nd copy for error checking) or fetching via Service_MachineAddress
        * Mouse handling changes, possibly aimed at hiding the mouse pointer if a mouse isn't connected
        * More strict CMOS validation in s/NewReset
      Admin:
        Identical binary to previous revision for IOMD & Raspberry Pi builds
      
      
      Version 5.50. Tagged as 'Kernel-5_50'
      9a571a08
    • Jeffrey Lee's avatar
      Delete pre-HAL and 26bit code · 7d5bfc66
      Jeffrey Lee authored
      Detail:
        This change gets rid of the following switches from the source (picking appropriate code paths for a 32bit HAL build):
        * HAL
        * HAL26
        * HAL32
        * No26bitCode
        * No32bitCode
        * IncludeTestSrc
        * FixR9CorruptionInExtensionSWI
        Various old files have also been removed (POST code, Arc/STB keyboard drivers, etc.)
      Admin:
        Identical binary to previous revision for IOMD & Raspberry Pi builds
      
      
      Version 5.49. Tagged as 'Kernel-5_49'
      7d5bfc66
    • Jeffrey Lee's avatar
      Merge HAL branch to trunk · bafe3084
      Jeffrey Lee authored
      Detail:
        This change merges the past 15+ years of HAL branch development back to the trunk.
        This is effectively the end for non-HAL builds of the kernel, as no attempt has been made to maintain it during this merge, and all non-HAL & non-32bit code will soon be removed anyway.
        Rather than list everything that's been added to the HAL branch, it's easier to describe the change in terms of the things that the HAL branch was lacking:
        * Trunk version of Docs/32bit contained updated comments for the SVC stack structure during ErrorV
        * Trunk version of s/HeapMan contained a tweak to try and reduce the number of small free blocks that are created
        * Trunk version of s/Kernel contained a change to only copy 248 bytes of the error string to the error buffer (down from 252 bytes), to take into account the extra 4 bytes needed by the PSR. However this goes against the decision that's been made in the HAL branch that the error buffer should be enlarged to 260 bytes instead (ref: https://www.riscosopen.org/tracker/tickets/201), so the HAL build will retain its current behaviour.
        * Trunk version of s/MsgCode had RMNot32bit error in the list of error messages to count when countmsgusage {TRUE}
        * Trunk version of s/PMF/i2cutils contained support for OS_Memory 5, "read/write value of NVRamWriteSize". Currently the HAL branch doesn't have a use for this (in particular, the correct NVRamWriteSize should be specified by the HAL, so there should be no need for software to change it at runtime), and so this code will remain switched out in the HAL build.
      Admin:
        Tested on Raspberry Pi
      
      
      Version 5.48. Tagged as 'Kernel-5_48'
      bafe3084
  26. 15 Jun, 2016 1 commit
    • Jeffrey Lee's avatar
      Clear the exclusive monitor when returning to pre-empted code · d10d2336
      Jeffrey Lee authored
      Detail:
        s/Kernel - Add macro for CLREX, which uses a dummy STREX on basic ARMv6 machines. Clear the exclusive monitor after issuing transient callbacks, to cope with callbacks being triggered on exit from IRQ
        s/ArthurSWIs, s/HAL, s/NewIRQs - Clear the exclusive monitor on exit from IRQ handlers & default FIQ handler
        s/VMSAv6 - Clear the exclusive monitor on entry to the data abort pre-veneer
      Admin:
        Tested on Raspberry Pi
        Non-transient callback handlers, custom abort handlers, FIQ handlers, and anything else which returns directly to interrupted user code is responsible for issuing its own CLREX if the code has done something that could have left the local monitor in the exclusive state (e.g. calling a SWI counts towards this, as there's no guarantee the monitor will be open on exit from the SWI)
      
      
      Version 5.35, 4.79.2.327. Tagged as 'Kernel-5_35-4_79_2_327'
      d10d2336
  27. 01 Jun, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix teletext mode when zero page relocated · 8a653457
      Jeffrey Lee authored
      Detail:
        s/vdu/vduttx - References to VduDriverWorkSpace need to be ZeroPage-relative. Without relocation, it looks like most of these addresses were hitting the Debugger workspace page, avoiding an immediate crash but causing no text to appear on screen.
      Admin:
        Tested on Raspberry Pi 1
      
      
      Version 5.35, 4.79.2.326. Tagged as 'Kernel-5_35-4_79_2_326'
      8a653457