Fix wrong XCBTable being used for pre-rev T StrongARMs. Update HAL UART API docs.

Detail:
  s/ARMops - Fix pre-rev T StrongARMs using the wrong XCBTable, causing invalid page flags to be used for the write-through cache policy
  Docs/HAL/Serial - Update HAL UART API docs. Mostly filling in some blanks, but also correcting a couple of things, and documenting new Features bit 4, LineStatus bit 8, and the effect on InterruptID.
Admin:
  Tested on pre-rev T StrongARM RiscPC


Version 5.61. Tagged as 'Kernel-5_61'

Docs/HAL/Serial

-Features
+int HAL_UARTPorts(void)
 
-     Bit 0:  FIFOs available
+  Return number of UART ports
 
-int ReceiveByte(int port, int *status)
+void HAL_UARTStartUp(int port)
+
+  Initialise the indicated port. Must be called before any of the other
+  control or data operations for that port.
+
+void HAL_UARTShutdown(int port)
+
+  Shutdown the indicated port
+
+int HAL_UARTFeatures(int port)
+
+  Bit 0:  FIFOs available
+  Bit 1:  DMA available
+  Bit 2:  Modem lines available
+  Bit 3:  Hardware RTS/CTS available
+  Bit 4:  Transmitter empty IRQ is actually "TX FIFO under threshold" IRQ, and
+          may only change state once level is crossed (so on startup IRQ may
+          not be firing). Use line status bit 8 to work out when to stop
+          filling the FIFO.
+
+int HAL_UARTReceiveByte(int port, int *status)
 
   Returns the next byte from the FIFO (if enabled) or the holding register.
   If status is non-NULL, the line status associated with the byte is
   read (see LineStatus). The return value is only meaningful if a
   received byte is available (bit 0 of *status will be set).
 
-void TransmitByte(int port, int byte)
+void HAL_UARTTransmitByte(int port, int byte)
 
-int LineStatus(int port)
+  Sends a byte. The routine is not expected to wait for FIFO space to become
+  available; instead it should silently fail.
+
+int HAL_UARTLineStatus(int port)
 
      Bit 0: Receiver Data Ready
      Bit 1: Overrun Error
      Bit 2: Parity Error
      Bit 3: Framing Error
      Bit 4: Break Error
-     Bit 5: Transmitter Holding Register Empty
-     Bit 6: Transmitter Empty (including FIFO)
+     Bit 5: Transmitter FIFO Empty
+     Bit 6: Transmitter FIFO + hold/shift register empty
      Bit 7: FIFO contains a Parity, Framing or Break error
+     Bit 8: TX FIFO full (may only be reported if Features bit 4 set)
 
   Parity, Framing and Break errors are associated with each byte received.
   Whether the values reported here are associated with the last byte
@@ -31,7 +55,7 @@ int LineStatus(int port)
   Error bits are cleared whenever status is read, using either LineStatus
   or ReceiveByte with status non-NULL.
 
-int InterruptEnable(int port, int eor, int mask)
+int HAL_UARTInterruptEnable(int port, int eor, int mask)
 
   Enables interrupts. Bits are:
  
@@ -40,14 +64,16 @@ int InterruptEnable(int port, int eor, int mask)
      Bit 2: Received Line Status
      Bit 3: Modem Status
 
+  new_state = (old_state AND mask) EOR eor
+
   Returns previous state.
 
-int Rate(int port, int baud16)
+int HAL_UARTRate(int port, int baud16)
 
   Sets the rate, in units of 1/16 of a baud. Returns the previous rate.
   Use -1 to read.
 
-int Format(int port, int format)
+int HAL_UARTFormat(int port, int format)
 
   Bits 0-1: Bits per word  0=>5, 1=>6, 2=>7, 3=>8
   Bit 2:    Stop length 0=>1, 1=>2 (1.5 if 5 bits)
@@ -59,30 +85,29 @@ int Format(int port, int format)
 
   Returns previous format. -1 to read.
 
-void FIFOSize(int *rx, int *tx)
+void HAL_UARTFIFOSize(int *rx, int *tx)
 
   Returns the size of the RX and TX FIFOs. Either parameter may be NULL.
   Note that the size of the TX FIFO is the total amount of data that can
-  be sent immediately when the Transmitter Holding Register Empty
-  status holds. (So an unusual UART that had a transmit threshold
+  be sent immediately when the Transmitter Holding Register Empty/FIFO under
+  threshold IRQ holds. (So an unusual UART that had a transmit threshold
   should return total FIFO size minus threshold).
 
-void FIFOClear(int port, int flags)
+void HAL_UARTFIFOClear(int port, int flags)
 
   Clears the input FIFO (if bit 0 set) and the output FIFO (if bit 1 set).
 
-int FIFOEnable(int port, int enable)
+int HAL_UARTFIFOEnable(int port, int enable)
 
   Enables or disables the RX and TX FIFOs: 0 => disable, 1 => enable
   -1 => read status. Returns previous status.
 
-int FIFOThreshold(int port, int threshold)
+int HAL_UARTFIFOThreshold(int port, int threshold)
 
-  Sets the receive threshold level for the FIFO RX interrupt. Normally
-  available values are 1,4,8 and 14 bytes. Returns previous value.
-  -1 to read.
+  Sets the receive threshold level for the FIFO RX interrupt. Returns previous
+  value. -1 to read.
   
-int InterruptID(int port)
+int HAL_UARTInterruptID(int port)
 
   Returns the highest priority interrupt currently asserted. In order
   of priority:
@@ -90,7 +115,8 @@ int InterruptID(int port)
   3 => Receiver Line Status (Cleared by ReceiveByte/LineStatus)
   2 => Received Data Available (Cleared by reading enough data)
   6 => Character Timeout (received data waiting)
-  1 => Transmitter Holding Register Empty (Cleared by this call)
+  1 => TX Holding Register Empty (Cleared by this call)/FIFO under threshould
+       (cleared by sending enough chars)
   0 => Modem Status (Cleared by ModemStatus)
   -1 => No Interrupt
 
@@ -98,22 +124,25 @@ int InterruptID(int port)
   change, or when RI goes from high to low (ie bits 0 to 3 of ModemStatus
   are set).
  
-int Break(int port, int enable)
+int HAL_UARTBreak(int port, int enable)
 
   Activates (1) or deactivates (0) a break condition. -1 to read,
   returns previous state.
                                
-int ModemControl(int port, int eor, int mask)
+int HAL_UARTModemControl(int port, int eor, int mask)
 
   Modifies the modem control outputs.
 
   Bit 0: DTR
   Bit 1: RTS
+  Bit 5: Use hardware RTS/CTS
+
+  new_state = (old_state AND mask) EOR eor
 
-  Note that these are logical outputs, although the physical pins may be inverted.
-  So 1 indicates a request to send.
+  Note that these are logical outputs, although the physical pins may be
+  inverted. So 1 indicates a request to send. Returns previous state.
 
-int ModemStatus(int port)
+int HAL_UARTModemStatus(int port)
 
   Reads the modem status inputs.
 
@@ -126,8 +155,14 @@ int ModemStatus(int port)
   Bit 6: RI
   Bit 7: DCD
 
-  Note that these are logical inputs, although the physical pins may be inverted.
-  So 1 indicates a Clear To Send condition.
+  Note that these are logical inputs, although the physical pins may be
+  inverted. So 1 indicates a Clear To Send condition. This must also clear
+  the modem interrupt status.
+
+int HAL_UARTDevice(int port)
+
+  Return the device number allocated to the UART port
 
-int Device(int port)
+int HAL_UARTDefault(void)
 
+  Return the UART number that should be used for OS_SerialOp, or -1 for none

VersionASM

@@ -11,13 +11,13 @@
                         GBLS    Module_HelpVersion
                         GBLS    Module_ComponentName
                         GBLS    Module_ComponentPath
-Module_MajorVersion     SETS    "5.60"
-Module_Version          SETA    560
+Module_MajorVersion     SETS    "5.61"
+Module_Version          SETA    561
 Module_MinorVersion     SETS    ""
-Module_Date             SETS    "13 Sep 2016"
-Module_ApplicationDate  SETS    "13-Sep-16"
+Module_Date             SETS    "09 Oct 2016"
+Module_ApplicationDate  SETS    "09-Oct-16"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.60"
-Module_HelpVersion      SETS    "5.60 (13 Sep 2016)"
+Module_FullVersion      SETS    "5.61"
+Module_HelpVersion      SETS    "5.61 (09 Oct 2016)"
                         END

VersionNum

-/* (5.60)
+/* (5.61)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        5.60
+#define Module_MajorVersion_CMHG        5.61
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                13 Sep 2016
+#define Module_Date_CMHG                09 Oct 2016
 
-#define Module_MajorVersion             "5.60"
-#define Module_Version                  560
+#define Module_MajorVersion             "5.61"
+#define Module_Version                  561
 #define Module_MinorVersion             ""
-#define Module_Date                     "13 Sep 2016"
+#define Module_Date                     "09 Oct 2016"
 
-#define Module_ApplicationDate          "13-Sep-16"
+#define Module_ApplicationDate          "09-Oct-16"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.60"
-#define Module_HelpVersion              "5.60 (13 Sep 2016)"
-#define Module_LibraryVersionInfo       "5:60"
+#define Module_FullVersion              "5.61"
+#define Module_HelpVersion              "5.61 (09 Oct 2016)"
+#define Module_LibraryVersionInfo       "5:61"

s/ARMops

@@ -530,6 +530,7 @@ Analyse_WB_Crd
 
         LDRB    a2, [v6, #ProcessorType]
         TEQ     a2, #SA110
+        TEQNE   a2, #SA110_preRevT
         ADREQL  a2, XCBTableSA110
         BEQ     Analyse_WB_Crd_finish
         TEQ     a2, #SA1100