Skip to content

GitLab

Commit b4016e9c authored by Kevin Bracey's avatar Kevin Bracey
Browse files

32-bit Kernel. 

Details:
  The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
  set to TRUE.
  If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
  although some internal changes have taken place to minimise compile
  switches between the two cases. See Docs.32bit for more technical info.

  The hardest part was the flood-fill...

Other changes:
  Pointer shape changes now take place on the next VSync, rather than actually
  WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
  down by 5% now :)

  Lots of really crusty pre-IOMD code removed.

Admin:
  Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
  will need to see a lot of use to iron out difficulties. I'd like anyone who
  has a non-frozen project to at least attempt using this Kernel.

Version 5.23. Tagged as 'Kernel-5_23'
parent 24044755
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1036 additions and 3200 deletions
s/ChangeDyn
View file @ b4016e9c
This diff is collapsed.
s/Convrsions
View file @ b4016e9c
......@@ -142,7 +142,6 @@ Signed_Output ROUT
Cardinal_Spaced_Output ROUT
Signed_Spaced_Output
[ StrongARM
SUB sp, sp, #12 ; get 12 byte buffer
Push "r1,r2,lr"
LDR r10,code_of_swi
......@@ -175,50 +174,6 @@ space_conv_exit
code_of_swi
DCD XOS_ConvertCardinal1 - OS_ConvertSpacedCardinal1
|
Push "R1, R2"
; copy our code into the stack (!!)
ADR R1, code_segment
LDMIA R1, {R1, R2, R12}
ADD R2, R2, R11
Pull "R10, R11"
Push "R1, R2, R12"
SUB sp, sp, #12 ; get 12 byte buffer
MOV R1, sp
MOV R2, #12
MOV lr, pc
ADD pc, sp, #12 ; oh for an "execute" instruction!
; note can't get VSet back from this "SWI"
RSB R0, R2, #12 ; bytes got
MOV R1, R10
MOV R2, R11
MOV R12, #0
MOV R11, sp
01 LDRB R10, [R11], #1
BL addconvchar
BVS space_conv_exit
SUBS R0, R0, #1
BEQ space_conv_exit
CMP R10, #"-"
BEQ %BT01
CMP R0, #3
CMPNE R0, #6
CMPNE R0, #9
BNE %BT01
MOV R10, #" "
BL addconvchar
BVC %BT01
space_conv_exit
ADD sp, sp, #12+12
B endconversion
code_segment
Push "lr"
SWI XOS_ConvertCardinal1 - OS_ConvertSpacedCardinal1
Pull "PC"
]
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -229,11 +184,14 @@ code_segment
addconvchar ROUT
CMP R2, R12
ORRLES pc, lr, #V_bit
BLE addconvcharoverflow
ADD R12, R12, #1
STRB R10, [R1], #1
BICS pc, lr, #V_bit
RETURNVC
addconvcharoverflow
RETURNVS
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; EcoNet conversions
......
s/Copro15ops
View file @ b4016e9c
......@@ -269,11 +269,10 @@ C15 CN 15
MACRO
ARM8_cleanflush_IDC $temp,$temp2
;for simplicity, disable interrupts during entire operation - 26-bit assumed
MOV $temp2,pc
AND $temp2,$temp2,#I_bit
EOR $temp2,$temp2,#I_bit ;temp := <current I> EOR <I set>
TEQP $temp2,pc ;disable I
;for simplicity, disable interrupts during entire operation
mrs ,$temp2,CPSR
ORR $temp,$temp2,#I32_bit
msr ,CPSR_c,$temp ;disable I
MOV $temp,#0 ;initial segment and index
01
ARM8_cleanflush_IDCentry $temp
......@@ -283,7 +282,7 @@ C15 CN 15
ADD $temp,$temp,#1 :SHL: 4 ;next segment
CMP $temp,#8 :SHL: 4 ;8 segments done?
BLO %BT01
TEQP $temp2,pc ;restore I
msr ,CPSR_c,$temp2 ;restore I
MEND
|
......@@ -479,15 +478,14 @@ C15 CN 15
MEND
;fully clean and flush DC - see ARMA_clean_DC for more info
;assumed to be 26 bit mode
MACRO
ARMA_fullycleanflush_DC $cleanaddr,$temp1,$temp2,$temp3
MOV $temp3,pc
ORR $temp1,$temp3,#I_bit
TEQP $temp1,#0 ;disable IRQs
mrs ,$temp3,CPSR
ORR $temp1,$temp3,#I32_bit
msr ,CPSR_c,$temp1 ;disable IRQs
ARMA_clean_DC $cleanaddr,$temp1,$temp2
ARMA_flush_DC
TEQP $temp3,#0 ;restore IRQ state
msr ,CPSR_c,$temp3 ;restore IRQ state
MEND
;enable core clock switching (fast core clock allowed)
......
s/FlashROM
View file @ b4016e9c
......@@ -64,8 +64,7 @@ FlashROM
; Switch CPU to 32-bit mode
MOV R0,#MMUC_L :OR: MMUC_D :OR: MMUC_P ; Set PROG32 and DATA32
ARM_write_control R0
MOV R0,#I32_bit :OR: F32_bit :OR: SVC32_mode
msr AL,CPSR_all,R0
msr ,CPSR_c,#I32_bit :OR: F32_bit :OR: SVC32_mode
; Initialise various CPU control registers
MOV R0,#IOMD_ROMCR_NSTicks_5 :OR: IOMD_ROMCR_HalfSpeed :OR: IOMD_ROMCR_32bit
......
s/GetAll
View file @ b4016e9c
......@@ -42,121 +42,12 @@
;whether compiling to run on (Risc PC) emulator
GBLL RunningOnEmul
RunningOnEmul SETL {FALSE} :LAND::LNOT: STB
RunningOnEmul SETL {FALSE}
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; now the conditional flags for the version we want
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; TMD 29-Apr-93: Fix1 conditioning removed for simplicity of code - always true
[ {TRUE}
! 0, "Fix1: interrupts re-enabled in ChangeDynamicArea"
]
GBLL Fix2
Fix2 SETL {TRUE}
[ Fix2
! 0, "Fix2: TMD optimisations of heap manager"
]
GBLL Fix3
Fix3 SETL {TRUE}
[ Fix3
! 0, "Fix3: ExtendHeap stack balanced"
]
GBLL Fix4
Fix4 SETL {TRUE}
[ Fix4
! 0, "Fix4: ExtendBlock IRQ latency improved"
]
GBLL Fix5
Fix5 SETL {TRUE}
[ Fix5
! 0, "Fix5: SpriteOp made re-entrant"
]
GBLL Fix6
Fix6 SETL {TRUE}
[ Fix6
! 0, "Fix6: OS_Byte &87 restores caller's IRQ state"
]
GBLL Fix7
Fix7 SETL {TRUE}
[ Fix7
! 0, "Fix7: OS_Word &0E,0 enables IRQs"
]
GBLL Fix8
Fix8 SETL {TRUE}
[ Fix8
! 0, "Fix8: OS_Word &15,0 enables IRQs"
]
GBLL Fix9
Fix9 SETL {TRUE}
[ Fix9
! 0, "Fix9: Incarnation names not terminated by 1st character"
]
GBLL Fix10
Fix10 SETL {TRUE}
[ Fix10
! 0, "Fix10: *Unplug terminated by address bug fixed"
]
GBLL Fix11
Fix11 SETL {TRUE}
[ Fix11
! 0, "Fix11: Podule IRQ despatcher doesn't corrupt R0"
]
GBLL Fix12
Fix12 SETL {TRUE}
[ Fix12
! 0, "Fix12: Rename incarnation fixed"
]
; TMD 04-Sep-89: Fix bug in prefer incarnation - corrupted error pointer if
; module or incarnation didn't exist
GBLL Fix13
Fix13 SETL {TRUE}
[ Fix13
! 0, "Fix13: Prefer incarnation fixed"
]
; TMD 06-Sep-89: Fix bug in CallAfter/Every - the error pointer was corrupted
; (errors caused by supplying non-positive time interval, or by being unable to
; claim a node from the system heap)
GBLL Fix14
Fix14 SETL {TRUE}
[ Fix14
! 0, "Fix14: CallAfter/Every error pointer not corrupted"
]
; TMD 11-Sep-89: Fix bug in AddCallBack - freed wrong heap node when chaining
; down the vector
GBLL Fix15
Fix15 SETL {TRUE}
[ Fix15
! 0, "Fix15: AddCallBack frees correct heap node"
]
; TMD 25-Sep-89: Fix bug in GSRead quoted termination - started skipping spaces
; from the wrong character, and didn't adjust for post increment after loading
; first non-space.
GBLL Fix16
Fix16 SETL {TRUE}
[ Fix16
! 0, "Fix16: GSRead quoted termination fixed"
]
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; essential global variables
......@@ -326,6 +217,9 @@ LateAborts SETL MEMM_Type = "ARM600" :LAND: {TRUE}
GBLL ShrinkableDAs ; if true, support Shrinkable Dynamic Areas (eg. CacheFS)
ShrinkableDAs SETL {TRUE}
GBLL ShadowROM ; if true, the ROM is mirrored above
ShadowROM SETL {FALSE} ; &FF800000
GBLL Interruptible32bitModes
Interruptible32bitModes SETL {TRUE} ;if true, limited 32-bit mode code support (interrupt handler does not assume
; 26-bit foreground), also allows faster, 32-bit APCS version of FPEmulator
......@@ -405,6 +299,9 @@ mjsServiceTrace SETL {FALSE}
GBLL mjsSysHeapNodesTrace ;for statistics gathering on some SysHeap nodes only
mjsSysHeapNodesTrace SETL {FALSE}
GBLL NoSPSRcorruption ;set to true if IRQ dispatcher
NoSPSRcorruption SETL {FALSE} ;preserves SPSR_SVC
[ StrongARM
! 0," ______________________________________________________"
......@@ -517,8 +414,6 @@ Reset_PoduleOrCallBackCorrupt * 9
; Flags for RISC OS Blue changes
;
GBLL AssembleA1KeyHandler
AssembleA1KeyHandler SETL {FALSE}
GBLL AssembleKEYV
AssembleKEYV SETL {TRUE} ; Use KEYV.
GBLL AssemblePointerV
......@@ -569,13 +464,6 @@ GetPalette SETS "GET s.Vdu.VduPal10"
]
GBLS GetRS423
[ DriversInKernel
GetRS423 SETS "GET s.PMF.rs423"
|
GetRS423 SETS ""
]
GBLS GetKbdDrA1
[ Keyboard_Type = "A1A500"
GetKbdDrA1 SETS "GET s.PMF.KbdDrA1"
......@@ -588,13 +476,6 @@ GetKbdDrA1 SETS ""
GetKbdRes SETS "GET s.KbdResA1"
|
GetKbdRes SETS "GET s.KbdRes" :CC: Keyboard_Type
]
GBLS GetKey2
[ AssembleA1KeyHandler
GetKey2 SETS "GET s.PMF.Key2"
|
GetKey2 SETS ""
]
; control switches for med_00001 (the flood fill routines 1024 line limit).
......@@ -757,29 +638,39 @@ StartOfPMF
GET s.PMF.osword
GET s.PMF.realtime
GET s.PMF.convdate
$GetRS423
GET s.PMF.i2cutils
GET s.PMF.oswrch
GET s.PMF.buffer
$GetKbdDrA1
GET s.PMF.key
$GetKey2
GET s.PMF.mouse
ALIGN
EndOfPMF
! 0, "PMF section size = &" :CC: :STR: (EndOfPMF - StartOfPMF)
[ {FALSE}
StartOfAMB_beforealign
ALIGN 4096 ;align to 4k page boundary, for easy ROMpatch
]
StartOfAMB
GET s.AMBControl.AMB
EndOfAMB
[ {FALSE}
DCB "GROT" ;spare words marker
ALIGN 4096 ;align to 4k page boundary, for easy ROMpatch
]
EndOfKernel
& 0 ; for patching by BigSplit et al
! 0, "PMF section size = &" :CC: :STR: (StartOfAMB_beforealign - StartOfPMF)
! 0, "AMB section size = &" :CC: :STR: (EndOfAMB - StartOfAMB)
[ {FALSE}
! 0, "AMB section (4k aligned) starts at ":CC::STR:(StartOfAMB)
! 0, "AMB section size (4k aligned) = &" :CC: :STR: (EndOfKernel - StartOfAMB)
]
[ med_00001_debug
! 0,""
......
s/HeapMan
View file @ b4016e9c
This diff is collapsed.
s/HeapSort
View file @ b4016e9c
......@@ -66,8 +66,7 @@ HeapSortRoutine ROUT
Push "r0-r3, hs_array, hs_procadr, hs_i, hs_j, hs_K, hs_R, lr"
MVN r14, #I_bit ; Enable interrupts (may take ages)
TSTP r14, pc
CLRPSR I_bit, r14 ; Enable interrupts (may take ages)
[ False
STR r0, ndump ; For debugging porpoises
......@@ -162,20 +161,9 @@ h6 MOV r0, hs_K ; IF K >= K(R(j)) THEN h8
MOV lr, pc ; r0, r1 for comparison
MOV pc, hs_procadr
[ True ; 1.73+ optimisation, faster in all cases
; Assumes signed comparison done <<<<<<
;h7
LDRLT r14, [hs_array, hs_j, LSL #2] ; R(i) = R(j)
STRLT r14, [hs_array, hs_i, LSL #2]
BLT h4
|
BGE h8 ; Assumes signed comparison done <<<<<<
;h7
LDR r14, [hs_array, hs_j, LSL #2] ; R(i) = R(j)
STR r14, [hs_array, hs_i, LSL #2]
B h4
]
h8 STR hs_R, [hs_array, hs_i, LSL #2] ; R(i) = R
......@@ -234,8 +222,9 @@ h8 STR hs_R, [hs_array, hs_i, LSL #2] ; R(i) = R
CMP r5, r3 ; reached start of cycle?
MOVEQ r7, r9 ; get back from temp slot if last one
BL MoveFromGivenSlot ; preserves flags
BL MoveFromGivenSlot ; corrupts flags, but preserves r5, r3...
CMP r5, r3
MOVNE r4, r7 ; update r4 (current block)
BNE %BT92
......@@ -273,13 +262,13 @@ MoveToTempSlot ENTRY "r4, r8, r9"
LDRPL r14, [r4], #4
STRPL r14, [r9], #4
BPL %BT00
EXITS
EXIT
01 SUBS r8, r8, #1
LDRPLB r14, [r4], #1
STRPLB r14, [r9], #1
BPL %BT01
EXITS
EXIT
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; In r4 -> where element is to be copied
......@@ -298,13 +287,13 @@ MoveFromGivenSlot ENTRY "r4, r7, r8"
LDRPL r14, [r7], #4
STRPL r14, [r4], #4
BPL %BT00
EXITS
EXIT
01 SUBS r8, r8, #1
LDRPLB r14, [r7], #1
STRPLB r14, [r4], #1
BPL %BT01
EXITS
EXIT
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Built-in sorting procedures
......@@ -336,9 +325,9 @@ hs_CardinalPtrCMP
hs_CardinalCMP
CMP r0, r1
BICCSS pc, lr, #N_bit :OR: V_bit ; CS -> GE (nv)
BIC lr, lr, #V_bit
ORRS pc, lr, #N_bit ; CC -> LT (Nv)
msr CS, CPSR_f, #C_bit ; CS -> GE (nv)
msr CC, CPSR_f, #N_bit ; CC -> LT (Nv)
MOV pc, lr
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; In r0, r1 -> integers
......@@ -378,7 +367,8 @@ hs_StringCMP ROUT
CMP r2, #space-1 ; Finished ?
BHI %BT10
BICS pc, lr, #N_bit :OR: V_bit ; GE
CMP r2, r2 ; return EQ (also GE)
MOV pc, lr
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Case-sensitive string comparison
......@@ -396,7 +386,8 @@ hs_StringSensCMP ROUT
CMP r2, #space-1 ; Finished ?
BHI %BT10
BICS pc, lr, #N_bit :OR: V_bit ; GE
CMP r2, r2 ; return EQ (also GE)
MOV pc, lr
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......
s/KbdResA1
View file @ b4016e9c
......@@ -67,10 +67,6 @@ A500Copy_Col * KEYDOWN + 8
; On ARM600, this routine must work in IRQ32 mode
IRQ_Test_CTRL_or_R_Pressed ROUT
[ CPU_Type = "ARM600"
BIC pc, pc, #&FC000000 ; take us out of the shadow ROM area
NOP ; (this instruction skipped)
]
Push "r0-r2, R10-R12, lr"
MOV R12, #IOC
......
s/KbdResPC
View file @ b4016e9c
......@@ -130,10 +130,6 @@ SetUpKbd
; On ARM600, this routine must work in IRQ32 mode
IRQ_Test_CTRL_or_R_Pressed ROUT
[ CPU_Type = "ARM600"
BIC pc, pc, #&FC000000 ; take us out of the shadow ROM area
NOP ; (this instruction skipped)
]
SUB lr, lr, #4
Push "r0-r2,lr"
......
s/Kernel
View file @ b4016e9c
This diff is collapsed.
s/MemInfo
View file @ b4016e9c
......@@ -247,14 +247,23 @@ MemoryConvert ROUT
;
ppn_to_logical
CMP r7, r3 ; Validate page number.
[ No26bitCode
BCC meminfo_returncs ; Invalid so return C set.
|
ORRCCS pc, lr, #C_bit ; Invalid so return C set.
]
LDR r4, [r6, r3, LSL #3] ; If valid then lookup logical address.
TST r0, #physical,given ; If physical address was given then
LDRNE r9, =&FFF
ANDNE r9, r5, r9 ; mask off page offset
ORRNE r4, r4, r9 ; and combine with logical address.
[ No26bitCode
CLC
MOV pc, lr
|
BICS pc, lr, #C_bit ; Return C clear.
]
;----------------------------------------------------------------------------------------
......@@ -276,19 +285,35 @@ logical_to_physical
LDR r5, [r8, r5, LSL #2] ; r5 = L2PT entry for L2PT entry for logical address
EOR r5, r5, #2_10 ; Check for valid page.
TST r5, #3
[ No26bitCode
BNE meminfo_returncs
|
ORRNES pc, lr, #C_bit
]
LDR r5, [r9] ; r5 = L2PT entry for logical address
EOR r5, r5, #2_10 ; Check for valid page.
TST r5, #3
[ No26bitCode
BNE meminfo_returncs
|
ORRNES pc, lr, #C_bit
]
LDR r9, =&FFF ; Valid so
BIC r5, r5, r9 ; mask off bits 0-11,
AND r9, r4, r9 ; get page offset from logical page
ORR r5, r5, r9 ; combine with physical page address.
[ No26bitCode
CLC
MOV pc, lr
|
BICS pc, lr, #C_bit
]
meminfo_returncs
SEC
MOV pc, lr
;----------------------------------------------------------------------------------------
; physical_to_ppn
......@@ -307,7 +332,11 @@ physical_to_ppn ROUT
MOV r3, #0 ; Start at page 0.
10
CMP r7, r3 ; Stop if we run out of pages
[ No26bitCode
BCC meminfo_returncs
|
ORRCCS pc, lr, #C_bit ; (return with C set).
]
LDMIA r9!, {r10,r11} ; Get start address and size of next block.
SUB r10, r5, r10 ; Determine if given address is in this block.
......@@ -316,7 +345,12 @@ physical_to_ppn ROUT
BCS %BT10
ADD r3, r3, r10, LSR #12
[ No26bitCode
CLC
MOV pc, lr
|
BICS pc, lr, #C_bit ; Return with C clear.
]
;----------------------------------------------------------------------------------------
......
s/Middle
View file @ b4016e9c
This diff is collapsed.
s/ModHand
View file @ b4016e9c
This diff is collapsed.
s/MoreComms
View file @ b4016e9c
......@@ -31,7 +31,11 @@ Error_Code ROUT
Push "r2"
MOV r0, sp ; Error block
[ :LNOT:International
; Haven't got any alternate code, but at least it'll assemble
|
BL TranslateError_VClear
]
; If error number's changed don't substitute
LDR r3, [r0]
......@@ -54,8 +58,8 @@ Error_Code ROUT
MOV r0, r3
90
ADD sp, sp, #12
Pull "r7,r8,lr"
ORRS pc, lr, #V_bit
SETV
Pull "r7,r8,pc"
Error_CodeTag DCB "ErrSub", 0
......@@ -208,7 +212,9 @@ ROMModules_Code ENTRY
BCS AckEscape
MOV r0, #ModHandReason_EnumerateROM_ModulesWithInfo
SWI XOS_Module
EXITS VS ; exit V clear
BVC %FT08
CLRV
EXIT ; exit V clear
; R1 = module number +1
; R2 = podule number
......@@ -218,7 +224,7 @@ ROMModules_Code ENTRY
; R6 = version number
; Copy info into buffer and prettyprint
08
MOV r5, r1 ; save r1 and r2 for next call to OS_Module
MOV r10, r2
MOV r0, r1
......@@ -265,7 +271,7 @@ ROMModules_Code ENTRY
ADDCC r3, r3, #8
BLCC %FT20
BCC %BT03
04
MOV r11, #"0"
TST r6, #&F0000000 ; 1st digit of integer part
ORRNE r0, r11, r6, LSR #28
......@@ -332,11 +338,12 @@ ROMModules_Code ENTRY
; R1 buffer ptr, R2 bufflen left
20
EntryS
SUBS r2, r2, #1
STRPLB r0, [r1], #1
MOVS pc, lr
EXITS
21
Push "r0, lr"
EntryS "r0"
MOV r12, r0
22
LDRB r0, [r12], #1
......@@ -348,10 +355,10 @@ ROMModules_Code ENTRY
]
BLNE %BT20
BNE %BT22
Pull "r0, lr"
PullEnvS
SUB r0, r12, r0 ; length of string
SUB r0, r0, #1
MOVS pc, lr
MOV pc, lr
23
BL %BT20
......@@ -379,6 +386,21 @@ rommstatu
rommstatr
= "Running:Running",0
ALIGN
|
romm_helpstr
= "No. Position",9,"Module Name",9,9,"Version",9,"Status",10,13,0
rommpossr
= "System ROM", 0
rommstu
= "Unplugged", 0
rommstd
= "Dormant", 0
rommsta
= "Active", 0
rommstr
= "Running", 0
ALIGN
]
......@@ -428,15 +450,16 @@ RMEDoCommand
BuildRMEnsureError
MOVS r0, r10
Pull lr, NE
ORRNES pc, lr, #V_bit
ADR r0, ErrorBlock_ModuleTooOld
BEQ %FT10
SETV
Pull pc
10 ADR r0, ErrorBlock_ModuleTooOld
[ International
LDR r4,[r3, #Module_Title]
ADD r4,r4,r3
BL TranslateError_UseR4
Pull "LR"
ORRS PC,LR,#V_bit
SETV
Pull pc
|
BL GetOscliBuffer
MOV r10, r5
......
s/MoreSWIs
View file @ b4016e9c
This diff is collapsed.
s/MsgCode
View file @ b4016e9c
......@@ -31,7 +31,12 @@ TranslateError_VClear ROUT
Push "r4,LR"
MOV r4,#0
BL TranslateError_UseR4
[ No26bitCode
CLRV
Pull "r4,PC"
|
Pull "r4,PC",,^
]
TranslateError ROUT
Push "r4,LR"
......@@ -41,21 +46,18 @@ TranslateError ROUT
TranslateError_UseR4
Push "R8,LR"
mrs ,R8,CPSR
ORR R8,R8,#V_bit ; V set ready :)
MOV R8,#0
LDRB R8, [R8, #ErrorSemaphore]
CMP R8,#0
Pull "R8,LR",NE
ORRNES PC,LR,#V_bit
MOV LR,#0
LDRB LR, [LR, #ErrorSemaphore]
TEQ LR,#0
BNE %FT90
BIC R8, R8, #&0F
ORR R8, R8, #SVC_mode ; SVC mode, preserve IRQ state
msr ,CPSR_c, R8
MOV R8,LR
[ {TRUE}
ORR LR, LR, #SVC_mode ; SVC mode, preserve IRQ state
TEQP PC, LR
|
TEQP PC,#SVC_mode
]
MOV R0,R0
Push "R0-R7,LR"
MOV R2,#0
......@@ -76,12 +78,10 @@ TranslateError_UseR4
MOV R1,#0
STRB R1, [R1 ,#ErrorSemaphore] ; Clear error semaphore
Pull "R0-R7,LR" ; Exit with new block and V set.
TEQP PC,R8 ; Back to original mode.
MOV R0,R0
Pull "R8,LR"
ORRS PC,R14,#V_bit ; original R0.
Pull "R0-R7,LR"
90
msr ,CPSR_cf, R8 ; Back to original mode, V set
Pull "R8,PC"
;----------------------------------------------------------------------------------------
;
......@@ -96,17 +96,29 @@ TranslateError_UseR4
; Returns to word after end of token.
;
WriteS_Translated ROUT
[ No26bitCode
Push "r0-r8,LR"
|
Push "r0-r7,LR"
]
MOV r4,#0
B Int_WriteS_Translated_UseR4
WriteS_Translated_UseR4
[ No26bitCode
Push "r0-r8,LR"
|
Push "r0-r7,LR"
]
Int_WriteS_Translated_UseR4
BIC r1,LR,#3 ; r1 -> Token.
BIC r1,r1,#2_111111 :SHL: 26
[ No26bitCode
mrs ,r8,CPSR
MOV r1,LR
|
BIC r1,LR,#ARM_CC_Mask ; r1 -> Token.
]
MOV r0,#0
LDR r0,[r0,#KernelMessagesBlock]
CMP r0,#0 ; If no messages file, try the global one.
......@@ -157,9 +169,12 @@ Int_WriteS_Translated_UseR4
B %BT01
; Now skip to end of token.
02
[ No26bitCode
LDR r1,[sp,#9*4] ; Get original token pointer
|
LDR r1,[sp,#8*4] ; Get original token pointer
BIC r1,r1,#3 ; r1 -> Token.
BIC r1,r1,#2_111111 :SHL: 26
BIC r1,r1,#ARM_CC_Mask ; r1 -> Token.
]
03
LDRB r0,[r1],#1
CMP r0,#32
......@@ -175,15 +190,21 @@ Int_WriteS_Translated_UseR4
ADD r1,r1,#3 ; Round up to next word.
BIC r1,r1,#3
[ No26bitCode
STR r1,[sp,#9*4] ; Store back as return address on stack
ORRVS r8,r8,#V_bit
msr ,CPSR_f,r8
Pull "r0-r8,PC" ;Return.
|
LDR r2,[sp,#8*4]
MOV r3,#2_111111 :SHL:26
ORR r3,r3,#2_11
AND r2,r2,r3 ; Just the flags and mode bits.
AND r2,r2,#ARM_CC_Mask ; Just the flags and mode bits.
ORR r1,r1,r2
ORRVS r1,r1,#V_bit
STR r1,[sp,#8*4] ; Store back as return address on stack
Pull "r0-r7,PC",,^ ;Return.
Pull "r0-r7,PC",,^ ;Return.
]
;----------------------------------------------------------------------------------------
;
......@@ -198,17 +219,29 @@ Int_WriteS_Translated_UseR4
; Returns to word after end of token.
;
GSWriteS_Translated ROUT
[ No26bitCode
Push "r0-r8,LR"
|
Push "r0-r7,LR"
]
MOV r4,#0
B Int_GSWriteS_Translated_UseR4
GSWriteS_Translated_UseR4
[ No26bitCode
Push "r0-r8,LR"
|
Push "r0-r7,LR"
]
Int_GSWriteS_Translated_UseR4
BIC r1,LR,#3 ; r1 -> Token.
BIC r1,r1,#2_111111 :SHL: 26
[ No26bitCode
mrs ,r8,CPSR
MOV r1,LR
|
BIC r1,LR,#ARM_CC_Mask ; r1 -> Token.
]
MOV r0,#0
LDR r0,[r0,#KernelMessagesBlock]
CMP r0,#0 ; If no messages file, try the global one.
......@@ -238,9 +271,12 @@ Int_GSWriteS_Translated_UseR4
SWI XOS_PrettyPrint
; Now skip to end of token.
02
[ No26bitCode
LDR r1,[sp,#9*4] ; Get original token pointer
|
LDR r1,[sp,#8*4] ; Get original token pointer
BIC r1,r1,#3 ; r1 -> Token.
BIC r1,r1,#2_111111 :SHL: 26
BIC r1,r1,#ARM_CC_Mask ; r1 -> Token.
]
03
LDRB r0,[r1],#1
CMP r0,#0
......@@ -251,15 +287,21 @@ Int_GSWriteS_Translated_UseR4
ADD r1,r1,#3 ; Round up to next word.
BIC r1,r1,#3
[ No26bitCode
STR r1,[sp,#9*4] ; Store back as return address on stack
ORRVS r8,r8,#V_bit
msr ,CPSR_f,r8
Pull "r0-r8,PC" ;Return.
|
LDR r2,[sp,#8*4]
MOV r3,#2_111111 :SHL:26
ORR r3,r3,#2_11
AND r2,r2,r3 ; Just the flags and mode bits.
AND r2,r2,#ARM_CC_Mask ; Just the flags and mode bits.
ORR r1,r1,r2
ORRVS r1,r1,#V_bit
STR r1,[sp,#8*4] ; Store back as return address on stack
Pull "r0-r7,PC",,^ ;Return.
]
;----------------------------------------------------------------------------------------
;FindToken
......@@ -274,7 +316,12 @@ Int_GSWriteS_Translated_UseR4
;
;
FindToken ROUT
[ No26bitCode
Push "r0-r8,LR"
mrs ,r8,CPSR
|
Push "r0-r7,LR"
]
MOV r1,r0
MOV r0,#0
......@@ -298,7 +345,13 @@ FindToken ROUT
01
STR r2,[sp]
[ No26bitCode
msr ,CPSR_f,r8
Pull "r0-r8,PC"
|
Pull "r0-r7,PC",,^
]
;----------------------------------------------------------------------------------------
;Write0_Translated
;
......@@ -311,7 +364,7 @@ FindToken ROUT
; Message printed, r0->Message.
;
Write0_Translated ROUT
Push "r0,r1,LR"
EntryS "r0,r1"
BL FindToken
MOV R1,R0
01
......@@ -319,10 +372,10 @@ Write0_Translated ROUT
CMP R0,#31
SWIGT XOS_WriteC
STRVS r0,[SP]
Pull "r0,r1,PC",VS
EXIT VS
BGT %BT01
Pull "r0,r1,PC",,^
EXITS
END
......
s/NewIRQs
View file @ b4016e9c
This diff is collapsed.
s/NewReset
View file @ b4016e9c
This diff is collapsed.
s/Oscli
View file @ b4016e9c
This diff is collapsed.
s/PMF/Buffer
View file @ b4016e9c
This diff is collapsed.
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment