32-bit Kernel.

Details:
  The Kernel will now compile to produce a pure 32-bit system if No26bitCode is
  set to TRUE.
  If No26bitCode is FALSE, then the Kernel will be a standard 26-bit Kernel,
  although some internal changes have taken place to minimise compile
  switches between the two cases. See Docs.32bit for more technical info.

  The hardest part was the flood-fill...

Other changes:
  Pointer shape changes now take place on the next VSync, rather than actually
  WAITING for the VSync. Turning the Hourglass on shouldn't slow your machine
  down by 5% now :)

  Lots of really crusty pre-IOMD code removed.

Admin:
  Tested in 32 and 26-bit forms in a limited desktop build. Basically, this
  will need to see a lot of use to iron out difficulties. I'd like anyone who
  has a non-frozen project to at least attempt using this Kernel.

Version 5.23. Tagged as 'Kernel-5_23'

Docs/32bit

+Here are some notes on my thoughts so far about 32-bit RISC OS.
+Any comments appreciated.
+
+                                  GENERAL
+                                  =======
+
+My current belief is that RISC OS will either be running 26-bit, or 32-bit,
+with no in between state.
+
+When running 32-bit, it will make no use of 26-bit modes, and will call all
+routines in a 32-bit mode. There will be no support for 26-bit code, as this
+would entail run-time selection of whether to call entry points in 26 or 32
+bit mode, an added complication.
+
+When running 26-bit, it will make no more use of 32-bit modes than it does
+currently, and the same restrictions on 32-bit code will apply as now.
+
+Desktop systems will probably always be 26-bit. NCs may be 32-bit, as they
+have little or no requirement to run external software, but could just as well
+be 26-bit. Anything running on an ARM 9/10 etc will have to be 32-bit.
+
+Standard (non-Kernel) software should be modified to work whether it is
+called in a 26-bit or a 32-bit mode. For pure C applications and modules,
+this can just be a recompile; the compiled code will then run on both
+existing 26-bit systems, back to RISC OS 3.1, and 32-bit systems. A new
+Shared C Library will be required to support 32-bit programs on old systems.
+
+Assembler modules should also run on either 26 or 32-bit systems; however to
+achieve this use of MSR and MRS instructions will often be required to
+manipulate the PSR - if this cannot be avoided the module will become RISC OS
+3.1 incompatible. In our build system we will hide most of the differences
+inside macros - use macros like SETPSR instead of using TEQP directly, and
+26/32-bit forms will be selected on compile time by build switches. You will
+either have a module that uses TEQP that will work on ARM2-ARM8, or a module
+that uses MSR which will work on ARM6 onwards.
+
+This way we will continue to be able to test software on our desktop systems -
+it can be the same 32-bit binary - it will just run in a 26-bit mode.
+
+RISC OS will be largely unmodified - almost all binary APIs will act the same
+in a 32-bit system as they do now, except that they will be called in a 32-bit
+version of the documented processor mode.
+
+One side-effect of this is that R14 on entry to routines will contain just
+the return address, with no flags. Hence to preserve flags, the CPSR must be
+stacked on entry, and restored on exit. This is cumbersome, but can be hidden
+inside EntryS and EXITS macros. Note that this behaviour is then slightly
+different - you are preserving flags across the call, not restoring the flags
+passed in in R14. Most of the time this doesn't matter, as the API is
+documented in terms of preserving flags. There are exceptions to this rule,
+notably SWI handling.
+
+On a 32-bit system, SWIs are no longer expected to preserve the N Z and C
+flags. They may still set/clear them to return results. 32-bit code should
+not assume that SWIs preserve flags. Requiring flag preservation would impose
+an unacceptable burden on SWI dispatch. This effectively respecifies *all*
+SWIs by changing the default rule in PRM 1-29. Also, it becomes impossible
+for SWIs outside the Kernel to depend on the NZCV flags on entry. SWIs inside
+the Kernel, such as OS_CallAVector, can still manipulate flags freely. This
+should not be an onerous restriction; it is impossible to specify entry flags
+for SWIs in C or BASIC, for example.
+
+Many existing APIs do not actually require flag preservation, such as service
+call entries. In this case, simply changing MOVS PC... to MOV PC... and LDM
+{}^ to LDM {} is sufficient to achieve 32-bit compatibility.
+
+
+                               NASTY HACKY BITS
+                               ================
+
+To just set and clear NZCV flags you can use the SETV etc macros, which will
+do the right thing (TM) for the different processor types. To actually
+preserve flags, you will probably be forced to use MRS and MSR instructions.
+These are NOPs on pre-ARM 6 ARMs, so you may be able to do clever stuff to
+keep ARM2 compatibility.
+
+For example, the recommended code to check whether you're in a 26-bit mode is:
+
+        MOV     R0, #0
+        MRS     R0, CPSR        ; NOP on 26-bit only ARMs
+        TST     R0, #2_11100    ; EQ if in a 26-bit mode, NE if not
+
+Sometimes you may be forced to play with the SPSR registers. Beware: interrupt
+code will corrupt SPSR_svc if it calls a SWI. Existing interrupt handlers know
+to preserve R14_svc before calling a SWI, but not SPSR_svc. Hence you must
+disable interrupts around SPSR manipulations.
+
+                                   MODULE ENTRIES
+                                   ==============
+
+Most module entries are treated the same in the 32-bit world, except they
+will be entered in a 32-bit mode, and hence R14 will be a return address
+with no flags.
+
+Init,Final
+----------
+Unchanged. Flag preservation not required - only V on exit is looked at.
+
+Service
+-------
+Unchanged. Flags on exit ignored.
+
+Help/command
+------------
+Unchanged. Flag preservation not required - only V on exit is looked at.
+
+SWI decoding code
+-----------------
+Unchanged. Flag preservation not required - V on exit is looked at in number
+to text case.
+
+SWI handler
+-----------
+On 26 bit systems, R14 is a return address (inside the Kernel) with the
+user's NZCIF flags in it, V clear, mode set to SVC. The CPSR NZCV
+flags on exit are then passed back to the SWI caller. Hence MOVS PC,R14
+preserves the SWI caller's NZC flags and clears V. The NZ and C flags in the
+current PSR on entry are undefined, and are NOT the caller's (but V is
+clear). Thus you can simply read, modify and preserve the caller's flags.
+
+On 32 bit systems, R14 is a return address only. There is no way of
+determining the caller's flags, so you are not expected to preserve them. The
+NZC and V flags you exit with will be returned to the caller.
+
+If writing a new module, simply specify that all your SWIs corrupt flags,
+then your SWI dispatchers can return with MOV PC,R14, regardless of whether
+running on a 26 or 32 bit system.
+
+If converting an existing module to run on 32-bit, it is highly recommended that
+the same binary continue to work on 26-bit systems. You should therefore take
+steps to preserve flags when running in a 26-bit mode, if the module did
+before. When running on a 32-bit system, you needn't preserve flags. The
+following wrapper around the original SWI entry (converted to be 32-bit safe)
+achieves this, assuming you always want NZ preserved on a 26-bit system.
+
+	Push	R14
+	BL	Original_SWI_Code
+	Pull	R14
+      [ PreARM6compatibility
+	MOV	R10,#0
+      ]
+	MRS	R10,CPSR		; NOP on pre-ARM6
+	TST	R10,#2_11100		; EQ if in 26-bit mode - C,V unaltered
+	MOVNE	PC,R14			; 32-bit exit: NZ corrupted, CV passed back
+      [ PassBackC
+	BICCC	R14,R14,#C_bit		; Extra guff to pass back C as well
+	ORRCS	R14,R14,#C_bit
+      ]
+	MOVVCS	PC,R14			; 26-bit exit: NZC preserved, V clear
+	ORRVSS	PC,R14,#V_bit		; 26-bit exit: NZC preserved, V set
+
+Yes, this is cumbersome, but it can be removed when backwards compatibility is
+no longer desired. The alternative, which would be to pass in caller flags in
+R14, would impose a permanent carbuncle on the 32-bit API.
+
+
+Module flags
+------------
+This is a new module header entry at &30. It is an offset to the module
+flags word(s). The first module flag word looks like:
+
+          Bit 0       Module is 32-bit compatible
+          Bits 1-31   Reserved (0)
+
+Non 32-bit compatible modules will not be loaded by a 32-bit RISC OS.
+If no flags word is present, the module is assumed to be 26-bit compatible.
+
+
+        
+                              ENVIRONMENT HANDLERS
+                              ====================
+
+Undefined instruction handler
+-----------------------------
+32 bit system: Now called in UND32 mode. No preveneer.
+26 bit: as before
+
+Prefetch abort, data abort
+--------------------------
+32 bit system: Now called in ABT32 mode. No preveneer.
+26 bit: as before
+
+Error
+-----
+32 bit system: USR32 mode. PC contains no PSR flags.
+26 bit: as before - PC contains PSR flags, but may not be reliable.
+
+BreakPoint
+----------
+32 bit system: register block must be 17 words long.
+               contains R0-R15,CPSR.
+               entered in SVC32 mode
+26 bit: as before
+
+Handlers can check format by looking at mode on entry to handler.
+
+The following code is suitable to restore the user registers and return
+in the 32-bit case:
+
+        ADR     R14, saveblock          ; get address of saved registers
+        LDR     R0, [R14, #16*4]        ; get user PSR
+ [ :LNOT: NoSPSRcorruption
+        MRS     R1, CPSR                ; get current PSR
+        ORR     R1, R1, #&80            ; disable interrupts to prevent
+        MSR     CPSR_c, R1              ; SPSR_SVC corruption by IRQ code (yuck)
+ ]
+        MSR     SPSR_cxsf, R0           ; put it into SPSR_SVC
+        LDMIA   R14, {R0-R14}^          ; load user registers
+        MOV     R0, R0                  ; no-op after forcing user mode
+        LDR     R14, [R14, #15*4]       ; load user PC into R14_SVC
+        MOVS    PC, R14                 ; return to correct address and mode
+
+Escape
+------
+32 bit system: as before, but called in SVC32
+
+Event
+----
+32 bit system: as before, but in IRQ32 or SVC32
+
+Exit
+----
+32 bit system: as before, but in USR32
+
+Unused SWI
+----------
+26 bit system: called in SVC26 mode.
+               R14 = a return address in the Kernel, with NZCVIF flags the same
+                     as the caller's (except V clear).
+               PSR flags undefined (except I+F as caller)
+32 bit system: called in SVC32 mode.
+               R14 = return address in the Kernel
+               No way to determine caller condition flags
+               PSR flags undefined (except I+F as caller)
+
+UpCall
+------
+32 bit system: as before, but SVC32 mode
+
+CallBack
+--------
+32 bit system: register block must be 17 words long.
+               contains R0-R15,CPSR.
+               entered in SVC32 mode, IRQs disabled
+26 bit: as before
+
+Handlers can check format by looking at mode on entry to handler.
+
+The following code is suitable to restore the user registers and return
+in the 32-bit case:
+
+        ADR     R14, saveblock          ; get address of saved registers
+        LDR     R0, [R14, #16*4]        ; get user PSR
+        MSR     SPSR_cxsf, R0           ; put it into SPSR_SVC/IRQ
+        LDMIA   R14, {R0-R14}^          ; load user registers
+        MOV     R0, R0                  ; no-op after forcing user mode
+        LDR     R14, [R14, #15*4]       ; load user PC into R14_SVC/IRQ
+        MOVS    PC, R14                 ; return to correct address and mode
+               
+Exception registers
+-------------------
+32 bit system: block must be 17 words long.
+               will contain R0-R15,PSR
+Exception handlers can determine block format by looking at mode on entry
+to handler.
+
+
+                     SOFTWARE VECTORS
+                     ================
+
+Software vectors have a number of different properties. They can be called
+under a variety of conditions, and the flags they exit with may or may not
+be significant.
+
+When called using OS_CallAVector, the caller's NZCV flags always used to be
+passed in in R14, and the claimant's flags on exit would be passed back.
+
+In a 32-bit system, the caller's flags are not passed in R14. Their C and V
+flags are visible in the PSR though, just as in a 26-bit system. N and Z are
+not visible. Again, exit flags are passed back.
+
+Most vectors are not intended to be called with OS_CallAVector, and their
+exit flags have never had significance, for example KeyV, EventV and TickerV.
+
+Others are vectored SWIs, such as ByteV and ReadLineV. These pass back
+C and V flags only.
+
+A few vectors, like RemV, attach significance to entry flags. If not claiming,
+you mustn't change those flags for the next callee. In 26-bit mode this might
+have been achieved by:
+
+	CMP	R1,#mybuffer
+	MOVNES	PC,LR
+
+In the 32-bit world, you could change the CMP to a TEQ to preserve C and V, or
+you could use something like:
+
+	Push	R14
+	MRS	R14, CPSR
+	CMP	R1, #maxbuffers
+	BLS	handleit
+	MSR	CPSR_f, R14
+	Pull	PC
+handleit
+	...
+		
+
+                     INSIDE THE KERNEL
+                     =================
+
+The 32-bit Kernel will stay in 32-bit modes, and pass out to apps/modules in
+32-bit modes. Hardware vectors will save R14+SPSR separately to allow return
+to any mode/address.
+
+The 26-bit Kernel will switch into 26-bit modes fairly early, but
+still save R14+SPSR separately to simplify the state of assembly switches.
+It will switch back to 32-bit mode to execute the return, and will munge fake
+26-bit R14s when about to call environment handlers.
+
+When the Kernel dispatches an internal SWI, the stack currently looks like:
+
+       SVCSTK-4    Caller's R12
+             -8    Caller's R11
+             -12   Caller's R10
+             -16   SWI number
+
+R11 is the SWI number with the X bit clear, R14 is the return address with
+caller's flags.
+
+This will be changed to look like:
+
+       SVCSTK-4    Caller's R12
+             -8    Caller's R11
+             -12   Caller's R10
+             -16   Return R14 (32-bit - no flags)
+             -20   SWI number
+
+R11 will still be the SWI number with the X bit clear, but R14 actually will
+be the caller's PSR. This minimises changes to the Kernel, as most routines
+only actually interpret R14 as holding the flags. For example, they might
+exit with:
+
+        ORRVS   lr, lr, #V_bit
+        B       SLVK
+
+Such code will not need altering between 26 and 32-bit versions.
+
+
+                               MEMORY MAP
+                               ==========
+
+The "Shadow ROM" at FF800000-FFFFFFFF has been removed. This was originally
+intended to allow hardware vectors to branch "down" to the ROM, but this scheme
+was replaced by LDR PC,xxx hardware vectors. The only place that used it was
+the Kernel's start-up "Ctrl-or-R" keyboard interrupt handler. This has been
+modified, as it is technically unpredictable to branch around the ends of the
+address space.
+
+With abort handlers now being called in Abort mode, an Abort stack is required.
+This has been positioned at 02002000, in the area currently "reserved for fake
+screen" (VIDC1 compatibility). The stacks are now:
+
+               Limit      Base
+          IRQ: 01F00000   01F01xxx
+          SVC: 01C00000   01C02000
+          UND: 01E00000   01E02000
+          ABT: 02000000   02002000
+
+All are defined to be on a 1MB boundary. The area beyond the limit is usually
+unmapped, to cause an abort.
+
+Their actual locations and sizes are subject to change. In particular, they
+may not be in the lower 64MB in future.
+
+                           MISCELLANEOUS SWIS
+                           ==================
+
+OS_EnterOS
+----------
+If called in a 26-bit mode, takes you into SVC26, else into SVC32.
+

HelpStrs

@@ -370,6 +370,7 @@ Save_Help
      =   "*",TokenEscapeChar,Token0
      =   " copies the given area of memory to the named file."
      =   " Length and addresses are in hexadecimal.",13
+Save_Syntax
      =   "Syntax: *",TokenEscapeChar,Token0
      =   " <filename> <start addr>"
      =   " <end addr> [<exec addr> [<load addr>]]",13

MkRomInst,fd7

@@ -16,5 +16,5 @@ Dir <Obey$Dir>
 time
 amu_machine rom
 time
-amu_machine install_rom INSTDIR=<install$dir>.ROM.<Machine>
+amu_machine install_rom INSTDIR=<install$dir>.<Build>.RISC_OS
 time

Resources/UK/Messages

+BadNumb:Number not recognised
+NoSuchSWI1:SWI &%0 not known
+VarCantFind:System variable '%0' not found
+BuffOverflow:Buffer overflow
 Escape:Escape
 Syntax:Syntax
 OptErr:Syntax: *Opt [<x> [[,] <y>]]
@@ -36,12 +40,8 @@ UndefinedInstruction:Internal error: undefined instruction at &%0
 InstructionAbort:Internal error: abort on instruction fetch at &%0
 DataAbort:Internal error: abort on data transfer at &%0
 AddressException:Internal error: address exception at &%0
-BranchThrough0:Internal error: branch through zero at &%0
-NoSuchSWI1:SWI &%0 not known
+BranchThrough0:Internal error: branch through zero
 SDoesntExist:Sprite doesn't exist
-VarCantFind:System variable '%0' not found
-BuffOverflow:Buffer overflow
-BadNumb:Number not recognised
 ModuleTooOld:Module %0 too old
 NaffRelease:Bad vector release
 RMNotFound:Module %0 not found

TestSrc/Begin

@@ -92,6 +92,9 @@
 ; 19 Jun 97     BAR     2.25    Remove un-necessary mov r13,r14's
 ;                               When completed flashing LED's restore the
 ;                               faultcode flag from fiq_regs.
+; 04 Apr 00     KJB     2.30    Converted to run in 32-bit mode always.
+;                               ShowIOMDRegs set to FALSE (request from
+;                               Tom Clay)
 ;
 ;------------------------------------------------------------------------
 ;
@@ -104,8 +107,8 @@
 
 TS_STATUS       *       "R"     ;  Medusa POST version 2.0x
 ;
-TS_RELEASE      *       22
-TS_CHANGES      *       4
+TS_RELEASE      *       23
+TS_CHANGES      *       0
 
 
                 GBLL    POSTenabled
@@ -115,7 +118,7 @@ POSTenabled     SETL    {TRUE}          ; don't permit POST for ordinary startup
 AlwaysShortPOST SETL    {TRUE} :LAND: STB       		; always do a short POST
 
                 GBLL    ShowIOMDRegs
-ShowIOMDRegs	SETL    (IO_Type = "IOMD") :LAND: {TRUE} :LAND: STB	; show IOMD regs
+ShowIOMDRegs	SETL    (IO_Type = "IOMD") :LAND: {FALSE} :LAND: STB	; show IOMD regs
 
                 GBLL   DontShowProgressColours
 DontShowProgressColours	SETL	{TRUE} :LAND: STB		; Do not show the progress colour screens.
@@ -287,22 +290,15 @@ ts_ROM_dvectors
         &       (ts_ID_text - ROM)      ; Selftest identification text
 
 
-;
-; vectors ORd with these flags to assure proper mode when
-; executed by host thro' vector table.
-;
-
-ts_runflags     *       (I_bit :OR: F_bit :OR: SVC_mode)
-
 ts_ROM_cvectors
-        &       ts_RomPatt              :OR: ts_runflags
-        &       ts_User_startup         :OR: ts_runflags
-        &       ts_Self_test_startup    :OR: ts_runflags
-        &       ts_Dealer_startup       :OR: ts_runflags
-        &       ts_Forced_startup       :OR: ts_runflags
-        &       ts_GetCommand           :OR: ts_runflags
-        &       ts_Softstart            :OR: ts_runflags
-        &       ts_Hardstart            :OR: ts_runflags
+        &       ts_RomPatt
+        &       ts_User_startup
+        &       ts_Self_test_startup
+        &       ts_Dealer_startup
+        &       ts_Forced_startup
+        &       ts_GetCommand
+        &       ts_Softstart
+        &       ts_Hardstart
 
 
 ;
@@ -348,51 +344,23 @@ ts_ROM_bvectors
 
         MACRO
         MODE    $mode_bits
-        TEQP    psr,#($mode_bits :OR: I_bit :OR: F_bit)
-        NOP
+        msr    ,CPSR_c,#I32_bit :OR: F32_bit :OR: $mode_bits
         MEND
 
         MACRO
         MOV_fiq $dest,$src
-        MODE    FIQ_mode
+        MODE    FIQ32_mode
         MOV     $dest,$src
-        MODE    SVC_mode
+        MODE    SVC32_mode
         MEND
 
         MACRO
         FAULT   $code
-        MODE    FIQ_mode
-        ORR     r12_fiq,r12_fiq,$code
-        MODE    SVC_mode
-        MEND
-
-        MACRO
-        M32_fiq $dest,$src,$tmp1,$tmp2
-        SetMode FIQ32_mode,$tmp1,$tmp2
-        MOV     $dest,$src
-        msr     AL,CPSR_all,$tmp2
-        MEND
-
-        MACRO
-        FAULT32 $code,$tmp
-        SetMode FIQ32_mode,$tmp
+        MODE    FIQ32_mode
         ORR     r12_fiq,r12_fiq,$code
-        SetMode SVC32_mode,$tmp
+        MODE    SVC32_mode
         MEND
 
- [ StrongARM_POST
-;  ensure 26-bit mode for StrongARM or ARM 8 (since there is no 26 bit configuration)
-        MACRO
-        Ensure26bit_ARM8A $tmp
-        ARM_read_ID $tmp
-        AND     $tmp, $tmp, #&F000
-        CMP     $tmp, #&A000
-        CMPNE   $tmp, #&8000
-        mrs     EQ, $tmp, CPSR_all
-        BICEQ   $tmp, $tmp, #&10
-        msr     EQ, CPSR_all, $tmp
-        MEND
-  ]
 
 ;
 ; Define an area of storage with the required set of data bus patterns
@@ -593,11 +561,6 @@ ts_User_startup    ROUT
 
 ; it's a power-on reset, so assume we can't be in 32-bit mode for ARM 6/7
 
-  [ StrongARM_POST
-    ; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
-    ; note that MOV_fiq macro assumes 26-bit, so must sort this now
-    Ensure26bit_ARM8A r0
-  ]
         MOV_fiq r12_fiq, #R_HARD
         B       ts_Self_test_startup
         |
@@ -616,11 +579,6 @@ ts_User_startup    ROUT
 
 ts_Forced_startup  ROUT
 
-  [ StrongARM_POST
-    ; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
-    ; note that MOV_fiq macro assumes 26-bit, so must sort this now
-    Ensure26bit_ARM8A r0
-  ]
         MOV_fiq r12_fiq, #R_TESTED
         B       ts_Self_test_startup
 
@@ -628,11 +586,6 @@ ts_Forced_startup  ROUT
 
 ts_Dealer_startup  ROUT
 
-  [ StrongARM_POST
-    ; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
-    ; note that MOV_fiq macro assumes 26-bit, so must sort this now
-    Ensure26bit_ARM8A r4
-  ]
         MOV_fiq r12_fiq, #R_EXTERN
 
         LDR     r4,%FT02                ; make a pointer to signon string
@@ -946,10 +899,10 @@ ts_MEMCset
 ;
 ; where mmmm is memory size in hex Kbytes, pp is page size in hex Kbytes.
 ;
-        MODE    FIQ_mode                        ; Save memory size and
+        MODE    FIQ32_mode                      ; Save memory size and
         MOV     r11_fiq,r2                      ; MEMC setup value for
         MOV     r10_fiq,r1                      ; later use
-        MODE    SVC_mode
+        MODE    SVC32_mode
 
         MOV     r8, r0, LSR #2                  ; MemSize now returns actual page size in r0
         ADD     r8,r8,r1,LSL #6
@@ -1405,14 +1358,14 @@ RAMtest
 					; and r4 the offset from physical to ORGed ROM addresses
 					; r4 = ROM - Phys[Ext]ROM
 	RSB	r4, r4, #PhysSpace	; r4 = PhysSpace - ROM + Phys[Ext]ROM, pc = ROM + offset
-	SetMode SVC32_mode,r0		; Must do this, as PhysSpace is outside 26 bit addressing
+        MODE    SVC32_mode              ; Must do this, as PhysSpace is outside 26 bit addressing
 	ADD	pc, pc, r4		; pc = PhysSpace + Phys[Ext]ROM + offset
         NOP                             ; this instruction skipped by pc adjustment
 
 ;
 ; Modify the PhysRamTable so only VRAM and the first ts_MaxRamTest of DRAM gets tested
 ;
-        M32_fiq r0,r12_fiq,r1,r2        ; get the test condition flags
+        MOV_fiq r0,r12                  ; get the test condition flags
 
         ANDS    r0,r0,#(R_EXTERN :OR: R_TESTED)
         BNE     %FT16                   ; do full test if test adapter is present
@@ -1430,7 +1383,7 @@ RAMtest
         CMPS    r9,r10
         BNE     %BT14
 16
-        FAULT32 #R_MEMORY,r0            ; memory tests were attempted
+        FAULT   #R_MEMORY               ; memory tests were attempted
 
         MOV     r9,#VideoPhysAddr
         LDR     r8,[r9]                 ; report the test address
@@ -1491,7 +1444,7 @@ RAMtest
         BEQ     %BT18                   ; if it passed, go look for another block
 
 20
-        FAULT32 #R_MEMFAILBIT,r2        ; failed - report fault address
+        FAULT   #R_MEMFAILBIT           ; failed - report fault address
         ADRL    r4,%BT2
         MOV     r11,r1                  ; Save failed data
         MOV     r8,r0                   ; first failing address
@@ -1625,11 +1578,6 @@ ts_restore_physical
         MOV     r7, #MMUC_D
         SetCop  r7, CR_Control
 
-  [ StrongARM_POST
-        Ensure26bit_ARM8A r7
-        MOV     r7, #MMUC_D    ;avoid corrupting r7, just in case
-  ]
-
         B       ts_VIDCtest
 
 ;

TestSrc/Cmos

@@ -21,7 +21,7 @@
 ;
 ; out:  R0 = sum of all bytes in block
 ;       R1 - R13 trashed
-;  
+;
 
 ts_CMOSread     ROUT
 
@@ -75,8 +75,7 @@ ts_TXCheckAck ROUT
         MOV     R12,R14
         BL      ts_TXByte
         BL      ts_Acknowledge
-        MOVVC   PC, R12                 ; acknowledged ok, so return
-        ORRS    PC, R12, #V_bit
+        MOV     PC, R12
 
 ; *****************************************************************************
 ;
@@ -86,11 +85,11 @@ ts_TXCheckAck ROUT
 ;
 
 ts_SetC1C0 ROUT
-        MOV     R11, R14
-        BIC     R14, R14, #Z_bit                ; indicate not checking clock
+        MOVS    R11, R14                        ; NE: indicate not checking clock
 ts_SetOrCheck
-        ORR     R14, R14, #I_bit                ; disable interrupts
-        TEQP    R14, #0
+        mrs    ,R14, CPSR
+        ORR     R14, R14, #I32_bit              ; disable interrupts
+        msr    ,CPSR_c, R14
 
         ADD     R0, R0, R1, LSL #1              ; R0 := C0 + C1*2
 
@@ -126,7 +125,7 @@ ts_SetOrCheck
 
 ts_SetC1C0CheckClock ROUT
         MOV     R11, R14
-        ORR     R14, R14, #Z_bit                ; indicate checking clock
+        CMP     R0, R0                          ; EQ: indicate checking clock
         B       ts_SetOrCheck
 
 
@@ -222,10 +221,10 @@ ts_Acknowledge ROUT
         BL      ts_SetC1C0
 
         TST     R3, #1                  ; should be LO for correct acknowledge
-        MOV     R3, PC
+        mrs    ,R3, CPSR
         BICEQ   R3, R3, #V_bit          ; clear V if correct acknowledge
         ORRNE   R3, R3, #V_bit          ; set V if no acknowledge
-        TEQP    R3, #0
+        msr    ,CPSR_f, R3
 
         MOV     PC,R9
 
@@ -305,7 +304,7 @@ ts_RXByte  ROUT
         SUBS    R4, R4, #1
         BCS     %BT10
 
-        MOV     R0, R3                  ; return the result in R0  
+        MOV     R0, R3                  ; return the result in R0
         MOV     PC, R9
 
         LTORG

TestSrc/Mem1IOMD

@@ -72,10 +72,6 @@ ts_LineTest
         MOV     r0,#MMUC_D
         SetCop  r0,CR_Control
 
-  [ StrongARM_POST
-        Ensure26bit_ARM8A r0
-  ]
-
         MOV     r0,#0
         MOV_fiq r9,r0                                   ; r9-fiq records low DRAM address for use elsewhere
 
@@ -367,10 +363,6 @@ ts_LineTestIOMD
         MOV     r0,#MMUC_D
         SetCop  r0,CR_Control
 
-  [ StrongARM_POST
-        Ensure26bit_ARM8A r10
-  ]
-
         MOV     r10, #0                                 ; indicate no RAM found yet
         MOV     r9, #IOMD_DRAMCR_DRAM_Small             ; bit to OR into DRAMCR
         MOV     r12, #DRAM0PhysRam

TestSrc/Mem4

@@ -3,8 +3,8 @@
 ; RISC OS 2+ BOOT TEST SOFTWARE.
 ; MEMORY TEST 4 VERSION H.      BRIAN RICE 12-01-90.
 ; 04-Apr-90     ArtG    0.1     Added ts_count_cams, improved reporting
-; 11-Apr-90     ArtG    0.2     Use RISC OS routine BangCams for 
-;                               alternate MEMC configurations.  
+; 11-Apr-90     ArtG    0.2     Use RISC OS routine BangCams for
+;                               alternate MEMC configurations.
 ; 17-Apr-90     ArtG    0.3     rationalise page-counting code
 ;
 ; This file will be called by MEM6x_SCR for the purposes of assembly.
@@ -14,8 +14,8 @@
 ; The module requires the running of the memory sizing routine used by
 ; the OS to set up the page size for this module.
 ;
-; This test module was designed to operate on all current and future 
-; machines. The module is designed to handle up to 512 physical pages 
+; This test module was designed to operate on all current and future
+; machines. The module is designed to handle up to 512 physical pages
 ; which is the maximum number of pages in a 16 MByte FOX.
 ;
 ; A 16 MB FOX has 4 MEMCs in use, each MEMC is addressed by Bits 7 and
@@ -50,7 +50,7 @@
 ;
 ; The patterns are chosen so that if two or more MEMCs are accessed
 ; together and both RAM outputs get enabled onto the data bus simultaneously,
-; then there is a reasonable chance that the data returned will show the 
+; then there is a reasonable chance that the data returned will show the
 ; presence of a fault.
 ;
 ; When the CAM entries have been initialised the module will then check that
@@ -186,7 +186,7 @@ ts_CAM
 ; 'C' pseudocode for the test routine.
 ;
 ;       for (i = &1ff; i >= 0; i--)
-;               set_cam_idle(i);               
+;               set_cam_idle(i);
 ;
 ;       find maximum page number.
 ;       if (max_page != ts_count_CAMS)
@@ -228,7 +228,7 @@ ts_CAM
 ;
         ROUT                                ; Local Branches.
 
-        BL      ts_count_CAMs               ; get log2 pagesize to r1  
+        BL      ts_count_CAMs               ; get log2 pagesize to r1
         MOV     r8, #ts_MAX_CAMS            ; r8= max. number of physical pages.
 0       SUBS    r8, r8, #&01                ; Subtract 1 to make it r8 - 1 Pages.
         BEQ     ts_bad_CAM_count            ; no pages ? - shouldn't hit this!
@@ -239,7 +239,7 @@ ts_CAM
         LDRB    r4, [r4, r8, LSR#7]         ; r4 = Loc pointed to by r4 + (r1 >> 7).
         ORR     r4, r8, r4, LSL #24         ; r4 = page number OR (MEMC code << 24).
         ORR     r4, r4, #ts_pagemark        ; r4 = page id OR magic number
-;            
+;
 ; The calculated page marker is now in r4, ref_p_mark.
 ; Current page in r8 - convert to physical address in r9.
 ; the pagesize power-of-2 is in r1 (from ts_count_CAMs)
@@ -252,10 +252,10 @@ ts_CAM
         LDR     r9, [r9, #ts_pmark_pos]     ; r9 = contents of loc pointed to by
                                             ;      r9 + ts_pmark_pos.
 ;
-; Check that read_p_mark is valid. 
+; Check that read_p_mark is valid.
 ;
-; Either the value read is the expected pagemark, junk (no memory) or an 
-; aliased pagemark - if it's aliased, then either the memory or the MEMC 
+; Either the value read is the expected pagemark, junk (no memory) or an
+; aliased pagemark - if it's aliased, then either the memory or the MEMC
 ; isn't decoded that far.
 ; Bump down and try a bit lower, until it's OK.
 ;
@@ -310,7 +310,7 @@ ts_CAM
         BL      ts_count_CAMs               ; get total number of pages
         SUB     r0,r0,#1                    ; make a mask for useable page
         AND     r0,r0,#&7f                  ; numbers - min(128, num_pages)
-        AND     r12, r12, r0                ; r12 -> (r12 + 1) masked 
+        AND     r12, r12, r0                ; r12 -> (r12 + 1) masked
         MOV     r0, #&00                    ; to useable page numbers.
         MOV     r1, r12
         BL      ts_set_cam                  ; Setup a page for vectors
@@ -342,7 +342,7 @@ ts_CAM
 ;
 ; ****************************************************************************
 ;
-ts_copy_vectors 
+ts_copy_vectors
 ;
 ; Copies the vectors to the physical page in r0 (preserved) also copies
 ; pagemark + phypage.
@@ -406,7 +406,7 @@ ts_set_camp
 ; r11 = PPL
 ;
         MOV     r3,r0           ; logical page number
-        MOV     r11,r2          ; protection level 
+        MOV     r11,r2          ; protection level
         MOV     r2,r1           ; physical page number
         MOV_fiq r0, r11_fiq     ; MEMC configuration
         MOV     r9, r0          ; keep a copy in r9
@@ -422,7 +422,7 @@ ts_set_camp
 ts_check_mapped
 ;
 ; This routine will check that the CAM has been programed correctly and that the required
-; page is responding when asked. A quick test is made to check that other pages are not 
+; page is responding when asked. A quick test is made to check that other pages are not
 ; responding as well.
 ;
 ; logical page  in r0,
@@ -475,7 +475,7 @@ ts_check_mapped
         CMP     r0, r1                      ; Are the read pagemarks equal ??
         ADRNE   r4, %F10
         BNE     ts_CAM_fail                 ; Failed : mapping not equal.
-        CMP     r0, r2                      ; 
+        CMP     r0, r2                      ;
         ADRNE   r4, %F11
         BNE     ts_CAM_fail                 ; Failed : map equal, but corrupt
 ;
@@ -483,7 +483,7 @@ ts_check_mapped
 ;
         MOV     r2, #1
 0       EOR     r0, r2, r3                  ; Flip a (walking) bit in the LPN.
-        CMP     r0, #ts_vrest               ; Is r0 = ts_vrest ?? Where all the pages are 
+        CMP     r0, #ts_vrest               ; Is r0 = ts_vrest ?? Where all the pages are
                                             ; mapped to.
         BEQ     %F1                         ; If r0 = ts_vrest then branch forward to 1.
 ;
@@ -503,7 +503,7 @@ ts_check_mapped
 ;
 ; Fault - is the page mapped there the same as our test page ?
 ;
-        CMP     r0, r1 
+        CMP     r0, r1
         ADREQ   r4, %F12                   ; Failed : phys page also mapped here
         ADRNE   r4, %F13                   ; Failed : page not unmapped
         EOR     r3, r2, r3                 ; remake the duff LPN for the error display
@@ -552,14 +552,14 @@ ts_CAM_fail
 ; **************************************************************************
 ;
 
-; Routine to return expected number of physical pages in r0. 
+; Routine to return expected number of physical pages in r0.
 ; Uses memory size determination from r10_fiq and page mode from r11_fiq.
 ; Returns pagesize as power-of-two in r1, for pagenumber->address calcs.
 
 ts_count_CAMs
 
         MODE    FIQ_mode
-        MOV     r0,r10_fiq,LSR #12      ; get values determined 
+        MOV     r0,r10_fiq,LSR #12      ; get values determined
         MOV     r1,r11_fiq,LSR #2       ; by MemSize
         MODE    SVC_mode
 
@@ -567,7 +567,7 @@ ts_count_CAMs
         MOV     r0,r0,LSR r1
         ADD     r1,r1,#12               ; page bit-shift value
 
-        MOVS    pc,lr
+        MOV     pc,lr
 
 
 ;

VersionASM

@@ -6,9 +6,9 @@
                         GBLS    Module_MinorVersion
                         GBLS    Module_Date
                         GBLS    Module_FullVersion
-Module_MajorVersion     SETS    "5.22"
-Module_Version          SETA    522
+Module_MajorVersion     SETS    "5.23"
+Module_Version          SETA    523
 Module_MinorVersion     SETS    ""
-Module_Date             SETS    "23 Mar 2000"
-Module_FullVersion      SETS    "5.22"
+Module_Date             SETS    "04 Apr 2000"
+Module_FullVersion      SETS    "5.23"
                         END

VersionNum

-/* (5.22)
+/* (5.23)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  *
  */
-#define Module_MajorVersion_CMHG        5.22
+#define Module_MajorVersion_CMHG        5.23
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                23 Mar 2000
+#define Module_Date_CMHG                04 Apr 2000
 
-#define Module_MajorVersion             "5.22"
-#define Module_Version                  522
+#define Module_MajorVersion             "5.23"
+#define Module_Version                  523
 #define Module_MinorVersion             ""
-#define Module_Date                     "23 Mar 2000"
+#define Module_Date                     "04 Apr 2000"
 
-#define Module_FullVersion              "5.22"
+#define Module_FullVersion              "5.23"

hdr/ExportVals/s/GetVals

@@ -25,6 +25,14 @@ med_00001_debug     SETL  {FALSE}
         GBLL  StrongARM
 StrongARM SETL {TRUE}
 
+; yet more..
+        GBLL    ChocolateSysHeap
+ChocolateSysHeap SETL {TRUE}
+
+        GBLL    mjsSysHeapNodesTrace
+mjsSysHeapNodesTrace SETL {TRUE}
+
+
         GET     ^.PublicWS
         GET     ^.KernelWS
 
@@ -61,6 +69,7 @@ String  SETS    "$String" :CC: ", R" :CC: ((:STR: Register) :RIGHT: 1)
         LabelValue Export_IRQsema
         LabelValue Export_LatchBSoftCopy
         LabelValue Export_MEMC_CR_SoftCopy
+        LabelValue Export_DebuggerSpace
         LabelValue Export_RedirectInHandle
         LabelValue Export_RedirectOutHandle
         LabelValue Export_ScratchSpace
@@ -75,6 +84,5 @@ String  SETS    "$String" :CC: ", R" :CC: ((:STR: Register) :RIGHT: 1)
         LabelValue VDWSSize
         LabelValue ScreenBlankFlag
         LabelValue ScreenBlankDPMSState
-        LabelValue Export_ResetType
 
         END

hdr/ExportVals/values

@@ -13,12 +13,39 @@
 ; limitations under the License.
 ;
 ARM stand alone Macro Assembler Version 2.00
-AMBControl_ws  at  00000175
-ARMA_Cleaner_flipflop at 00000179
-SyncCodeA_sema (byte) at 0000017D
-VideoPhysAddr held at  00000180
-ProcessorType  at  00000235
-ProcessorFlags at  00000236
+AMBControl_ws  at  00000180
+ARMA_Cleaner_flipflop at 00000184
+SyncCodeA_sema (byte) at 00000188
+Oscli_CmdHashSum      at 0000018C
+Oscli_CmdHashLists    at 00000190
+Serv_SysChains        at 00000194
+Serv_UsrChains        at 00000198
+Serv_AwkwardChain     at 0000019C
+VideoPhysAddr held at  000001A0
+LCD_Active flag byte held at  00000259
+ProcessorType  at  0000025B
+ProcessorFlags at  0000025C
+Free space after ProcVec = 00000020
+Free space after EnvString = 000000E0
+Free space after CamMap debug block = 00000024
+KeyWorkSpace          at 00000590
+ChocolateCBBlocks     at 00000790
+ChocolateSVBlocks     at 00000794
+ChocolateTKBlocks     at 00000798
+ChocolateMRBlocks     at 0000079C
+ChocolateMABlocks     at 000007A0
+ChocolateMSBlocks     at 000007A4
+Module_List           at 000007D0
+ModuleSWI_HashTab     at 00000C40
+SysVars_StickyPtrs    at 00000E40
+Abort32_dumparea      at 00000E6C
+Help_guard            at 00000E84
+PCI_status            at 00000E98
+IOMD_NoInterrupt      at 00000E9C
+
+**WARNING** compiling in code to trace some SysHeap node statistics (mjsSysHeapNodesTrace TRUE)
+
+mjsSHNodesTrace_ws    at 00000EAC
 Label Export_BgEcfOraEor has the value &000004C0
 Label Export_FgEcfOraEor has the value &00000480
 Label Export_BranchToSWIExit has the value &01F037FC
@@ -41,4 +68,3 @@ Label Export_VduDriverWorkSpace has the value &00001000
 Label VDWSSize has the value &00003000
 Label ScreenBlankFlag has the value &0000047C
 Label ScreenBlankDPMSState has the value &0000047D
-Label Export_ResetType has the value &00000174

hdr/KernelWS

@@ -758,7 +758,9 @@ SpChoosePtr # 4
 PointerHeights # 4      ; 4 x 1 byte
 PointerActiveXs # 4     ; 4 x 1 byte
 PointerActiveYs # 4     ; 4 x 1 byte
-PointerShapeNumber # 4  ; only bottom byte used
+PointerShapeNumber # 1  ; includes bit 7 linkage flag
+PointerShapeChanged # 1 ; non-zero: change shape next vsync
+         # 2
 PointerX # 4            ; co-ordinates of pointer (not always = mouse)
 PointerY # 4
 
@@ -949,11 +951,6 @@ VEndSoftCopy    #       4       ; soft copy of VEnd  ------------""-------------
 VStartSoftCopy  #       4       ; soft copy of VStart so we can calculate VIDINITB correctly
 DAList          #       4       ; Pointer to first node on dynamic area list
 
- [ STB
-Export_ResetType	#	1	; &174 ; bit 0 => 1 = por, 0 = not por ; bits 1-7 reserved (zero)
-        ASSERT  Export_ResetType =  ResetType
-        ASSERT ?Export_ResetType = ?ResetType
- ]
 
                 AlignSpace 16
 AMBControl_ws   #       4       ; workspace anchor word for AMBControl
@@ -978,12 +975,6 @@ Serv_AwkwardChain       # 4          ;anchor for chain handling non-compliant mo
       ! 0, "Serv_UsrChains        at ":CC::STR:(Serv_UsrChains)
       ! 0, "Serv_AwkwardChain     at ":CC::STR:(Serv_AwkwardChain)
 
- [ StorkPowerSave
-;;;   AlignSpace 4
-;;;VIDCExternalSoftCopy #  4       ; soft copy of VIDCExternal
-;;;VIDCFSynSoftCopy     #  4       ; soft copy of VIDCFSyn
-;;;VIDCControlSoftCopy  #  4       ; soft copy of VIDCControl
- ]
 
                 AlignSpace 32   ; skipped bit must start on 32-byte boundary (due to speedup)
 
@@ -1019,6 +1010,7 @@ L2PTSize        #       4       ; Amount of memory (in bytes) used for static L2
                                 ; bit for the free pool L2, which follows directly after it
 SoftCamMapSize  #       4       ; Amount of memory (in bytes) used for soft CAM map
                                 ; (whole number of pages)
+InitKbdHandler  #       4       ; Address of interrupt routine
 InitKbdWs       #       16      ; Workspace for reset keyboard IRQ code (was 12 changed for Morris)
 CLine_Softcopy  #        1      ; Added for Morris - Monitor id
 
@@ -1064,16 +1056,8 @@ ProcVec_End             #       0
 ProcVecPreVeneersSize   *       4*4     ; Space for preveneers for loading handler addresses from 0 page.
 ProcVecPreVeneers       #       ProcVecPreVeneersSize
 
-; [ StorkPowerSave
-;;;VIDCExternalSoftCopy #  4       ; soft copy of VIDCExternal
-;;;VIDCFSynSoftCopy     #  4       ; soft copy of VIDCFSyn
-;;;VIDCControlSoftCopy  #  4       ; soft copy of VIDCControl
-; ]
-
-        ! 0, "Free space after ProcVec = ":CC::STR:(&320-@)
-
-        ASSERT  @ <= &320
-                #       &320-@
+        ASSERT  @ = &300
+Export_DebuggerSpace    #       16*8    ; Debugger module needs some zero page
 
   [ E2ROMSupport
 NVRamSize	#	1		; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
@@ -1218,12 +1202,13 @@ OscliCBcurrend  #       4
 ReturnCode      #       4
 RCLimit         #       4
 
-SpriteSize      #       4       ; saved on startup for Sprite code and RAMFS
-RAMDiscSize     #       4
-FontCacheSize   #       4       ; and font manager
+SpriteSize      #       4       ; saved on startup for Sprite code
 
 TickNodeChain   #       4
 
+PIRQ_Chain      #       4
+PFIQasIRQ_Chain #       4
+
 ; Workspace
 
 EnvTime            #    5
@@ -1244,12 +1229,10 @@ MonitorLeadType #       1       ; some function of the monitor lead inputs, as y
 
                 AlignSpace
 
-DUMPER            #     16 * 4
-
-Page_Size         #  4
-PIRQ_Chain        #  4
-PFIQasIRQ_Chain   #  4
+DUMPER          #       17 * 4  ; now 17 words for 32-bit
 
+                #       4       ; PxxxIRQ_Chain used to be here
+Page_Size       #       4
 CMOSRAMCache    #       256
 
 ; Was Free space (752 bytes) left by old IRQ despatch (new IRQ despatch moved as it required more space).
@@ -1325,7 +1308,7 @@ HeapReturnedReg_R2  # 4
 HeapReturnedReg_R3  # 4
 HeapReturnedReg_R4  # 4
 HeapReturnedReg_R13 # 4
-HeapReturnedReg_PC  # 4                 ; also acts as interlock
+HeapReturnedReg_PSR # 4                 ; also acts as interlock
 
 PrinterBufferAddr   #  4                ; holds address of printer buffer
 PrinterBufferSize   #  4                ; size of printer buffer - not to be confused with PrintBuffSize
@@ -1522,7 +1505,7 @@ Export_SvcTable                |#|     &400
         ASSERT ?Export_SvcTable = ?SvcTable
 
  ASSERT SvcTable = &01F033FC ; Required for SVC table pokers, 1.20 compatible
-SWIDespatch_Size        *       29*4
+SWIDespatch_Size        *       33*4
 SWIDespatch             |#|     SWIDespatch_Size
 
 

hdr/PublicWS

@@ -46,8 +46,8 @@ IRQsema             #         4
                     ^ &00000114
 MEMC_CR_SoftCopy    #         4
 
-                    ^ &00000174
-ResetType           #         1           ; bit 0 => type of last reset. Other bits reserved (zero).
+                    ^ &00000300
+DebuggerSpace       #      8*16
 
                     ^ &0000047C
 ScreenBlankFlag     #         1           ; 0 => unblanked, 1 => blanked

s/AMBControl/Memory

@@ -44,20 +44,19 @@ XROS_Module ENTRY
         STR     R5,[R2],#4                      ; enough space so just store
         Pull    "R3-R5"
 ; can never error
-        EXITS
+        CLRV
+        EXIT
 02
         SUB     R3,R5,R4
         SWI     XOS_Module
         STRVC   R5,[R2],#4
         Pull    "R3-R5"
-        EXITS   VC
         EXIT
 
 
 ros_free
         SUB     R2,R2,#4
         SWI     XOS_Module
-        EXITS   VC
         EXIT
 
 ros_claim
@@ -65,7 +64,6 @@ ros_claim
         SWI     XOS_Module
         STRVC   R3,[R2],#4                      ; so modptr-4 = amount asked for + 4
         SUB     R3,R3,#4                        ; needs to be preserved
-        EXITS   VC
         EXIT
 
 

s/AMBControl/service

@@ -32,11 +32,11 @@ AMBsrv_memorymoved
         MOV     R12,#AMBControl_ws
         LDR     R12,[R12]
         CMP     R12,#0
-        Pull    "R3-R6,R12,PC",EQ,^        ;AMBControl not initialised yet!
+        Pull    "R3-R6,R12,PC",EQ          ;AMBControl not initialised yet!
 
         LDR     R4,AMBMappedInNode
         CMP     R4,#0
-        Pull    "R3-R6,R12,PC",EQ,^        ;done if nothing mapped in
+        Pull    "R3-R6,R12,PC",EQ          ;done if nothing mapped in
 
         LDR     R3,[R4,#AMBNode_Npages]
 
@@ -47,7 +47,7 @@ AMBsrv_memorymoved
 
         CMP     R6,R3
         STRNE   R6,[R4,#AMBNode_Npages]    ;update Npages
-        Pull    "R3-R6,R12,PC",LE,^        ;done if Npages same, or shrink
+        Pull    "R3-R6,R12,PC",LE          ;done if Npages same, or shrink
 
         MOV     R5,#ApplicationStart
         ADD     R5,R5,R3,LSL #Log2PageSize ;first logical address to find
@@ -55,7 +55,7 @@ AMBsrv_memorymoved
         ADD     R4,R4,R3,LSL #2            ;first page number word to use
         SUB     R3,R6,R3                   ;no. of pages to find (grow number)
         BL      AMB_FindMemMapEntries
-        Pull    "R3-R6,R12,PC",,^
+        Pull    "R3-R6,R12,PC"
 
 
 ;Service_PagesSafe
@@ -71,11 +71,11 @@ AMBsrv_pagessafe
         MOV     R12,#AMBControl_ws
         LDR     R12,[R12]
         CMP     R12,#0
-        Pull   "R0-R1,R5-R10,R12,PC",EQ,^  ;AMBControl not initialised yet!
+        Pull   "R0-R1,R5-R10,R12,PC",EQ    ;AMBControl not initialised yet!
 
         LDR    R0,AMBNtasks
         CMP    R0,#0
-        Pull   "R0-R1,R5-R10,R12,PC",EQ,^  ;no nodes to check
+        Pull   "R0-R1,R5-R10,R12,PC",EQ    ;no nodes to check
 
 ;speed-up - list of pages tends to span a narrow range of page numbers, so
 ;            use min,max limits to skip search
@@ -136,7 +136,7 @@ AMBsrv_pagessafe
         LDR    R0,[R0,#AMBNode_next]
         CMP    R0,R1                 ;done if back at anchor node
         BNE    %BT01
-        Pull    "R0-R1,R5-R10,R12,PC",,^
+        Pull    "R0-R1,R5-R10,R12,PC"
 
     END
 

s/Arthur2

@@ -262,7 +262,7 @@ TimeVarTooLong
       [ International
         B      TranslateError
       |
-        ORRS   PC, LR, #V_bit
+        RETURNVS
       ]
 
 ReadYear
@@ -367,9 +367,10 @@ SetRC   Push  "lr"
         LDR    R4, =RCLimit
         LDR    R4, [R4]
         CMP    R2, R4
-        Pull  "lr", LS
-        BICLSS PC, lr, #V_bit
-        ADRGT  R0, ErrorBlock_RCExc
+        BHI    %FT03
+        CLRV
+        Pull  "PC"
+03      ADRGT  R0, ErrorBlock_RCExc
         ADRLT  R0, ErrorBlock_RCNegative
       [ International
         BL     TranslateError
@@ -479,7 +480,7 @@ GSINIT  ROUT
 ;        EQ means char is CR or LF, i.e. string is empty.
 
         ; Enable interupts as we've no right to have them disabled here
-        TEQP    pc, #SVC_mode
+        WritePSRc SVC_mode, R1
 
  [ GS_BufferNotStack
         AND     R2, R2, #GS_NoQuoteMess :OR: GS_NoVBarStuff :OR: GS_Spc_term
@@ -548,7 +549,7 @@ GSREAD  ROUT
 
         ; enable interupts as (a) they'll get enabled by a <thing> entry
         ; and (b) GSREAD may take some time
-        TEQP    pc, #SVC_mode
+        WritePSRc SVC_mode, R10
 
         BIC     lr, lr, #C_bit
         MOV     R10, #0
@@ -829,7 +830,7 @@ GSTRANS ROUT                    ; enables interrupts
 
         BIC      lr, lr, #C_bit
         Push    "R1, R3-R5, lr"
-        TEQP     PC, #SVC_mode             ; enable ints.
+        WritePSRc SVC_mode, R3             ; enable ints.
 
         MOV      R3, R1
         MOV      R4, R1                    ; two copies of start ptr
@@ -899,7 +900,7 @@ GSTRANS ROUT                    ; enables interrupts
  ]
 
 ReadVarValue ROUT
-        TEQP    PC, #SVC_mode   ; enable interupts (mode remains unchanged)
+        WritePSRc SVC_mode, r11 ; enable interupts (mode remains unchanged)
         Entry   "r0,r1"
 
         MOV     r11, r4
@@ -1204,7 +1205,7 @@ SysVar_Write0 Entry "r0,r1"
 
 SetVarValue
         ; enable IRQs
-        TEQP    pc, #SVC_mode
+        WritePSRc SVC_mode, r10
 
         Entry   "r0,r1,r2,r4,r5,r6,r9"
 
@@ -1904,7 +1905,7 @@ VarFindIt Entry "r0,r1,r2,r5,r6,r7,r8,r9,r10,r11"
         BNE     %BT45
 
 50
-        MOVHS   r10, pc                 ; preserve last HS result we got
+        mrs     HS, r10, CPSR           ; preserve last HS result we got
         MOVHS   r11, r4
         MOVLO   r6, r5
 55
@@ -1924,7 +1925,7 @@ VarFindIt Entry "r0,r1,r2,r5,r6,r7,r8,r9,r10,r11"
   ]
         MOVLS   r4, r11
         MOVHI   r3, #0
-        TEQLSP  pc, r10
+        msr     LS, CPSR_f, r10
 
  [ DebugSysVars
         SWI     XOS_WriteS
@@ -1932,8 +1933,7 @@ VarFindIt Entry "r0,r1,r2,r5,r6,r7,r8,r9,r10,r11"
         SWI     XOS_NewLine
  ]
         MOV     r12, r6
-        MOV     lr, pc
-        TEQP    lr, #Z_bit
+        TOGPSR  Z_bit, lr
         EXIT
 
 65
@@ -2091,7 +2091,7 @@ VarFindIt_QA ROUT
         BNE     %BT45
 
 50
-        MOVHS   r10, pc                 ; preserve last HS result we got
+        mrs     HS, r10, CPSR           ; preserve last HS result we got
         MOVHS   r11, r4
         MOVLO   r6, r5
 55
@@ -2113,10 +2113,9 @@ VarFindIt_QA ROUT
         MOV     r7, r6
         MOVLS   r6, r11
         MOVHI   r5, #0
-        TEQLSP  pc, r10
+        msr     LS, CPSR_f, r10
 
-        MOV     lr, pc
-        TEQP    lr, #Z_bit
+        TOGPSR  Z_bit, lr
 99
         Pull    "r0,r1,r2,r3,r4,r8,r9,r10,r11,PC"
 

s/Arthur3

@@ -123,8 +123,8 @@ NoTHEN  ROUT
         BL      TranslateError
       ]
 IfError
-        Pull    "R2, lr"
-        ORRS    PC, lr, #V_bit
+        SETV
+        Pull    "R2, pc"
 01
         &       ErrorNumber_Syntax
         =       "NoThen:There is no THEN", 0
@@ -133,8 +133,10 @@ IfError
 WantInteger ROUT
         CMP     R1, #0
         Pull    "R1"
-        Pull    "R2, lr", EQ            ; integer returned, so leave expranal error there
-        ORREQS  PC, lr, #V_bit
+        BNE     %FT10
+        SETV
+        Pull    "R2, pc"               ; integer returned, so leave expranal error there
+10
         ADR     R0, %FT01
       [ International
         BL      TranslateError
@@ -235,7 +237,7 @@ ExprBuffOFlo ROUT
 
 ReadExpression ROUT
         Push    "R0-R4, lr"
-        TEQP    PC, #SVC_mode   ; interrupts on, ta.
+        CLRPSR  I_bit, R12    ; interrupts on, ta.
         LDR     R12, =ExprWSpace
         STR     R13, ExprSVCstack
         ADR     R1, ExprBuff
@@ -279,9 +281,10 @@ ReadExpression ROUT
 03
         LDRB    R3, tos_op
         CMP     R3, #op_Bra
-        BLNE    compile_top_op
-        BNE     %BT03
-
+        BEQ     %FT55
+        BL      compile_top_op
+        B       %BT03
+55
         ePull   "R0, R2"
         CMP     R0, #type_Operator
         BEQ     MissingOpErr
@@ -328,9 +331,10 @@ ReadExpression ROUT
         LDRB    R3, tos_op
         LDRB    R0, [R0, R3]
         CMP     R0, R4
-        BLGT    compile_top_op
-        BGT     %BT04
-
+        BLE     %FT75
+        BL      compile_top_op
+        B       %BT04
+75
         MOV     R0, #type_Operator
         ePush   "R0, R2"        ;  push (operator)
         STRB    R2, tos_op
@@ -396,7 +400,7 @@ rightprectab
 ;*****************************************************************************
 
 compile_top_op ROUT
-; preserves the flags
+; corrupts the flags
         Push    "R2-R4, lr"
         ePull   "R0, R2"
         CMP     R0, #type_Operator
@@ -421,7 +425,7 @@ DispatchReturn
         BLEQ    Push_String
         ePush   "R0, R2"                ; temp val -> stack
 
-        GRABS   "R2-R4, PC"
+        Pull    "R2-R4, PC"
 
 ; the routines in this table are entered with one operand popped,
 ; any other op on stack ready to pop.
@@ -556,7 +560,7 @@ Minus_Code    ROUT  ; integer-integer
 Times_Code   ROUT  ; integer*integer
         BL      TwoIntegers
         MOV     R3, R2
-        MULTIPLY R2, R3, R4             ; get R3*R4->R2
+        MUL     R2, R4, R3              ; get R3*R4->R2
         B       DispatchReturn
 
 MOD_Code     ROUT  ; integer MOD integer
@@ -1282,8 +1286,7 @@ FindOption ENTRY "r1, r3-r5"
         ADDEQ   r1, r1, #1
         BEQ     %BT01
         CMP     r3, #"."
-        MOV     r3, #Z_bit
-        TEQP    r3, pc                          ; invert EQ/NE
+        TOGPSR  Z_bit, r3                       ; invert EQ/NE
         CMPNE   r1, #0
         ADDNE   r1, r1, #1                      ; skip .
         BNE     %FT02
@@ -1428,8 +1431,8 @@ ConfigGenErr
         BL      TranslateError
       ]
 ExitConfig
-        Pull    "lr"
-        ORRS    pc, lr, #V_bit
+        SETV
+        Pull    "pc"
 
 conoptservice
         MOV     r1, #Service_UKConfig
@@ -1584,8 +1587,8 @@ statoptservice
       [ International
         BL      TranslateError
       ]
-        Pull    "lr"
-        ORRS    pc, lr, #V_bit
+        SETV
+        Pull    "pc"
 03
         &       ErrorNumber_Syntax
         =       "BadStat:Bad status option", 0
@@ -1745,7 +1748,7 @@ FrigCapsList
 ; Preserves flags
 
 ListOneConfig   ROUT
-        Push    "lr"
+        EntryS
         LDRB    r4, [r2]
         CMP     r4, #ConType_Field
         CMPNE   r4, #ConType_Size
@@ -1788,9 +1791,7 @@ ListOneConfig   ROUT
 ExitShow
         SWIVC   XOS_NewLine
 11
-        Pull    "lr"
-        BICVCS  pc, lr, #V_bit
-        ORRS    pc, lr, #V_bit
+        EXITV
 05
         =       "<D>", 0
 42
@@ -1885,8 +1886,9 @@ ExitShow
  ]
         ADRL    r8, ScreenSizeFrig      ; if zero and it's ScreenSize, then call OS_ReadSysInfo to find appropriate amount
         TEQ     r8, r2
-        SWIEQ   XOS_ReadSysInfo         ; proper screen size (r0=0) on entry
-        MOVEQ   r0, r0, LSR #10
+        BNE     %FT35
+        SWI     XOS_ReadSysInfo         ; proper screen size (r0=0) on entry
+        MOV     r0, r0, LSR #10
 35
         Pull    "r8, r9"
         BL      PrintR0
@@ -1972,7 +1974,7 @@ ReadByte ENTRY  "r0, r2"
 
 ; take infoword in R0, return value in R0
 
-GetValue ENTRY  "r1"
+GetValue EntryS "r1"
         BL      ReadByte                ; now extract the value
         AND     r14, r0, #&FF           ; get bitoff
         MOV     r1, r1, LSR r14         ; throw away low bits

s/ArthurSWIs

@@ -39,7 +39,7 @@
 
 ReadUnsigned_Routine ENTRY "r0-r1, r3-r4, r9"
 
-        TEQP    PC, #SVC_mode
+        WritePSRc SVC_mode, r9
 
 ; first set range limit
         MOV     r9, r2            ; limit value
@@ -258,17 +258,31 @@ VecInitLoop
 ; Call_vector (n)
 ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 ; In:   r10 = vector number
+  [ No26bitCode
+;       lr contains return address
+;       cpsr contains flags/int state to set up before calling
+  |
 ;       lr contains return address + flags/int state to set up before calling
+  ]
 
 ; Out:  r10, r12, lr corrupted
 
 CallVector ROUT
 
+  [ No26bitCode
+        mrs     AL, r12, CPSR
+        CMP     r10, #NVECTORS
+        BHS     CallVecTooHigh          ; return - silly value
+
+        msr     AL, CPSR_f, r12         ; put back caller's flags + int state
+        Push    lr                      ; claimed return goes back to caller
+  |
         CMP     r10, #NVECTORS
         MOVCSS  pc, lr                  ; return - silly value
 
         Push    lr                      ; claimed return goes back to caller
         TEQP    lr, #0                  ; put back caller's flags + int state
+  ]
 
         LDR     r14, =VecPtrTab         ; Point at table of head pointers
         LDR     r10, [r14, r10, LSL #2] ; nextblock:=vecptrtab!(n*4)
@@ -284,9 +298,17 @@ CallVecLoop
         TEQ     r10, #0                 ; until nextblock points to zero
         BNE     CallVecLoop
 
+  [ No26bitCode
+        Pull    pc                      ; can't restore all flags. CV will be preserved
+
+CallVecTooHigh
+        msr     AL, CPSR_f, r12
+        MOV     pc, lr
+  |
         Pull    pc,,^                   ; we don't expect to get to here
                                         ; (should always be claimed),
                                         ; but return to caller, restoring flags
+  ]
 
 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 ;Add_To_vector(n, Addressess)
@@ -311,11 +333,7 @@ ClaimVector_SWICode   ROUT
 
       Push "R0-R4, link"
 
- [ IrqsInClaimRelease
-        MOV     R4, #I_bit
-        TST     R4, PC                  ; is I_bit set ?
-        TEQEQP  R4, PC                  ; No, then set it, save changed bits
-        MOVNE   R4, #0                  ; Else no changed bits
+        PHPSEI  R4, R14                 ; Disable IRQs
 
         MOV     R3, #0                  ; List of de-linked nodes is empty
         LDR     R11, =VecPtrTab         ; Get ptr to table of head pointers
@@ -325,7 +343,7 @@ ClaimVector_SWICode   ROUT
         MOVVC   R3, R12                 ; New head of de-linked nodes
         BVC     %BT01                   ; Repeat until all nodes de-linked
 
-        TEQP    R4, PC                  ; Restore IRQ state
+        PLP     R4                      ; Restore IRQ state
 
 ; Free the list of de-linked nodes, pointed to by R3, enter with VS
 
@@ -333,14 +351,7 @@ ClaimVector_SWICode   ROUT
         BLVC    FreeNode                ; Free the node pointed to by R12
         SUBS    R12, R3, #0             ; Any more nodes to free?
         BNE     %BT02                   ; Yes then jump
- |
-      TEQP  PC, #SVC_mode+I_bit     ; IRQs off while holding context.
-      LDR   R11, =VecPtrTab         ; Point at table of head pointers
-      LDR   R10, [R11, R0, LSL #2]! ; R10 "nextblock" := !oldptr,
-                                    ; point R11 at the table entry "oldptr"
-01    BL    FreeLink
-      BVC   %BT01                   ; loop with chain pointers still set
- ]
+
 GoForAddToVec
       LDR   R11, =VecPtrTab         ; Point at table of head pointers
 
@@ -361,7 +372,7 @@ GoForAddToVec
   ]
       BVS   BadClaimVector          ; Failed : Exit
 
-      TEQP  PC, #SVC_mode+I_bit     ; force noirq
+      WritePSRc SVC_mode+I_bit, R3  ; force noirq
       LDR   R3, [R11]               ; "nextblock" :=vecptrtab!(n*4)
       STMIA R2, {R3, R4, R10}       ; Atomic Operation thus links in the new
                                     ; routine
@@ -392,31 +403,17 @@ ReleaseVector_SWICode
       SETV  CS
       BVS   BadVectorRelease
 
- [ IrqsInClaimRelease
         Push    "R0-R2,R9,link"
 
-        MOV     R9, #I_bit
-        TST     R9, PC                  ; is I_bit set ?
-        TEQEQP  R9, PC                  ; No, then set it, R9 = changed bits
-        MOVNE   R9, #0                  ; Else R9=0 for no change
+        PHPSEI  R9, R14                 ; Disable IRQs
 
         LDR     R11, =VecPtrTab         ; Get ptr to table of head pointers
         LDR     R10, [R11, R0, LSL #2]! ; R10 "nextblock" := *oldptr, R11= root ptr
         BL      FindAndDelinkNode       ; R10,R11->R10,R11,R12
-        TEQP    R9, PC                  ; Restore IRQ state
+        PLP     R9                      ; Restore IRQ state
         BLVC    FreeNode                ; If found, free the node in R12
 
         Pull    "R0-R2,R9,link"
- |
-      Push "R0-R2, link"
-
-      TEQP  PC, #SVC_mode+I_bit     ; IRQs off while holding context.
-      LDR   R11, =VecPtrTab         ; Point at table of head pointers
-      LDR   R10, [R11, R0, LSL #2]! ; R10 "nextblock" := !oldptr,
-                                    ; point R11 at the table entry "oldptr"
-      BL    FreeLink
-      Pull "R0-R2, link"
- ]
 
 BadVectorRelease
       ADRVS R0, ErrorBlock_NaffRelease
@@ -449,7 +446,7 @@ BadVectorRelease
 
 FindAndDelinkNode
         CMP     R10, #0                 ; End of chain?
-        ORREQS  PC, lr, #V_bit          ; Yes, return error
+        RETURNVS EQ                     ; Yes, return error
 
         LDR     R12, [R10, #VecWSpace]
         CMP     R12, R2                 ; Workspace matches?
@@ -462,7 +459,7 @@ FindAndDelinkNode
         MOV     R12, R10                ; R12-> node to de-link
         LDR     R10, [R12, #TailPtr]    ; Get link to next node
         STR     R10, [R11]              ; Previous node's link -> next node
-        BICS    PC, lr, #V_bit          ; Return no error
+        RETURNVC EQ                     ; Return no error
 
 ; Return node to heap space
 ; In:
@@ -592,8 +589,10 @@ defaultvectab
 
 NaffVector ROUT
 Def_100HZ
-        Pull    lr                      ; Claim vector, do nowt
-        BICS    pc, lr, #V_bit
+        mrs     AL, lr, CPSR
+        BIC     lr, lr, #V_bit
+        msr     AL, CPSR_f, lr          ; Clear V, preserve rest
+        LDR     pc, [sp], #4            ; Claim vector, do nowt
 
 ; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 ; SWIs to save any vector entries pointing into application workspace
@@ -612,7 +611,7 @@ Application_Delink ROUT
 
       MOV   R3, #NVECTORS-1
       LDR   R4, [R3, #AplWorkSize-(NVECTORS-1)]
-      TEQP  PC, #SVC_mode+I_bit     ; IRQs off while holding context.
+      SETPSR I_bit, R3           ; IRQs off while holding context.
 
 03    LDR   R11, =VecPtrTab         ; Point at table of head pointers
       ADD   R10, R11, R3, LSL #2
@@ -741,8 +740,8 @@ Issue_Service ROUT             ; R1 is service number, R2 may be a parameter
        CMP      R1,#ServMinUsrNumber
        BHS      %FT84
 ;call anyone on the appropriate Sys chain
-       LDR      R10,=Serv_SysChains
-       LDR      R10,[R10]
+       MOV      R10,#0
+       LDR      R10,[R10,#Serv_SysChains]
        CMP      R10,#0
        BEQ      %FT88
        LDR      R11,[R10,R1,LSL #2]             ;pick up the chain anchor
@@ -797,8 +796,8 @@ Issue_Service ROUT             ; R1 is service number, R2 may be a parameter
 ;
 ;call everyone on the chain of Awkward modules, always passing service number in R1
 88
-       LDR      R10,=Serv_AwkwardChain
-       LDR      R11,[R10]
+       MOV      R10,#0
+       LDR      R11,[R10,#Serv_AwkwardChain]
        CMP      R11,#0
        BEQ      %FT01
        LDR      R10,[R11,#ServChain_Size]
@@ -912,17 +911,11 @@ sam001
        STRNEB   R10, [R10, #MOShasFIQ]
        MOVNE    r1, #Service_Serviced
 fakeservicecall
-       [ {FALSE}
-       Push     PC, EQ                         ; return address
-       SUBEQ    stack, stack, #4*4             ; pseudo- r9-r12
-       BEQ      %BT05                          ; wacky pseudo-BL!
-	|
 	; do it this way to cope with ARM v4/v3 differences on storing PC
        SUBEQ    stack,stack,#20
        STREQ    PC,[stack,#16]
        BEQ      %BT05
-       MOV	R0,R0
-	]
+       MOV      r0, r0
        MOV      r10, #0
        LDRB     r9, [r10, #FIQclaim_interlock]
        STRB     r10, [r10, #FIQclaim_interlock]
@@ -993,15 +986,15 @@ checkmoshandlers
 ; SWI to call a vector
 ;************************************************
 CallAVector_SWI  ; R9 is the vector number (!!)
-       Push     "lr"
+       STR       lr, [sp, #-4]!         ; save caller PSR on stack
        MOV       R10, R9
-       ORR       R14, R14, #SVC_mode
-       TEQP      PC, R14             ; restore caller CCs
+       msr       AL, CPSR_f, R14        ; restore caller CCs
        BL        CallVector
-       MOV       R10, PC, LSR #28    ; restore CCs
-       Pull     "lr"
+       mrs       AL, r10, CPSR          ; restore CCs
+       LDR       lr, [sp], #4
+       AND       r10, r10, #&F0000000
        BIC       lr, lr, #&F0000000
-       ORR       lr, lr, R10, LSL #28
+       ORR       lr, lr, r10
        ExitSWIHandler
 
 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -1099,60 +1092,14 @@ ValidateAddress_Code ROUT
         LDR     R12, [R10, #AplWorkSize]
         BL      RangeCheck
 
- [ :LNOT: NewStyle_Screen
-        VDWS    R11
-        MOV     R12, #ScreenEndAdr
-        LDR     R11, [R11, #TotalScreenSize]
-        ADD     R12, R12, R11
-        SUB     R11, R12, R11, LSL #1
-        BL      RangeCheck
- ]
-
- [ NewStyle_SysHeap
         MOV     r11, #SysHeapChunkAddress       ; need to still check 1st 8K
         ADD     r12, r11, #SysHeapStart-SysHeapChunkAddress
         BL      RangeCheck
- |
-        LDR     R11, =SysHeapStart
-        LDR     R12, [R11, #:INDEX: hpdend]
-        ADD     R12, R11, R12
-        MOV     R11, #SysHeapChunkAddress
-        BL      RangeCheck
- ]
-
- [ :LNOT: NewStyle_RMA
-        MOV     R11, #RMAAddress
-        LDR     R12, [R11, #:INDEX: hpdend]
-        ADD     R12, R11, R12
-        BL      RangeCheck
- ]
-
- [ :LNOT: NewStyle_SpriteArea
-        LDR     R12, [R10, #SpriteSize]
-        ADD     R12, R12, #SpriteSpaceAddress
-        MOV     R11, #SpriteSpaceAddress
-        BL      RangeCheck
- ]
-
- [ :LNOT: NewStyle_RAMDisc
-        LDR     R12, [R10, #RAMDiscSize]
-        ADD     R12, R12, #RAMDiscAddress
-        MOV     R11, #RAMDiscAddress
-        BL      RangeCheck
- ]
-
- [ :LNOT: NewStyle_FontArea
-        LDR     R12, [R10, #FontCacheSize]
-        ADD     R12, R12, #FontCacheAddress
-        MOV     R11, #FontCacheAddress
-        BL      RangeCheck
- ]
 
         MOV     R11, #CursorChunkAddress
         ADD     R12, R11, #32*1024
         BL      RangeCheck
 
- [ NewCDA
 ; not in one of those ranges, so check against dynamic area list
         MOV     r10, #DAList
 10
@@ -1174,7 +1121,6 @@ ValidateAddress_Code ROUT
         CMP     r1, r12                 ; else if range ends before end+1 of this area
         BCC     AddressIsValid          ; then it's valid
 20
- ]
 
 ; not in one of those ranges, so issue service so modules can add other valid areas