ExtraSWIs

; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > ExtraSWIs

 [ ProcessorVectors

;----------------------------------------------------------------------------------------
; ClaimProcVecSWI
;
;       In:     r0 = vector and flags
;                       bit     meaning
;                       0-7     vector number
;                               0 = 'Branch through 0' vector
;                               1 = Undefined instruction
;                               2 = SWI
;                               3 = Prefetch abort
;                               4 = Data abort
;                               5 = Address exception (only on ARM 2 & 3)
;                               6 = IRQ
;                               7+ = reserved for future use
;                       8       0 = release
;                               1 = claim
;                       9-31    reserved (set to 0)
;               r1 = replacement value
;               r2 = value which should currently be on vector (only needed for release)
;
;       Out:    r1 = value which has been replaced (only returned on claim)
;
;       Allows a module to attach itself to one of the processor vectors.
;
ClaimProcVecSWI ROUT
        Entry   "r3-r5"

        AND     r3, r0, #&FF            ; Get vector number.
        CMP     r3, #(ProcVec_End-ProcVec_Start):SHR:2
        ADRCSL  r0, ErrorBlock_BadClaimNum
        BCS     %FT30

        MOV     r4, r1                  ; r4 = replacement value
        LDR     r5, =ZeroPage+ProcVec_Start
        PHPSEI                          ; Disable IRQs while we mess around with vectors.

        TST     r0, #1:SHL:8
        LDRNE   r1, [r5, r3, LSL #2]!   ; If claiming then return current value (r5->vector to replace).
        BNE     %FT10

        LDR     r3, [r5, r3, LSL #2]!   ; Releasing so get current value (r5->vector to replace).
        TEQ     r2, r3                  ; Make sure it's what the caller thinks it is.
        ADRNEL  r0, ErrorBlock_NaffRelease
        BNE     %FT20
10
        STR     r4, [r5]                ; Store replacement value.
        PLP                             ; Restore IRQs.
        PullEnv
        ExitSWIHandler

20
        PLP                             ; Restore IRQs and return error.
30
  [ International
        BL      TranslateError
  ]
        PullEnv
        B       SLVK_SetV

 ]


        END