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Commit 2247d8e9 authored by Jeffrey Lee's avatar Jeffrey Lee
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Add zero page relocation support 

Detail:
  A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
  At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
  There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
  * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
  * ShareFS needs unplugging/removing since it can't cope with it yet
  * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
  * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
  The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
  Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
  File changes:
  - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
  - hdr/Copro15ops - Corrected $quick handling in myISB macro
  - hdr/Options - Added ideal setting for us to use for HiProcVecs
  - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
  - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
  - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
  - s/KbdResPC - Disable compilation of dead code
  - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
Admin:
  Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
  High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.


Version 5.35, 4.79.2.98.2.48. Tagged as 'Kernel-5_35-4_79_2_98_2_48'
parent 26a09556
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Showing with 581 additions and 584 deletions
VersionASM
View file @ 2247d8e9
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.47"
Module_Date SETS "07 Aug 2011"
Module_ApplicationDate SETS "07-Aug-11"
Module_MinorVersion SETS "4.79.2.98.2.48"
Module_Date SETS "08 Aug 2011"
Module_ApplicationDate SETS "08-Aug-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.47)"
Module_HelpVersion SETS "5.35 (07 Aug 2011) 4.79.2.98.2.47"
Module_FullVersion SETS "5.35 (4.79.2.98.2.48)"
Module_HelpVersion SETS "5.35 (08 Aug 2011) 4.79.2.98.2.48"
END
VersionNum
View file @ 2247d8e9
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.47
#define Module_Date_CMHG 07 Aug 2011
#define Module_MinorVersion_CMHG 4.79.2.98.2.48
#define Module_Date_CMHG 08 Aug 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.47"
#define Module_Date "07 Aug 2011"
#define Module_MinorVersion "4.79.2.98.2.48"
#define Module_Date "08 Aug 2011"
#define Module_ApplicationDate "07-Aug-11"
#define Module_ApplicationDate "08-Aug-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.47)"
#define Module_HelpVersion "5.35 (07 Aug 2011) 4.79.2.98.2.47"
#define Module_FullVersion "5.35 (4.79.2.98.2.48)"
#define Module_HelpVersion "5.35 (08 Aug 2011) 4.79.2.98.2.48"
#define Module_LibraryVersionInfo "5:35"
hdr/ARMops
View file @ 2247d8e9
......@@ -66,27 +66,27 @@ CPUFlag_HiProcVecs * 1:SHL:20 ; High processor vectors are in
; The macro to do an ARM operation. All ARM operations are expected
; to corrupt a1 only
; This macro corrupts ip unless $zero reg is supplied
; This macro corrupts ip unless $zeropage reg is supplied
MACRO
ARMop $op, $cond, $tailcall, $zero
[ "$zero" = ""
MOV$cond ip, #ZeroPage
ARMop $op, $cond, $tailcall, $zeropage
[ "$zeropage" = ""
LDR$cond ip, =ZeroPage
]
[ "$tailcall" = ""
MOV$cond lr, pc
]
[ "$zero" = ""
[ "$zeropage" = ""
LDR$cond pc, [ip, #Proc_$op]
|
LDR$cond pc, [$zero, #Proc_$op]
LDR$cond pc, [$zeropage, #Proc_$op]
]
MEND
MACRO
ChangedProcVecs $tmp
[ XScaleJTAGDebug
MOV $tmp, #0
LDR $tmp, =ZeroPage
LDR $tmp, [$tmp, #ProcessorFlags]
TST $tmp, #CPUFlag_XScaleJTAGconnected
BEQ %FT01
......
hdr/Copro15ops
View file @ 2247d8e9
......@@ -572,7 +572,7 @@ C15 CN 15
|
[ NoARMv7
; ARMv6, use legacy MCR op
[ "$quick"="q"
[ "$quick"=""
MOV$cond $temp,#0
]
MCR$cond p15,0,$temp,c7,c5,4
......
hdr/Options
View file @ 2247d8e9
......@@ -357,7 +357,9 @@ GetMessages SETS ""
]
GBLL HiProcVecs ; Relocate processor vectors and first 16K of workspace to &FFFF0000
HiProcVecs SETL {FALSE} ; Coming soon!
HiProcVecs SETL {FALSE} ; Leave off for now
; In an ideal world, we'd use something like this:
; HiProcVecs SETL M_Tungsten :LOR: :LNOT: NoARMv6
GBLL DebugForcedReset ; debug forced hard resets
DebugForcedReset SETL {FALSE}
......
s/AMBControl/allocate
View file @ 2247d8e9
......@@ -64,7 +64,7 @@ allocate
STR R4,[R2,#AMBNode_Npages] ;number of pages = 0 (so far)
MOV R4,#ApplicationStart
STR R4,[R2,#AMBNode_startaddr]
LDR R4,=AppSpaceDANode
LDR R4,=ZeroPage+AppSpaceDANode
LDR R4,[R4,#DANode_Flags]
AND R4,R4,#&7F
STR R4,[R2,#AMBNode_PPL] ;PPL from bottom 8 bits of DA flags
......
s/AMBControl/growp
View file @ 2247d8e9
......@@ -34,8 +34,8 @@ growpages ROUT
MOV R0,R2 ;R0 -> AMB node
LDR R1,=FreePoolDANode ;R1 := source for pages
LDR R2,=AppSpaceDANode ;R2 := dest for pages
LDR R1,=ZeroPage+FreePoolDANode ;R1 := source for pages
LDR R2,=ZeroPage+AppSpaceDANode ;R2 := dest for pages
LDR R7,[R0,#AMBNode_Npages] ;R7 := current no. of pages
SUB R3,R6,R7 ;no. of pages required from FreePool
......@@ -88,7 +88,7 @@ growpages ROUT
LDR R5,[R2,#DANode_Size]
ADD R5,R5,R3,LSL #Log2PageSize
STR R5,[R2,#DANode_Size] ;new AppSpace size
MOV R6,#0
LDR R6,=ZeroPage
STR R5,[R6,#MemLimit] ;update MemLimit
02
......@@ -115,7 +115,7 @@ growp_TryToShrinkShrinkables ROUT
MOV R11,R1 ; -> FreePool DANode
MOV R1,R3,LSL #Log2PageSize ;amount we need in FreePool
MOV R2,R4,LSL #Log2PageSize ;amount we have in FreePool
MOV R10,#DAList
LDR R10,=ZeroPage+DAList
ASSERT DANode_Link = 0 ;because DAList has only link
10
LDR R10,[R10,#DANode_Link] ;and load next
......
s/AMBControl/main
View file @ 2247d8e9
......@@ -58,7 +58,7 @@ AMBControl_Init
STR R0,[R2]
;claim block for PhysBin array
LDR R3,=MaxCamEntry
LDR R3,=ZeroPage+MaxCamEntry
LDR R3,[R3]
ADD R3,R3,#1 ;no. of RAM pages extant
MOV R3,R3,LSR #AMBPhysBinShift ;no. of bin entries reqd.
......@@ -69,7 +69,7 @@ AMBControl_Init
STR R2,AMBPhysBin
;init PhysBin
MOV R0,#PhysRamTable
LDR R0,=ZeroPage+PhysRamTable
LDR R3,AMBPhysBin
LDR R4,AMBPhysBinEntries
LDMIA R0!,{R1,R2} ;address,size of first physical fragment
......@@ -90,7 +90,7 @@ AMBControl_Init
STR R1,[R1,#AMBNode_prev] ;anchor prev initially -> anchor (empty list)
STR R1,[R1,#AMBNode_next] ;anchor next initially -> anchor (empty list)
[ AMB_LazyMapIn
MOV R0,#0
LDR R0,=ZeroPage
LDR R0,[R0,#ProcessorFlags]
TST R0,#CPUFlag_BaseRestored
MOVEQ R1,#AMBFlag_LazyMapIn_disable ;laziness not supported if we can't trivially restart after abort (because we're lazy!)
......@@ -99,7 +99,7 @@ AMBControl_Init
MOVNE R1,#AMBFlag_LazyMapIn_disable
STR R1,AMBFlags
]
MOV R0,#AMBControl_ws
LDR R0,=ZeroPage+AMBControl_ws
STR R12,[R0] ;now initialisation is complete
Pull "R0-R4,R12,PC"
......@@ -114,7 +114,7 @@ AMBControl_Init
; other regs. depend on reason code
AMBControlSWI
MOV R12,#AMBControl_ws
LDR R12,=ZeroPage+AMBControl_ws
LDR R12,[R12]
AND R11,R0,#&FF
......
s/AMBControl/mapslot
View file @ 2247d8e9
......@@ -121,12 +121,12 @@ ms_mapdone
;update AppSpace kernel stuff
LDR R2,[R1,#AMBNode_Npages]
LDR R3,=AppSpaceDANode
LDR R3,=ZeroPage+AppSpaceDANode
MOV R0,#ApplicationStart
CMP R5,#-1
ADDNE R0,R0,R2,LSL #Log2PageSize
STR R0,[R3,#DANode_Size]
MOV R3,#0
LDR R3,=ZeroPage
STR R0,[R3,#MemLimit]
CMP R5,#-1
MOVEQ R3,#0
......
s/AMBControl/memmap
View file @ 2247d8e9
......@@ -63,7 +63,7 @@
;
AMB_LazyFixUp ROUT
MOV r7,r12
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT90 ;not initialised!
......@@ -127,7 +127,7 @@ AMB_LazyFixUp ROUT
MOV r5,#L2PT
STR r4,[r5,r0,LSL #2] ;update L2PT
;
MOV r5,#0
LDR r5,=ZeroPage
LDR r5,[r5,#CamEntriesPointer]
ADD r5,r5,r6,LSL #3 ;r5 -> CAM entry affected
MOVS r0,r0,LSL #Log2PageSize ;address is now ordinary again, and must be non-zero
......@@ -184,7 +184,7 @@ AMB_MakeHonestLA ROUT
CMP r0,#AbsMaxAppSize ;quick dismiss if definitely not app address
MOVHS pc,lr
Push "r1,r12,lr"
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT90 ;we're dormant!
......@@ -205,11 +205,11 @@ AMB_MakeHonestLA ROUT
;
AMB_MakeHonestPN ROUT
Push "r1-r3,r12,lr"
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT90 ;we're dormant!
MOV r14,#0
LDR r14,=ZeroPage
LDR r1,[r14,#MaxCamEntry]
CMP r0,r1
BHI %FT90 ;invalid page number
......@@ -317,7 +317,7 @@ AMB_movepagesin_CAM ROUT
MOV lr,r9
MOV r9,r3
MOV r11,#0
LDR r11,=ZeroPage
LDR r11,[r11,#CamEntriesPointer] ;r11 -> CAM
CMP r8,#8
......@@ -370,7 +370,7 @@ AMB_movepagesout_CAM ROUT
MOV lr,r9
LDR r9,=DuffEntry
MOV r11,#0
LDR r11,=ZeroPage
LDR r11,[r11,#CamEntriesPointer] ;r11 -> CAM
CMP r8,#8
......@@ -474,7 +474,7 @@ AMB_SetMemMapEntries ROUT
MOV r10,r4 ;ptr to next page number
LDR r2,[r10] ;page number of 1st page
MOV r7,#0
LDR r7,=ZeroPage
LDR r7,[r7,#CamEntriesPointer] ;r7 -> CAM
ADD r1,r7,r2,LSL #3 ;r1 -> CAM entry for 1st page
[ AMB_LimpidFreePool
......@@ -503,7 +503,7 @@ AMB_SetMemMapEntries ROUT
;
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingUncachedEntries,,,r3 ;no cache worries, hoorah
MOV r3,r5
BL AMB_movepagesout_L2PT ;unmap 'em from where they are
......@@ -515,7 +515,7 @@ AMB_smme_mapnotlimpid
;
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingEntries,,,r3 ;
MOV r3,r5
BL AMB_movepagesout_L2PT
......@@ -528,7 +528,7 @@ AMB_smme_mapnotlimpid
AMB_smme_mapin
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingUncachedEntries,,,r3 ;TLB coherency, possibly not needed (TLBs shouldn't cache 0 entries)
MOV r3,r5
BL AMB_movepagesin_L2PT
......@@ -540,7 +540,7 @@ AMB_smme_mapin
AMB_smme_mapout
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingEntries,,,r3 ;
LDR r3,=DuffEntry
BL AMB_movepagesout_L2PT
......@@ -571,12 +571,11 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
Push "r0-r11,lr"
MOV r10,r4 ;ptr to page list
MOV r7,#0
LDR r7,[r7,#CamEntriesPointer] ;r7 -> CAM
LDR r2,=ZeroPage
MOV r9,#AP_Duff ;permissions for DuffEntry
LDR r1,=DuffEntry ;means Nowhere, in CAM
LDR r7,[r2,#CamEntriesPointer] ;r7 -> CAM
MOV r4,#ApplicationStart ;log. address of first page
MOV r2,#0 ;r2 is zero during sparse map out
LDR r1,=DuffEntry ;means Nowhere, in CAM
;if the number of pages mapped in is small enough, we'll do cache/TLB coherency on
;just those pages, else global (performance decision, threshold probably not critical)
......@@ -605,6 +604,7 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
BEQ %FT16
TEQ r6, #0
BNE %FT14 ;check for coherency as we go
LDR r2,=ZeroPage
MOV r0,r4 ;address of page
ARMop MMU_ChangingEntry,,,r2
14
......@@ -612,6 +612,7 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
ADD r0,r7,r0,LSL #3 ;r0 -> CAM entry for page
STMIA r0,{r1,r9} ;CAM entry for page set to DuffEntry,AP_Duff
LDR lr,=L2PT ;lr -> L2PT
MOV r2, #0
STR r2,[lr,r4,LSR #(Log2PageSize-2)] ;L2PT entry for page set to 0 (means translation fault)
SUBS r3,r3,#1
STREQ r2,[r5,#-4] ;make sure we clear last word of bitmap, and...
......@@ -621,7 +622,9 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
ADD r4,r4,#PageSize ;next logical address
MOVS r8,r8,LSL #1 ;if 32 bits processed...
BNE %BT12
STR r2,[r5,#-4] ;zero word of bitmap we've just traversed (r2 is 0)
MOV r2, #0
STR r2,[r5,#-4] ;zero word of bitmap we've just traversed
LDR r2,=ZeroPage
B %BT10
20
......@@ -645,7 +648,7 @@ AMB_MakeUnsparse ROUT
SUB r0,r0,#1
MOVS r0,r0,LSR #Log2PageSize
BEQ %FT20
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT20
......@@ -700,7 +703,7 @@ AMB_FindMemMapEntries ROUT
Push "r0-r11,lr"
;initialise r0,r1,r2 as physical RAM chunk cache for AMB_r11topagenum routine
MOV r9,#PhysRamTable
LDR r9,=ZeroPage+PhysRamTable
LDMIA r9,{r0,r1} ;r0,r1 := phys addr,size of chunk
ADD r1,r1,r0 ;r0,r1 := lowest addr,highest addr + 1 of chunk
MOV r2,#0 ;r2 := first page number of chunk
......@@ -761,7 +764,7 @@ AMB_r11topagenum ROUT
ADD r11,r11,r2 ;page number
MOV pc,lr
10
MOV r9,#PhysRamTable
LDR r9,=ZeroPage+PhysRamTable
MOV r2,#0 ;start at page number 0
20
LDMIA r9!,{r0,r1} ;r0,r1 := phys addr,size of chunk
......
s/AMBControl/service
View file @ 2247d8e9
......@@ -30,7 +30,7 @@
AMBsrv_memorymoved ROUT
Push "R3-R6,R12,LR"
MOV R12,#AMBControl_ws
LDR R12,=ZeroPage+AMBControl_ws
LDR R12,[R12]
CMP R12,#0
Pull "R3-R6,R12,PC",EQ ;AMBControl not initialised yet!
......@@ -41,7 +41,7 @@ AMBsrv_memorymoved ROUT
LDR R3,[R4,#AMBNode_Npages]
LDR R6,=AppSpaceDANode
LDR R6,=ZeroPage+AppSpaceDANode
LDR R6,[R6,#DANode_Size]
SUB R6,R6,#ApplicationStart
MOV R6,R6,LSR #Log2PageSize
......@@ -172,7 +172,7 @@ AMBsrv_memorymoved ROUT
AMBsrv_pagessafe ROUT
Push "R0-R1,R5-R10,R12,LR"
MOV R12,#AMBControl_ws
LDR R12,=ZeroPage+AMBControl_ws
LDR R12,[R12]
CMP R12,#0
Pull "R0-R1,R5-R10,R12,PC",EQ ;AMBControl not initialised yet!
......
s/AMBControl/shrinkp
View file @ 2247d8e9
......@@ -61,8 +61,8 @@ shrinkpages
TST R3,#1 ;check flag
MOVEQ R1,#0 ;source is not App space
LDRNE R1,=AppSpaceDANode ;source is App space
LDR R2,=FreePoolDANode ;dest
LDRNE R1,=ZeroPage+AppSpaceDANode ;source is App space
LDR R2,=ZeroPage+FreePoolDANode ;dest
LDR R7,[R0,#AMBNode_Npages] ;R7 := current number of pages
SUBS R3,R7,R6 ;R3 := no. of pages to move
......@@ -90,7 +90,7 @@ shrinkpages
LDRNE R0,[R1,#DANode_Size]
SUBNE R0,R0,R3,LSL #Log2PageSize
STRNE R0,[R1,#DANode_Size]
MOVNE R5,#0
LDRNE R5,=ZeroPage
STRNE R0,[R5,#MemLimit] ;update MemLimit
02
......
s/ARM600
View file @ 2247d8e9
This diff is collapsed.
s/ARMops
View file @ 2247d8e9
......@@ -72,7 +72,7 @@ ARM_Analyse
Push "v1,v2,v5,v6,v7,lr"
ARM_read_ID v1
ARM_read_cachetype v2
MOV v6, #ZeroPage
LDR v6, =ZeroPage
ADRL v7, KnownCPUTable
FindARMloop
......@@ -111,6 +111,9 @@ FindARMloop
|
MOV v5, #0
]
[ HiProcVecs
ORR v5, v5, #CPUFlag_HiProcVecs
]
TST v2, #CT_S
ORRNE v5, v5, #CPUFlag_SplitCache+CPUFlag_SynchroniseCodeAreas
......@@ -147,9 +150,10 @@ FindARMloop
BNE %FT35
; Do we get vector exceptions on read?
MOV a1, #0
LDR a2, =ZeroPage
MOV a1, a2
LDR a1, [a1] ; If this aborts a1 will be left unchanged
TEQ a1, #0
TEQ a1, a2
ORREQ v5, v5, #CPUFlag_VectorReadException
]
35
......@@ -342,8 +346,7 @@ Analyse_WB_CR7_LDa
ADRL a1, MMU_ChangingUncachedEntries_WB_CR7_LDa
STR a1, [v6, #Proc_MMU_ChangingUncachedEntries]
MOV a1, #0
LDRB a2, [a1, #DCache_Associativity]
LDRB a2, [v6, #DCache_Associativity]
MOV a3, #256
MOV a4, #8 ; to find log2(ASSOC), rounded up
......@@ -357,15 +360,15 @@ Analyse_WB_CR7_LDa_L1
RSB a2, a4, #32
MOV a3, #1
MOV a3, a3, LSL a2
STR a3, [a1, #DCache_IndexBit]
LDR a4, [a1, #DCache_NSets]
LDRB a2, [a1, #DCache_LineLen]
STR a3, [v6, #DCache_IndexBit]
LDR a4, [v6, #DCache_NSets]
LDRB a2, [v6, #DCache_LineLen]
SUB a4, a4, #1
MUL a4, a2, a4
STR a4, [a1, #DCache_IndexSegStart]
STR a4, [v6, #DCache_IndexSegStart]
MOV a2, #64*1024 ; arbitrary-ish
STR a2, [a1, #DCache_RangeThreshold]
STR a2, [v6, #DCache_RangeThreshold]
ADRL a1, XCBTableWBR ; assume read-allocate WB/WT cache
STR a1, [v6, #MMU_PCBTrans]
......@@ -421,14 +424,13 @@ Analyse_WB_Crd
ADRL a1, MMU_ChangingUncachedEntries_WB_Crd
STR a1, [v6, #Proc_MMU_ChangingUncachedEntries]
MOV a1, #0
LDR a2, =DCacheCleanAddress
STR a2, [a1, #DCache_CleanBaseAddress]
STR a2, [a1, #DCache_CleanNextAddress]
STR a2, [v6, #DCache_CleanBaseAddress]
STR a2, [v6, #DCache_CleanNextAddress]
MOV a2, #64*1024 ;arbitrary-ish threshold
STR a2, [a1, #DCache_RangeThreshold]
STR a2, [v6, #DCache_RangeThreshold]
LDRB a2, [a1, #ProcessorType]
LDRB a2, [v6, #ProcessorType]
TEQ a2, #SA110
ADREQL a2, XCBTableSA110
BEQ Analyse_WB_Crd_finish
......@@ -437,7 +439,7 @@ Analyse_WB_Crd
ADREQL a2, XCBTableSA1110
ADRNEL a2, XCBTableWBR
Analyse_WB_Crd_finish
STR a2, [a1, #MMU_PCBTrans]
STR a2, [v6, #MMU_PCBTrans]
B %FT90
Analyse_WB_Cal_LD
......@@ -489,16 +491,15 @@ Analyse_WB_Cal_LD
ADRL a1, MMU_ChangingUncachedEntries_WB_Cal_LD
STR a1, [v6, #Proc_MMU_ChangingUncachedEntries]
MOV a1, #0
LDR a2, =DCacheCleanAddress
STR a2, [a1, #DCache_CleanBaseAddress]
STR a2, [a1, #DCache_CleanNextAddress]
STR a2, [v6, #DCache_CleanBaseAddress]
STR a2, [v6, #DCache_CleanNextAddress]
[ XScaleMiniCache
! 1, "You need to arrange for XScale mini-cache clean area to be mini-cacheable"
LDR a2, =DCacheCleanAddress + 4 * 32*1024
STR a2, [a1, #MCache_CleanBaseAddress]
STR a2, [a1, #MCache_CleanNextAddress]
STR a2, [v6, #MCache_CleanBaseAddress]
STR a2, [v6, #MCache_CleanNextAddress]
]
......@@ -508,14 +509,14 @@ Analyse_WB_Cal_LD
|
MOV a2, #32*1024
]
STR a2, [a1, #DCache_RangeThreshold]
STR a2, [v6, #DCache_RangeThreshold]
; enable full coprocessor access
LDR a2, =&3FFF
MCR p15, 0, a2, c15, c1
ADRL a2, XCBTableXScaleWA ; choose between RA and WA here
STR a2, [a1, #MMU_PCBTrans]
STR a2, [v6, #MMU_PCBTrans]
B %FT90
......@@ -769,7 +770,7 @@ KnownCPUFlags
ARM_Analyse_Fancy
Push "v1,v2,v5,v6,v7,lr"
ARM_read_ID v1
MOV v6, #ZeroPage
LDR v6, =ZeroPage
ADRL v7, KnownCPUTable_Fancy
10
LDMIA v7!, {a1, a2}
......@@ -791,6 +792,9 @@ ARM_Analyse_Fancy
STRB a1, [v6, #Cache_Type]
MOV v5, #CPUFlag_32bitOS+CPUFlag_No26bitMode ; 26bit has been obsolete for a long time
[ HiProcVecs
ORR v5, v5, #CPUFlag_HiProcVecs
]
; Work out whether the cache info is in ARMv6 or ARMv7 style
MRC p15, 0, a1, c0, c0, 1
......@@ -1132,7 +1136,7 @@ Cache_CleanAll_WB_CR7_LDa ROUT
; DCache_IndexSegStart = &000000E0 (start at index=0, segment = 7)
;
Push "a2, ip"
MOV ip, #0
LDR ip, =ZeroPage
LDRB a1, [ip, #DCache_LineLen] ; segment field starts at this bit
LDR a2, [ip, #DCache_IndexBit] ; index field starts at this bit
LDR ip, [ip, #DCache_IndexSegStart] ; starting value, with index at min, seg at max
......@@ -1153,7 +1157,7 @@ Cache_CleanInvalidateAll_WB_CR7_LDa ROUT
; similar to Cache_CleanAll, but does clean&invalidate of Dcache, and invalidates ICache
;
Push "a2, ip"
MOV ip, #0
LDR ip, =ZeroPage
LDRB a1, [ip, #DCache_LineLen] ; segment field starts at this bit
LDR a2, [ip, #DCache_IndexBit] ; index field starts at this bit
LDR ip, [ip, #DCache_IndexSegStart] ; starting value, with index at min, seg at max
......@@ -1180,7 +1184,7 @@ Cache_InvalidateAll_WB_CR7_LDa ROUT
Cache_RangeThreshold_WB_CR7_LDa ROUT
MOV a1, #0
LDR a1, =ZeroPage
LDR a1, [a1, #DCache_RangeThreshold]
MOV pc, lr
......@@ -1226,7 +1230,7 @@ IMB_Range_WB_CR7_LDa ROUT
ADD a2, a2, a1
BHS IMB_Full_WB_CR7_LDa
Push "lr"
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ; clean DCache entry by VA
......@@ -1250,7 +1254,7 @@ MMU_Changing_WB_CR7_LDa ROUT
MMU_ChangingEntry_WB_CR7_LDa ROUT
Push "a2, lr"
ADD a2, a1, #PageSize
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c14, 1 ; clean&invalidate DCache entry
......@@ -1271,13 +1275,12 @@ MMU_ChangingEntry_WB_CR7_LDa ROUT
MMU_ChangingEntries_WB_CR7_LDa ROUT
Push "a2, a3, lr"
MOV a2, a2, LSL #Log2PageSize
MOV a3, #0
LDR a3, [a3, #DCache_RangeThreshold] ;check whether cheaper to do global clean
LDR lr, =ZeroPage
LDR a3, [lr, #DCache_RangeThreshold] ;check whether cheaper to do global clean
CMP a2, a3
BHS %FT30
ADD a2, a2, a1 ;clean end address (exclusive)
MOV a3, #0
LDRB a3, [a3, #DCache_LineLen]
LDRB a3, [lr, #DCache_LineLen]
MOV lr, a1
10
MCR p15, 0, a1, c7, c14, 1 ; clean&invalidate DCache entry
......@@ -1365,7 +1368,7 @@ Cache_CleanAll_WB_Crd ROUT
;
Push "a2-a4, v1, v2, lr"
MOV lr, #0
LDR lr, =ZeroPage
LDR a1, [lr, #DCache_CleanBaseAddress]
LDR a2, =DCache_CleanNextAddress
LDR a3, [lr, #DCache_Size]
......@@ -1409,7 +1412,7 @@ Cache_InvalidateAll_WB_Crd
MOV pc, lr
Cache_RangeThreshold_WB_Crd
MOV a1, #0
LDR a1, =ZeroPage
LDR a1, [a1, #DCache_RangeThreshold]
MOV pc, lr
......@@ -1435,7 +1438,7 @@ IMB_Range_WB_Crd ROUT
ADD a2, a2, a1
BHS IMB_Full_WB_Crd
Push "lr"
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ;clean DCache entry
......@@ -1462,7 +1465,7 @@ MMU_ChangingEntry_WB_Crd ROUT
;
Push "a2, lr"
ADD a2, a1, #PageSize
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ;clean DCache entry
......@@ -1483,13 +1486,12 @@ MMU_ChangingEntries_WB_Crd ROUT
;
Push "a2, a3, lr"
MOV a2, a2, LSL #Log2PageSize
MOV a3, #0
LDR a3, [a3, #DCache_RangeThreshold] ;check whether cheaper to do global clean
LDR lr, =ZeroPage
LDR a3, [lr, #DCache_RangeThreshold] ;check whether cheaper to do global clean
CMP a2, a3
BHS %FT30
ADD a2, a2, a1 ;clean end address (exclusive)
MOV a3, #0
LDRB a3, [a3, #DCache_LineLen]
LDRB a3, [lr, #DCache_LineLen]
MOV lr, a1
10
MCR p15, 0, a1, c7, c10, 1 ;clean DCache entry
......@@ -1603,9 +1605,9 @@ Cache_CleanAll_WB_Cal_LD ROUT
; - see remarks at top of XScale ops for discussion of strategy
;
Push "a2-a4, v1, v2, lr"
MOV lr, #0
LDR lr, =ZeroPage
LDR a1, [lr, #DCache_CleanBaseAddress]
LDR a2, =DCache_CleanNextAddress
LDR a2, =ZeroPage+DCache_CleanNextAddress
LDR a3, [lr, #DCache_Size]
LDRB a4, [lr, #DCache_LineLen]
MOV v2, #0
......@@ -1634,9 +1636,9 @@ Cache_MiniInvalidateAll_WB_Cal_LD ROUT
; 'cleans' to achieve invalidate as side effect (mini cache will be configured writethrough)
;
Push "a2-a4, v1, v2, lr"
MOV lr, #0
LDR lr, =ZeroPage
LDR a1, [lr, #MCache_CleanBaseAddress]
LDR a2, =MCache_CleanNextAddr
LDR a2, =ZeroPage+MCache_CleanNextAddr
LDR a3, [lr, #MCache_Size]
LDRB a4, [lr, #MCache_LineLen]
MOV v2, #0
......@@ -1684,7 +1686,7 @@ Cache_InvalidateAll_WB_Cal_LD ROUT
Cache_RangeThreshold_WB_Cal_LD ROUT
MOV a1, #0
LDR a1, =ZeroPage
LDR a1, [a1, #DCache_RangeThreshold]
MOV pc, lr
......@@ -1723,7 +1725,7 @@ IMB_Range_WB_Cal_LD ROUT
ADD a2, a2, a1
BHS IMB_Full_WB_Cal_LD
Push "lr"
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ; clean DCache entry
......@@ -1759,7 +1761,7 @@ MMU_ChangingEntry_WB_Cal_LD ROUT
;
Push "a2, lr"
ADD a2, a1, #PageSize
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ; clean DCache entry
......@@ -1789,13 +1791,12 @@ MMU_ChangingEntries_WB_Cal_LD ROUT
;
Push "a2, a3, lr"
MOV a2, a2, LSL #Log2PageSize
MOV a3, #0
LDR a3, [a3, #DCache_RangeThreshold] ;check whether cheaper to do global clean
LDR lr, =ZeroPage
LDR a3, [lr, #DCache_RangeThreshold] ;check whether cheaper to do global clean
CMP a2, a3
BHS %FT30
ADD a2, a2, a1 ;clean end address (exclusive)
MOV a3, #0
LDRB a3, [a3, #DCache_LineLen]
LDRB a3, [lr, #DCache_LineLen]
MOV lr, a1
10
MCR p15, 0, a1, c7, c10, 1 ; clean DCache entry
......@@ -1866,7 +1867,7 @@ MMU_ChangingUncachedEntries_WB_Cal_LD ROUT
Cache_CleanAll_WB_CR7_Lx ROUT
; Clean cache by traversing all sets and ways for all data caches
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
MOV lr, #ZeroPage
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
BIC a1, a1, #&FF000000 ; Discard unification/coherency bits
......@@ -1911,7 +1912,7 @@ Cache_CleanInvalidateAll_WB_CR7_Lx ROUT
; similar to Cache_CleanAll, but does clean&invalidate of Dcache, and invalidates ICache
;
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
MOV lr, #ZeroPage
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
BIC a1, a1, #&FF000000 ; Discard unification/coherency bits
......@@ -1961,7 +1962,7 @@ Cache_InvalidateAll_WB_CR7_Lx ROUT
; no clean, assume caller knows what's happening
;
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
MOV lr, #ZeroPage
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
BIC a1, a1, #&FF000000 ; Discard unification/coherency bits
......@@ -2007,7 +2008,7 @@ Cache_InvalidateAll_WB_CR7_Lx ROUT
Cache_RangeThreshold_WB_CR7_Lx ROUT
MOV a1, #0
LDR a1, =ZeroPage
LDR a1, [a1, #DCache_RangeThreshold]
MOV pc, lr
......@@ -2056,7 +2057,7 @@ IMB_Full_WB_CR7_Lx ROUT
; Luckily, we only need to clean as far as the level of unification
;
Push "a2,a3,a4,v1,v2,v3,v4,v5,lr"
MOV lr, #ZeroPage
LDR lr, =ZeroPage
LDR a1, [lr, #Cache_Lx_Info]!
ADD lr, lr, #Cache_Lx_DTable-Cache_Lx_Info
MOV a1, a1, LSR #27
......@@ -2111,7 +2112,7 @@ IMB_Range_WB_CR7_Lx ROUT
CMPLO a1, a2 ; The routine below will fail if the end address wraps around, so just IMB_Full instead
BHS IMB_Full_WB_CR7_Lx
Push "a1,a3,lr"
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen] ; log2(line len)-2
MOV a3, #4
MOV lr, a3, LSL lr
......@@ -2122,7 +2123,7 @@ IMB_Range_WB_CR7_Lx ROUT
BLO %BT10
myDSB ,a1 ; Wait for clean to complete
Pull "a1" ; Get start address back
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #ICache_LineLen] ; Use ICache line length, just in case D&I length differ
MOV lr, a3, LSL lr
10
......@@ -2150,9 +2151,9 @@ MMU_Changing_WB_CR7_Lx ROUT
;
MMU_ChangingEntry_WB_CR7_Lx ROUT
Push "a2, lr"
MOV lr, #0
myDSB ,lr,,y ; Ensure the page table write has actually completed
myDSB ,lr ; Ensure the page table write has actually completed
myISB ,lr,,y ; Also required
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen] ; log2(line len)-2
MOV a2, #4
MOV lr, a2, LSL lr
......@@ -2162,8 +2163,8 @@ MMU_ChangingEntry_WB_CR7_Lx ROUT
ADD a1, a1, lr
CMP a1, a2
BNE %BT10
MOV lr, #0
myDSB ,lr,,y ; Wait for clean to complete
myDSB ,lr ; Wait for clean to complete
LDR lr, =ZeroPage
LDRB lr, [lr, #ICache_LineLen] ; Use ICache line length, just in case D&I length differ
MOV a1, #4
MOV lr, a1, LSL lr
......@@ -2188,13 +2189,12 @@ MMU_ChangingEntries_WB_CR7_Lx ROUT
myDSB ,lr ; Ensure the page table write has actually completed
myISB ,lr,,y ; Also required
MOV a2, a2, LSL #Log2PageSize
MOV a3, #0
LDR a3, [a3, #DCache_RangeThreshold] ;check whether cheaper to do global clean
LDR lr, =ZeroPage
LDR a3, [lr, #DCache_RangeThreshold] ;check whether cheaper to do global clean
CMP a2, a3
BHS %FT30
ADD a2, a2, a1 ;clean end address (exclusive)
MOV a3, #0
LDRB a3, [a3, #DCache_LineLen] ; log2(line len)-2
LDRB a3, [lr, #DCache_LineLen] ; log2(line len)-2
MOV lr, #4
MOV a3, lr, LSL a3
MOV lr, a1
......@@ -2203,8 +2203,8 @@ MMU_ChangingEntries_WB_CR7_Lx ROUT
ADD a1, a1, a3
CMP a1, a2
BNE %BT10
MOV a3, #0
myDSB ,a3,,y ; Wait for clean to complete
myDSB ,a3 ; Wait for clean to complete
LDR a3, =ZeroPage
LDRB a3, [a3, #ICache_LineLen] ; Use ICache line length, just in case D&I length differ
MOV a1, #4
MOV a3, a1, LSL a3
......@@ -2261,7 +2261,7 @@ MMU_ChangingUncachedEntries_WB_CR7_Lx ROUT
; IMPORT Write0_Translated
ARM_PrintProcessorType
MOV a1, #ZeroPage
LDR a1, =ZeroPage
LDRB a1, [a1, #ProcessorType]
TEQ a1, #ARMunk
MOVEQ pc, lr
......
s/Arthur2
View file @ 2247d8e9
......@@ -124,7 +124,7 @@ InitVariables ROUT
; Blank the sysvar list
MOV R0, #0
LDR R12, =VariableList
LDR R12, =ZeroPage+VariableList
STR R0, [R12]
; Set up the preset system variables
......@@ -374,14 +374,14 @@ ReadTimeFormattedAtR1
B %BT01
ReadRC ROUT
MOV R0, #0
LDR R0, =ZeroPage
LDR R0, [R0, #ReturnCode]
B ReadNumSysVar
SetRC Push "lr"
BL SetNumSysVar
LDR R4, =ReturnCode
LDR R4, =ZeroPage+ReturnCode
STR R2, [R4]
LDR R4, =RCLimit
LDR R4, =ZeroPage+RCLimit
LDR R4, [R4]
CMP R2, R4
BHI %FT03
......@@ -405,7 +405,7 @@ SetDateSuffixFormat
MakeErrorBlock RCExc
MakeErrorBlock RCNegative
ReadRCL MOV R0, #0
ReadRCL LDR R0, =ZeroPage
LDR R0, [R0, #RCLimit]
ReadNumSysVar
Push "lr"
......@@ -422,7 +422,7 @@ ReadNumSysVar
Pull "PC"
SetRCL Push "lr"
BL SetNumSysVar
LDR R4, =RCLimit
LDR R4, =ZeroPage+RCLimit
CMP R2, #0 ; can't set -ve RCLimit
RSBMIS R2, R2, #0
MOVMI R2, #0 ; BIC of MININT
......@@ -1634,7 +1634,7 @@ SetVarVal_NewNodeReady
ADD sp, sp, #12
Pull "r0,r1,r2"
]
LDR r11, =VariableList
LDR r11, =ZeroPage+VariableList
LDR r10, [r11]
[ SysVars_QuickContext
TEQ r10,#0
......@@ -1774,7 +1774,7 @@ SetVarVal_DeleteIt
TEQ r10, #VarType_Code
BNE SetVarVal_TestVExit
80
LDR r11, =VariableList
LDR r11, =ZeroPage+VariableList
LDR r10, [r11]
[ SysVars_QuickContext
ADD r10,r10,#SysVars_VTableOffset
......@@ -1872,7 +1872,7 @@ VarFindIt Entry "r0,r1,r2,r5,r6,r7,r8,r9,r10,r11"
BL SysVar_Write0
]
LDR r9, =VariableList
LDR r9, =ZeroPage+VariableList
LDR r9, [r9]
TEQ r9, #0
[ SysVars_QuickContext
......@@ -2111,7 +2111,7 @@ WildMatch ROUT
VarFindIt_QA ROUT
Push "r0,r1,r2,r3,r4,r8,r9,r10,r11,LR"
MOV r0, r3
LDR r9, =VariableList
LDR r9, =ZeroPage+VariableList
LDR r9, [r9]
TEQ r9,#0
BEQ %FT99 ;exit with EQ (not found)
......@@ -2201,7 +2201,7 @@ SysVars_ClaimVNode ROUT
BHI %FT80 ;too big for sticky node
ADD r3,r3,#SysVars_StickyNode_UnitSize-1
BIC r3,r3,#SysVars_StickyNode_UnitSize-1 ;round up to unit size
MOV r1,#SysVars_StickyPointers
LDR r1,=ZeroPage+SysVars_StickyPointers
LDR r2,[r1,r3,LSR #(SysVars_StickyNode_Log2US-2)] ;sticky pointer for this size
CMP r2,#0 ;also clears V
BEQ %FT80
......@@ -2209,7 +2209,7 @@ SysVars_ClaimVNode ROUT
STR LR,[r1,r3,LSR #(SysVars_StickyNode_Log2US-2)] ;used it
[ mjsSysHeapNodesTrace
Push "r0-r2"
MOV r0,#0
LDR r0,=ZeroPage
LDR r1,[r0,#mjsSHNT_vcs_total]
ADD r1,r1,#1
STR r1,[r0,#mjsSHNT_vcs_total]
......@@ -2220,7 +2220,7 @@ SysVars_ClaimVNode ROUT
STRVS r0,[SP]
[ mjsSysHeapNodesTrace
Push "r0-r2"
MOV r0,#0
LDR r0,=ZeroPage
LDR r1,[r0,#mjsSHNT_vch_total]
ADD r1,r1,#1
STR r1,[r0,#mjsSHNT_vch_total]
......@@ -2247,14 +2247,14 @@ SysVars_FreeVNode
BHI %FT80
TST r1,#SysVars_StickyNode_UnitSize-1 ;is it a multiple of unit size
BNE %FT80
MOV r3,#SysVars_StickyPointers
LDR r3,=ZeroPage+SysVars_StickyPointers
LDR LR,[r3,r1,LSR #(SysVars_StickyNode_Log2US-2)] ;sticky pointer for this size
CMP LR,#0
STREQ r2,[r3,r1,LSR #(SysVars_StickyNode_Log2US-2)] ;stick!
80
[ mjsSysHeapNodesTrace
Push "r0-r2"
MOV r0,#0
LDR r0,=ZeroPage
LDREQ r1,[r0,#mjsSHNT_vfs_total]
LDRNE r1,[r0,#mjsSHNT_vfh_total]
ADD r1,r1,#1
......@@ -2294,7 +2294,7 @@ SysVars_ExpandOrShrinkVNode
BIC r4,r4,#SysVars_StickyNode_UnitSize-1 ;round up to unit size
CMP r4,r6 ;same as current size?
BEQ %FT55
MOV r1,#SysVars_StickyPointers
LDR r1,=ZeroPage+SysVars_StickyPointers
LDR LR,[r1,r4,LSR #(SysVars_StickyNode_Log2US-2)] ;sticky pointer for this size
CMP LR,#0
BEQ %FT40
......@@ -2326,7 +2326,7 @@ SysVars_ExpandOrShrinkVNode
55
[ mjsSysHeapNodesTrace
Push "r0-r2"
MOV r0,#0
LDR r0,=ZeroPage
LDR r1,[r0,#mjsSHNT_vxs_total]
ADD r1,r1,#1
STR r1,[r0,#mjsSHNT_vxs_total]
......@@ -2337,7 +2337,7 @@ SysVars_ExpandOrShrinkVNode
90
[ mjsSysHeapNodesTrace
Push "r0-r2"
MOV r0,#0
LDR r0,=ZeroPage
LDR r1,[r0,#mjsSHNT_vxh_total]
ADD r1,r1,#1
STR r1,[r0,#mjsSHNT_vxh_total]
......
s/Arthur3
View file @ 2247d8e9
......@@ -1409,7 +1409,7 @@ ConParmTooBigError
= "ConParmTooBig:Configure parameter too big", 0
ALIGN
01
MOV r12, #Module_List
LDR r12, =ZeroPage+Module_List
conoptloop
LDR r12, [r12]
CMP r12, #0
......@@ -1542,7 +1542,7 @@ ReadSizeParm ROUT
ADRL r14, FontSizeFrig-4 ; point at info word for fontsize
TEQ r8, r14 ; if fontsize
MOVEQ r8, #4*1024 ; then use 4K (lucky it's a pagesize!)
MOVNE r8, #0 ; else use pagesize units
LDRNE r8, =ZeroPage ; else use pagesize units
LDRNE r8, [r8, #Page_Size]
ADRL r14, PageShifts-1
LDRB r14, [r14, r8, LSR #12]
......@@ -1576,7 +1576,7 @@ Status_Code ROUT
Pull "pc"
01
MOV r6, #Module_List
LDR r6, =ZeroPage+Module_List
statoptloop
LDR r6, [r6]
CMP r6, #0
......@@ -1663,7 +1663,7 @@ ListAll ROUT
10
ADRL r0, dotstring ; match all
Push "r3, r7"
MOV r7, #Module_List
LDR r7, =ZeroPage+Module_List
listallmloop
LDR r7, [r7]
CMP r7, #0
......@@ -1890,7 +1890,7 @@ ExitShow
Push "r8, r9"
ADRL r8, FontSizeFrig
CMP r4, r8
MOVNE r8, #0
LDRNE r8, =ZeroPage
LDRNE r8, [r8, #Page_Size]
MOVEQ r8, #4*1024
ADRL r9, PageShifts-1
......@@ -2388,7 +2388,7 @@ Config_MonitorType_setcode
BL ConfigCheckEOL
BVS ExitConfig
LDR r0, =VduDriverWorkSpace+CurrentMonitorType
LDR r0, =ZeroPage+VduDriverWorkSpace+CurrentMonitorType
STR r4, [r0] ; update current value
MOV r0, r1
......@@ -2459,7 +2459,7 @@ Read_Configd_Sync Entry
SetUpPrinterBuffer Entry "r1-r3"
MOV r0, #PrinterBufferCMOS
BL Read
MOV r2, #0
LDR r2, =ZeroPage
LDR r2, [r2, #Page_Size]
MULS r3, r2, r0
BEQ %FT10 ; if zero, then use default area & size
......@@ -2470,7 +2470,7 @@ SetUpPrinterBuffer Entry "r1-r3"
LDR r2, =PrintBuff ; use default buffer
MOV r3, #PrintBuffSize
20
MOV r0, #0
LDR r0, =ZeroPage
STR r2, [r0, #PrinterBufferAddr]
STR r3, [r0, #PrinterBufferSize]
EXIT
......
s/ArthurSWIs
View file @ 2247d8e9
......@@ -314,7 +314,7 @@ InitVectors
MOV R0, #NVECTORS
ADR R1, defaultvectab ; Point at the default vector table
LDR R2, =VecPtrTab ; Point at table of head pointers
LDR R2, =ZeroPage+VecPtrTab ; Point at table of head pointers
VecInitLoop
STR R1, [R2], #4
......@@ -355,7 +355,7 @@ CallVector ROUT
TEQP lr, #0 ; put back caller's flags + int state
]
LDR r14, =VecPtrTab ; Point at table of head pointers
LDR r14, =ZeroPage+VecPtrTab ; Point at table of head pointers
LDR r10, [r14, r10, LSL #2] ; nextblock:=vecptrtab!(n*4)
CallVecLoop
......@@ -407,7 +407,7 @@ ClaimVector_SWICode ROUT
PHPSEI R4, R14 ; Disable IRQs
MOV R3, #0 ; List of de-linked nodes is empty
LDR R11, =VecPtrTab ; Get ptr to table of head pointers
LDR R11, =ZeroPage+VecPtrTab ; Get ptr to table of head pointers
LDR R10, [R11, R0, LSL #2]! ; R10 "nextblock" := *oldptr, R11= root ptr
01 BL FindAndDelinkNode ; R10,R11->R10,R11,R12
STRVC R3, [R12, #TailPtr] ; Attach de-linked nodes onto this node
......@@ -424,7 +424,7 @@ ClaimVector_SWICode ROUT
BNE %BT02 ; Yes then jump
GoForAddToVec
LDR R11, =VecPtrTab ; Point at table of head pointers
LDR R11, =ZeroPage+VecPtrTab ; Point at table of head pointers
ADD R11, R11, R0, LSL #2
MOV R10, R1 ; Address
......@@ -432,7 +432,7 @@ GoForAddToVec
[ ChocolateSysHeap
ASSERT ChocolateSVBlocks = ChocolateBlockArrays + 4
MOV r3,#ChocolateBlockArrays
LDR r3,=ZeroPage+ChocolateBlockArrays
LDR r3,[r3,#4]
BL ClaimChocolateBlock
MOVVS R3, #VecNodeSize ; Ask for this number of bytes
......@@ -478,7 +478,7 @@ ReleaseVector_SWICode
PHPSEI R9, R14 ; Disable IRQs
LDR R11, =VecPtrTab ; Get ptr to table of head pointers
LDR R11, =ZeroPage+VecPtrTab ; Get ptr to table of head pointers
LDR R10, [R11, R0, LSL #2]! ; R10 "nextblock" := *oldptr, R11= root ptr
BL FindAndDelinkNode ; R10,R11->R10,R11,R12
PLP R9 ; Restore IRQ state
......@@ -541,7 +541,7 @@ FreeNode
MOV R2, R12
[ ChocolateSysHeap
ASSERT ChocolateSVBlocks = ChocolateBlockArrays + 4
MOV r1,#ChocolateBlockArrays
LDR r1,=ZeroPage+ChocolateBlockArrays
LDR r1,[r1,#4]
BL FreeChocolateBlock
BLVS FreeSysHeapNode
......@@ -588,23 +588,23 @@ defaultvectab
& 0, 0, NaffVector ; UserV * &00
& 0, 0, ErrHandler ; ErrorV * &01
& 0, 0, NOIRQ ; IrqV * &02
& 0, OsbyteVars, PMFWrch ; WrchV * &03
& 0, ZeroPage+OsbyteVars, PMFWrch ; WrchV * &03
& 0, 0, NewRdch ; RdchV * &04 - start of VecNo=SWINo section
& 0, 0, VecOsCli
& 0, OsbyteVars, OsByte
& 0, OsbyteVars, OsWord
& 0, ZeroPage+OsbyteVars, OsByte
& 0, ZeroPage+OsbyteVars, OsWord
& 0, 0, NaffVector ; filev
& 0, 0, NaffVector ; argsv
& 0, 0, NaffVector ; bgetv
& 0, 0, NaffVector ; bputv
& 0, 0, NaffVector ; gbpbv
& 0, 0, NaffVector ; findv
& 0, OsbyteVars, VecRdLine ; ReadlineV * &0E - end of VecNo=SWINo
& 0, ZeroPage+OsbyteVars, VecRdLine ; ReadlineV * &0E - end of VecNo=SWINo
& 0, 0, NaffVector ; fscv
& 0, EvtHan_ws, DefEvent ; EventV * &10
& 0, ZeroPage+EvtHan_ws, DefEvent ; EventV * &10
& 0, 0, NaffVector ; UPTV * &11
& 0, 0, NaffVector ; NETV * &12
......@@ -621,7 +621,7 @@ defaultvectab
& 0, 0, NaffVector ; UKVDU23V * &17 ; ---| VDU23 (decimal)
& 0, HiServ_ws, HighSWI ; UKSWIV * &18 ; ---| Unknown SWI numbers
& 0, ZeroPage+HiServ_ws, HighSWI ; UKSWIV * &18 ; ---| Unknown SWI numbers
& 0, 0, NaffVector ; UKPLOTV * &19 ; ---| VDU25 (decimal)
......@@ -630,15 +630,15 @@ defaultvectab
& 0, 0, NaffVector ; VDUXV * &1B
& 0, 0, Def_100HZ ; TickerV * &1C
& 0, UpCallHan_ws, CallUpcallHandler
& 0, ZeroPage+UpCallHan_ws, CallUpcallHandler
; UpCallV * &1D
& 0, 0, AdjustOurSet ; ChangeEnvironment * &1E
& 0, VduDriverWorkSpace, SpriteVecHandler ; SpriteV * &1F
& 0, ZeroPage+VduDriverWorkSpace, SpriteVecHandler ; SpriteV * &1F
& 0, 0, NaffVector ; DrawV * &20
& 0, 0, NaffVector ; EconetV * &21
& 0, 0, NaffVector ; ColourV * &22
& 0, VduDriverWorkSpace, MOSPaletteV ; PaletteV * &23
& 0, ZeroPage+VduDriverWorkSpace, MOSPaletteV ; PaletteV * &23
& 0, 0, NaffVector ; SerialV * &24
& 0, 0, NaffVector ; FontV * &25
......@@ -652,7 +652,7 @@ defaultvectab
& 0, 0, NaffVector ; LowPriorityEventV &28
& 0, 0, NaffVector ; &29
[ UseGraphicsV
& 0, 0, MOSGraphicsV ; GraphicsV * &2a
& 0, ZeroPage, MOSGraphicsV ; GraphicsV * &2a
|
& 0, 0, NaffVector ; GraphicsV * &2a
]
......@@ -688,11 +688,17 @@ Application_Delink ROUT
CMP R1, #4
BLT %FT99 ; invalid buffer size
[ ZeroPage = 0
MOV R3, #NVECTORS-1
LDR R4, [R3, #AplWorkSize-(NVECTORS-1)]
|
LDR R4, =ZeroPage
MOV R3, #NVECTORS-1
LDR R4, [R4, #AplWorkSize]
]
SETPSR I_bit, R2 ; IRQs off while holding context.
03 LDR R11, =VecPtrTab ; Point at table of head pointers
03 LDR R11, =ZeroPage+VecPtrTab ; Point at table of head pointers
ADD R10, R11, R3, LSL #2
04 MOV R11, R10 ; step chain
LDR R10, [R11]
......@@ -727,7 +733,7 @@ Application_Delink ROUT
MOV R10, R12 ; keep updated thisblk
[ ChocolateSysHeap
ASSERT ChocolateSVBlocks = ChocolateBlockArrays + 4
MOV r1,#ChocolateBlockArrays
LDR r1,=ZeroPage+ChocolateBlockArrays
LDR r1,[r1,#4]
BL FreeChocolateBlock
BLVS FreeSysHeapNode
......@@ -841,7 +847,7 @@ Issue_Service ROUT ; R1 is service number, R2 may be a parameter
CMP R1,#ServMinUsrNumber
BHS %FT84
;call anyone on the appropriate Sys chain
MOV R10,#0
LDR R10,=ZeroPage
LDR R10,[R10,#Serv_SysChains]
CMP R10,#0
BEQ %FT88
......@@ -875,7 +881,7 @@ Issue_Service ROUT ; R1 is service number, R2 may be a parameter
;
;call anyone on the appropriate Usr chain
84
LDR R10,=Serv_UsrChains
LDR R10,=ZeroPage+Serv_UsrChains
LDR R10,[R10]
CMP R10,#0
BEQ %FT88
......@@ -898,7 +904,7 @@ Issue_Service ROUT ; R1 is service number, R2 may be a parameter
;
;call everyone on the chain of Awkward modules, always passing service number in R1
88
MOV R10,#0
LDR R10,=ZeroPage
LDR R11,[R10,#Serv_AwkwardChain]
CMP R11,#0
BEQ %FT01
......@@ -919,7 +925,7 @@ Issue_Service ROUT ; R1 is service number, R2 may be a parameter
| ;IF/ELSE ChocolateService
05 MOV R10, #Module_List
05 LDR R10, =ZeroPage+Module_List
03 LDR R10, [R10, #Module_chain_Link]
CMP R10, #0
BEQ %FT01
......@@ -984,24 +990,34 @@ Issue_Service ROUT ; R1 is service number, R2 may be a parameter
]
assert (Service_ReleaseFIQ :AND: &FF) <> 0
[ HAL
[ ZeroPage = 0
LDRB R9, [R1, #MOShasFIQ-Service_ReleaseFIQ]
STRB R1, [R1, #MOShasFIQ-Service_ReleaseFIQ]
|
LDR R1, =ZeroPage+MOShasFIQ
ASSERT ((ZeroPage+MOShasFIQ) :AND: 255) <> 0
LDRB R9, [R1]
STRB R1, [R1]
]
TEQ R9, #0
BNE %FT06
ADR R1, FIQKiller
MOV R10, #FIQKiller_ws - FIQKiller
MOV R11, #&1C
LDR R11, =ZeroPage+&1C
04 LDR LR, [R1], #4
SUBS R10, R10, #4
STR LR, [R11], #4
BNE %BT04
[ ZeroPage <> 0
LDR R10, =ZeroPage
]
AddressHAL R10
LDR R14, [R9, #-(EntryNo_HAL_FIQDisableAll+1)*4]
STMIA R11, {R9, R14}
Push "R0"
MOV R0, #0 ; in case 32-byte cache lines
MOV R1, #&100
LDR R0, =ZeroPage
ADD R1, R0, #&100
ARMop IMB_Range,,,R0
Pull "R0"
]
......@@ -1011,7 +1027,7 @@ Issue_Service ROUT ; R1 is service number, R2 may be a parameter
Pull "R9-R12, PC"
FIQclaim
MOV R10, #0
LDR R10, =ZeroPage
[ FIQDebug
TubeChar r0, r1, "MOV r1, #""C"""
......@@ -1044,7 +1060,7 @@ FIQclaim
CMP r9, #0
sam001
]
ASSERT (ZeroPage :AND: 255) = 0
STRNEB R10, [R10, #MOShasFIQ]
MOVNE r1, #Service_Serviced
fakeservicecall
......@@ -1053,7 +1069,7 @@ fakeservicecall
STREQ PC,[stack,#16]
BEQ %BT05
MOV r0, r0
MOV r10, #0
LDR r10, =ZeroPage
LDRB r9, [r10, #FIQclaim_interlock]
STRB r10, [r10, #FIQclaim_interlock]
......@@ -1086,7 +1102,7 @@ test_FIQclaim_in_progress
TubeChar r0, r1, "MOV r1, #""R"""
]
MOV r10, #0
LDR r10, =ZeroPage
LDRB r9, [r10, #FIQclaim_interlock]
CMP r9, #0
......@@ -1109,7 +1125,12 @@ test_FIQclaim_in_progress
; r9-r12, lr corruptible
checkmoshandlers
[ ZeroPage = 0
LDR r9, [r1, #SExitA-Service_NewApplication]
|
LDR r9, =ZeroPage
LDR r9, [r9, #SExitA]
]
ADRL r10, CLIEXIT
CMP r9, r10
BNE %BT05
......@@ -1147,7 +1168,7 @@ display_post_postinit_calls
[ HAL
FIQKiller
SUB R14, R14, #4
MOV R13, #&100
ADR R13, FIQKiller-&1C+&100
ADR R10, FIQKiller_ws
STMFD R13!, {R0-R3,R14}
MOV R14, PC
......@@ -1261,9 +1282,13 @@ ValidateAddress_Code ROUT
Push "R1, lr"
CMP R0, R1
SUBNE R1, R1, #1 ; cope with zero length range sensibly
MOV R10, #0
LDR R10, =ZeroPage
[ ZeroPage = 0
MOV R11, #0
|
MOV R11, #ScratchSpace
]
LDR R12, [R10, #AplWorkSize]
BL RangeCheck
......@@ -1298,8 +1323,18 @@ ValidateAddress_Code ROUT
ADD R12, R11, R12, LSL #1 ; doubly-mapped friggage
BL RangeCheck
[ ZeroPage <> 0
MOV r11, r10
ADD r12, r11, #16*1024
BL RangeCheck
LDR r11, =DebuggerSpace
ADD r12, r11, #DebuggerSpace_Size
BL RangeCheck
]
; not in one of those ranges, so check against dynamic area list
MOV r10, #DAList
LDR r10, =ZeroPage+DAList
10
LDR r10, [r10, #DANode_Link]
TEQ r10, #0 ; end of list
......
s/ChangeDyn
View file @ 2247d8e9
This diff is collapsed.
s/ExtraSWIs
View file @ 2247d8e9
......@@ -49,7 +49,7 @@ ClaimProcVecSWI ROUT
BCS %FT30
MOV r4, r1 ; r4 = replacement value
LDR r5, =ProcVec_Start
LDR r5, =ZeroPage+ProcVec_Start
PHPSEI ; Disable IRQs while we mess around with vectors.
TST r0, #1:SHL:8
......
s/HAL
View file @ 2247d8e9
......@@ -520,12 +520,12 @@ RISCOS_Start
; Map in page zero
ADD a1, v3, #DRAMOffset_PageZero - DRAMOffset_L1PT
MOV a2, #0
[ ECC
LDR a2, =ZeroPage
[ ECC
LDR a3, =(AP_Read * L2X_APMult) + L2_C + L2_B + 1:SHL:31
|
|
LDR a3, =(AP_Read * L2X_APMult) + L2_C + L2_B
]
]
MOV a4, #16*1024
BL Init_MapIn
......@@ -710,6 +710,9 @@ MMU_activation_zone
[ NoUnaligned
ORR v5, v5, #MMUC_A ; Alignment exceptions on
]
[ HiProcVecs
ORR v5, v5, #MMUC_V ; High processor vectors enabled
]
MMUon_instr
ARM_write_control v5
[ MEMM_Type = "VMSAv6"
......@@ -835,13 +838,15 @@ MMUon_nol1ptoverlap
MOV a1, #L1_Fault
BL RISCOS_ReleasePhysicalAddress
ASSERT ZeroPage = 0
LDR a1, =HALWorkspace
MOV a2, #0
LDR a2, =ZeroPage
LDR a3, [a2, #HAL_WsSize]
[ ZeroPage <> 0
MOV a2, #0
]
BL memset
MOV a2, #ZeroPage
LDR a2, =ZeroPage
LDR a1, =IOLimit
STR a1, [a2, #IOAllocLimit]
LDR a1, =IO
......@@ -852,7 +857,7 @@ MMUon_nol1ptoverlap
; Initialise the HAL. Due to its memory claiming we need to get our v1 and v2 values
; into workspace and out again around it.
MOV a1, #ZeroPage
LDR a1, =ZeroPage
STR v1, [a1, #InitUsedBlock]
STR v2, [a1, #InitUsedEnd]
......@@ -867,7 +872,7 @@ MMUon_nol1ptoverlap
ALIGN
]
MOV a1, #ZeroPage
LDR a1, =ZeroPage
LDR v1, [a1, #InitUsedBlock]
LDR v2, [a1, #InitUsedEnd]
......@@ -883,7 +888,7 @@ MMUon_nol1ptoverlap
MOV a1, #0
CallHAL HAL_TimerSetPeriod
MOV a1, #InitIRQWs
LDR a1, =ZeroPage+InitIRQWs
MOV a2, #1
STRB a2, [a1, #KbdScanActive]
......@@ -897,8 +902,7 @@ MMUon_nol1ptoverlap
LDR v5, [v8, #RAMLIMIT]
LDR v7, [v8, #MaxCamEntry]
MOV a1, #0
LDR a1, [a1, #HAL_StartFlags]
LDR a1, [v8, #HAL_StartFlags]
TST a1, #OSStartFlag_RAMCleared
; Clear the memory.
BLEQ ClearPhysRAM
......@@ -909,11 +913,10 @@ MMUon_nol1ptoverlap
STR v7, [v8, #MaxCamEntry]
; Set v4 to XCB bits for default cacheable+bufferable
MOV v5, #0
LDR v4, [v5, #MMU_PCBTrans]
LDR v4, [v8, #MMU_PCBTrans]
LDRB v4, [v4, #0]
; Set v5 to XCB bits for default bufferable
LDR v5, [v5, #MMU_PCBTrans]
LDR v5, [v8, #MMU_PCBTrans]
LDRB v5, [v5, #XCB_NC]
; Set up the data cache cleaner space if necessary (eg. for StrongARM core)
......@@ -993,6 +996,14 @@ MMUon_nol1ptoverlap
BL Init_MapInRAM
]
[ HiProcVecs
; Map in DebuggerSpace
LDR a1, =DebuggerSpace
ORR a2, v5, #AP_Read * L2X_APMult
LDR a3, =(DebuggerSpace_Size + &FFF) :AND: &FFFFF000
BL Init_MapInRAM
]
[ MinorL2PThack
; Allocate backing L2PT for the free pool
MOV a1, #FreePoolAddress
......@@ -1126,10 +1137,12 @@ HAL_InvalidateCache_ARMvF
] ; MEMM_Type = "VMSAv6"
CountPageTablePages ROUT
MOV a1, #ZeroPage
LDR a1, =ZeroPage
LDR a2, =CAM
LDR a3, [a1, #MaxCamEntry]
[ ZeroPage <> 0
MOV a1, #0
]
ADD a3, a3, #1
ADD a4, a2, a3, LSL #3
10 LDR ip, [a4, #-8]!
......@@ -1139,7 +1152,7 @@ CountPageTablePages ROUT
ADDEQ a1, a1, #4096
TEQ a4, a2
BNE %BT10
MOV a2, #0
LDR a2, =ZeroPage
STR a1, [a2, #L2PTUsed]
MOV pc, lr
......@@ -1173,7 +1186,7 @@ PhysAddrToPageNo
ROUT
ConstructCAMfromPageTables
Push "v1-v8, lr"
MOV a1, #ZeroPage
LDR a1, =ZeroPage
LDR a2, [a1, #MaxCamEntry]
LDR ip, [a1, #MMU_PCBTrans]
LDR v1, =CAM ; v1 -> CAM (for whole routine)
......@@ -1207,13 +1220,13 @@ ConstructCAMfromPageTables
[ MEMM_Type <> "VMSAv6"
TEQ v6, #L2_SmallPage ; convert small pages to extended pages
BNE %FT50
MOV lr, #0 ; if we now know that CPU supports them
LDR a1, [lr, #ProcessorFlags]
LDR a2, =ZeroPage ; if we now know that CPU supports them
LDR a1, [a2, #ProcessorFlags]
TST a1, #CPUFlag_ExtendedPages
BEQ %FT50
ASSERT ZeroPage = 0
LDR a1, [lr, #MMU_PCBTrans] ; reprocess C and B bits as per XCB table
MOV lr, #0
TST v5, #L2_C ; (eg if C and B both set, replace with
ORREQ lr, lr, #DynAreaFlags_NotCacheable ; default cacheable+bufferable XCB)
TST v5, #L2_B
......@@ -1224,7 +1237,6 @@ ConstructCAMfromPageTables
BIC v5, v5, #2_000000001100 ; remove old C+B
BIC a1, v5, #2_000000110011 ; remove all other bits for just address
ORR v5, v5, lr ; put in new XCB
MOV a2, #ZeroPage
ARMop MMU_ChangingEntry,,,a2
STR v5, [v4, v2, LSR #10] ; update page table
]
......@@ -1523,7 +1535,7 @@ Init_MapInPage
BNE %FT50
TEQ v3, #0 ; if we've been given an extended page
BNE %FT45 ; must check that (a) the MMU is on
MOV lr, #0
LDR lr, =ZeroPage
LDR lr, [lr, #ProcessorFlags] ; and (b) the CPU supports them
TST lr, #CPUFlag_ExtendedPages
BNE %FT50
......@@ -1795,11 +1807,11 @@ ClearPhysRAM ROUT
]
;now let us do the clear
MOV r0,#ZeroPage+InitClearRamWs ;we can preserve r7-r9,r13 at logical address 52..67
LDR r0,=ZeroPage+InitClearRamWs ;we can preserve r7-r9,r13 at logical address 52..67
STMIA r0,{r4-r11,lr}
MOV r8, #0
LDR r8, =ZeroPage
MOV r9, #0
LDR r7, =PhysRamTable ; point to 5 lots of (physaddr,size)
LDR r7, =ZeroPage+PhysRamTable ; point to 5 lots of (physaddr,size)
ADR r6, RamSkipTable
ADD r4, r7, #PhysRamTableEnd-PhysRamTable ; r4 -> end of table
10
......@@ -1809,7 +1821,6 @@ ClearPhysRAM ROUT
TEQ r11, #0
BEQ %FT50
15
ASSERT ZeroPage=0
ADD r11, r10, r11 ; r11 = end address
; Need to check for RAM we've already used
......@@ -1887,18 +1898,18 @@ ClearPhysRAM ROUT
BNE %BT10
50 MOV r1, #0
MOV r0, #ZeroPage+InitClearRamWs
LDR r0, =ZeroPage+InitClearRamWs
LDMIA r0, {r4-r11,r14} ;restore
CPR_skipped
LDR r0, =OsbyteVars + :INDEX: LastBREAK
LDR r0, =ZeroPage+OsbyteVars + :INDEX: LastBREAK
MOV r1, #&80
STRB r1, [r0] ; flag the fact that RAM cleared
MSR CPSR_c, #F32_bit + UND32_mode ; retrieve the MMU control register
MOV r0, #ZeroPage ; soft copy
LDR r0, =ZeroPage ; soft copy
STR sp, [r0, #MMUControlSoftCopy]
MSR CPSR_c, #F32_bit + SVC32_mode
......@@ -2066,7 +2077,7 @@ RISCOS_MapInIO ROUT
; request not currently mapped, only partially mapped, or mapped with wrong flags
;
32
MOV ip, #ZeroPage
LDR ip, =ZeroPage
LDR v2, [ip, #IOAllocPtr]
ADD v1, v2, a2
SUB v1, v1, a3 ; attempt to allocate size of a3-a2
......@@ -2160,7 +2171,7 @@ HardwareSWI
HardwareCall
Push "v1-v4,sb,lr"
ADD v8, sb, #1 ; v8 = entry no + 1
MOV ip, #0
LDR ip, =ZeroPage
LDR v7, [ip, #HAL_Descriptor]
AddressHAL ip ; sb set up
LDR v7, [v7, #HALDesc_NumEntries] ; v7 = number of entries
......@@ -2178,7 +2189,7 @@ HardwareCall
HardwareLookup
ADD v8, sb, #1 ; v8 = entry no + 1
MOV ip, #0
LDR ip, =ZeroPage
LDR v7, [ip, #HAL_Descriptor]
AddressHAL ip
LDR v7, [v7, #HALDesc_NumEntries]
......@@ -2207,7 +2218,7 @@ HardwareDeviceAdd_Common
Entry
BL HardwareDeviceRemove_Common ; first try to remove any device already at the same address
EXIT VS
MOV lr, #0
LDR lr, =ZeroPage
LDR r1, [lr, #DeviceCount]
LDR r2, [lr, #DeviceTable]
TEQ r2, #0
......@@ -2216,7 +2227,7 @@ HardwareDeviceAdd_Common
LDR lr, [r2, #-4] ; word before heap block is length including length word
TEQ r1, lr, LSR #2 ; block already full?
BEQ %FT81
MOV lr, #0
LDR lr, =ZeroPage
10 STR r1, [lr, #DeviceCount]
ADD lr, r2, r1, LSL #2
SUB lr, lr, #4
......@@ -2239,7 +2250,7 @@ HardwareDeviceAdd_Common
ADDVS sp, sp, #4
EXIT VS
Pull "r0"
MOV lr, #0
LDR lr, =ZeroPage
MOV r1, #1
STR r2, [lr, #DeviceTable]
B %BT10
......@@ -2252,7 +2263,7 @@ HardwareDeviceAdd_Common
ADDVS sp, sp, #4
EXIT VS
Pull "r0"
MOV lr, #0
LDR lr, =ZeroPage
LDR r1, [lr, #DeviceCount]
STR r2, [lr, #DeviceTable]
ADD r1, r1, #1
......@@ -2260,7 +2271,7 @@ HardwareDeviceAdd_Common
HardwareDeviceRemove_Common
Entry "r4"
MOV lr, #0
LDR lr, =ZeroPage
LDR r3, [lr, #DeviceCount]
LDR r4, [lr, #DeviceTable]
TEQ r3, #0
......@@ -2283,7 +2294,7 @@ HardwareDeviceRemove_Common
STRCS r2, [r4, #-8]
SUBCSS r3, r3, #1
BCS %BT02
MOV lr, #0
LDR lr, =ZeroPage
LDR r3, [lr, #DeviceCount]
SUB r3, r3, #1
STR r3, [lr, #DeviceCount]
......@@ -2291,7 +2302,7 @@ HardwareDeviceRemove_Common
HardwareDeviceEnumerate
Push "r3-r4,lr"
MOV lr, #0
LDR lr, =ZeroPage
LDR r2, [lr, #DeviceCount]
LDR r3, [lr, #DeviceTable]
SUBS r4, r2, r1
......@@ -2349,11 +2360,11 @@ DebugTerminal_Rdch
CallHAL HAL_DebugRX
CMP a1, #27
BNE %FT25
LDR a2, =OsbyteVars + :INDEX: RS423mode
LDR a2, =ZeroPage + OsbyteVars + :INDEX: RS423mode
LDRB a2, [a2]
TEQ a2, #0 ; is RS423 raw data,or keyb emulator?
BNE %FT25
MOV a2, #0
LDR a2, =ZeroPage
LDRB a1, [a2, #ESC_Status]
ORR a1, a1, #&40
STRB a1, [a2, #ESC_Status] ; mark escape flag
......@@ -2363,7 +2374,7 @@ DebugTerminal_Rdch
25
CMP a1, #-1
Pull "a2-a4,sb,ip,pc",NE ; claim it
MOV R0, #0
LDR R0, =ZeroPage
LDRB R14, [R0, #CallBack_Flag]
TST R14, #CBack_VectorReq
BLNE process_callback_chain
......@@ -2405,9 +2416,12 @@ Reset_IRQ_Handler
ORR a3, a2, #SVC32_mode
MSR CPSR_c, a3
Push "a1-a2,lr"
MOV v2, #0
LDR v2, =ZeroPage
AddressHAL v2
MOV v1, #IICBus_Base
ADD v1, v2, #IICBus_Base
[ ZeroPage <> 0
MOV v2, #0
]
10
LDR a2, [v1, #IICBus_Type]
TST a2, #IICFlag_Background
......@@ -2417,7 +2431,7 @@ Reset_IRQ_Handler
ADD v1, v1, #IICBus_Size
CMP v2, #IICBus_Count
BNE %BT10
MOV a1, #InitIRQWs
LDR a1, =ZeroPage+InitIRQWs
LDRB a1, [a1, #KbdScanActive]
TEQ a1, #0
CallHAL HAL_KbdScanInterrupt,NE
......
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