ARMv8_nAArch32

# From DDI 0487A.g section J5
# Overlay this with ARMv7 encodings to fill the holes where ARMv8 additions are

# F6.1.54 Load-Aquire
# F6.1.210 Store-Release
# F6.1.56 Load-Aquire Exclusive
# F6.1.212 Store-Release Exclusive
# These alias into the LDREX/STREX family (see below)

# F6.1.50 Halting breakpoint
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,7)} {lnot(op)}	UNDEFINED

# F6.1.179 Send event local
(cond:4)001100100000(11110000)00000101	{ne(cond,15)}	UNALLOCATED_MEM_HINT

# F6.1.40 CRC
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,4)}	UNDEFINED

# Note that [LDR|STR]EX[B|H|D] appear here because previously
# bits 8-11 SBO, but that recommendation has changed because
# ARMv8 has added [LDA|STL]EX[B|H|D] in the same instruction space.

# A8.8.212 in DDI 0406C STREX
# A1 ARMv6*, ARMv7
(cond:4)00011000(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREX_A1

# A8.8.213 in DDI 0406C STREXB
# A1 ARMv6K, ARMv7
(cond:4)00011100(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXB_A1

# A8.8.214 in DDI 0406C STREXD
# A1 ARMv6K, ARMv7
(cond:4)00011010(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXD_A1

# A8.8.215 in DDI 0406C STREXH
# A1 ARMv6K, ARMv7
(cond:4)00011110(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXH_A1

# A8.8.75 in DDI 0406C LDREX
# A1 ARMv6*, ARMv7
(cond:4)00011001(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREX_A1

# A8.8.76 in DDI 0406C LDREXB
# A1 ARMv6K, ARMv7
(cond:4)00011101(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXB_A1

# A8.8.77 in DDI 0406C LDREXD
# A1 ARMv6K, ARMv7
(cond:4)00011011(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXD_A1

# A8.8.78 in DDI 0406C LDREXH
# A1 ARMv6K, ARMv7
(cond:4)00011111(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXH_A1