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Commit c7711b01 authored by Robert Sprowson's avatar Robert Sprowson
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Add decgen encodings describing ARMv8 AArch32 instructions 

These can be overlaid on top of the larger ARMv7 encodings to add the new ARMv8 opcodes, or to fault them as undefined by using the nARMv8 one.
Currently missing the new VFP and SIMD opcodes.

Version 1.88. Tagged as 'Library-1_88'
parent 5e4e8c00
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Showing with 146 additions and 35 deletions
Misc/decgen/encodings/ARMv7
View file @ c7711b01
......@@ -15,14 +15,12 @@
(cond:4)0001(op:4)(:12)1001(:4) {ne(cond,15)} {lt(op,8)} {band(op,3)} UNDEFINED
# A5.2.11
(cond:4)00110(op)10(op1:4)(:8)(op2:8) {ne(cond,15)} {lnot(op)} {lnot(op1)} {gt(op2,4)} {lt(op2,0xf0)} UNALLOCATED_HINT
(cond:4)00110(op)10(op1:4)(:8)(op2:8) {ne(cond,15)} {lnot(op)} {lnot(op1)} {gt(op2,5)} {lt(op2,0xf0)} UNALLOCATED_HINT
# A5.2.12
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,1)} {lnot(band(op,1))} UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(band(op2,6),2)} {ne(op,1)} UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,4)} UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,6)} {ne(op,3)} UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,7)} {lnot(op)} UNDEFINED
# A5.4
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4) {lt(cond,14)} {eq(op1,31)} {eq(op2,7)} PERMA_UNDEFINED
......@@ -328,20 +326,10 @@
(cond:4)000PU0W0(Rn:4)(Rt:4)(0000)1101(Rm:4) {ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))} LDRD_reg_A1 # Note manual disambiguation (see A5.2)
# A8.8.75 LDREX
# A1 ARMv6*, ARMv7
(cond:4)00011001(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREX_A1
# A8.8.76 LDREXB
# A1 ARMv6K, ARMv7
(cond:4)00011101(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREXB_A1
# A8.8.77 LDREXD
# A1 ARMv6K, ARMv7
(cond:4)00011011(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREXD_A1
# A8.8.78 LDREXH
# A1 ARMv6K, ARMv7
(cond:4)00011111(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREXH_A1
# See ARMv8/nARMv8 for the differing encodings of these instructions
# A8.8.80 LDRH (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
......@@ -848,20 +836,10 @@
(cond:4)000PU0W0(Rn:4)(Rt:4)(0000)1111(Rm:4) {ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))} STRD_reg_A1 # Note manual disambiguation (see A5.2)
# A8.8.212 STREX
# A1 ARMv6*, ARMv7
(cond:4)00011000(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREX_A1
# A8.8.213 STREXB
# A1 ARMv6K, ARMv7
(cond:4)00011100(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREXB_A1
# A8.8.214 STREXD
# A1 ARMv6K, ARMv7
(cond:4)00011010(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREXD_A1
# A8.8.215 STREXH
# A1 ARMv6K, ARMv7
(cond:4)00011110(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREXH_A1
# See ARMv8/nARMv8 for the differing encodings of these instructions
# A8.8.217 STRH (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
......
Misc/decgen/encodings/ARMv8_AArch32 0 → 100644
View file @ c7711b01
# From DDI 0487A.g section J5
# Can be overlaid directly on top of the ARMv7 encodings
# F6.1.54 Load-Aquire
(cond:4)00011(sz:2)1(Rn:4)(Rt:4)(11)001001(1111) {ne(cond,15)} {ne(sz,1)} LDA_A1
# F6.1.210 Store-Release
(cond:4)00011(sz:2)0(Rn:4)(1111)(11)001001(Rt:4) {ne(cond,15)} {ne(sz,1)} STL_A1
# F6.1.56 Load-Aquire Exclusive
(cond:4)00011001(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEX_A1
(cond:4)00011011(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEXD_A1
(cond:4)00011101(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEXB_A1
(cond:4)00011111(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEXH_A1
# F6.1.212 Store-Release Exclusive
(cond:4)00011000(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEX_A1
(cond:4)00011010(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEXD_A1
(cond:4)00011100(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEXB_A1
(cond:4)00011110(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEXH_A1
# Table J5.7.1 External Debug
# DCPS1/2/3 has no A32 encoding
# F6.1.50 Halting breakpoint
(cond:4)00010(op:2)0(imm12:12)0(op2:3)(imm4:4) {ne(cond,15)} {eq(op2,7)} {lnot(op)} HLT_A1
# Table J5.7.2 Barriers and hints
# DMB OSHLD/NSHLD/ISHLD/LD see F6.1.44, same encoding as ARMv7
# DSB OSHLD/NSHLD/ISHLD/LD see F6.1.45, same encoding as ARMv7
# F6.1.179 Send event local
(cond:4)001100100000(11110000)00000101 {ne(cond,15)} SEVL_A1
# Table J5.7.3 TLB maintenance
# Accessed using MCR operations, so no new opcodes
# F6.1.40 CRC
(cond:4)00010(sz:2)0(Rn:4)(Rd:4)(0)(0)C(0)0(op2:3)(Rm:4) {ne(cond,15)} {eq(op2,4)} CRC_A1
# Note that [LDR|STR]EX[B|H|D] appear here because previously
# bits 8-11 SBO, but that recommendation has changed because
# ARMv8 has added [LDA|STL]EX[B|H|D] in the same instruction space.
# F4.2.10
(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4) {ne(cond,15)} {lor(eq(op,8),eq(op,9))} {eq(op1,1)} UNDEFINED
(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4) {ne(cond,15)} {lor(eq(op,10),eq(op,11))} {lnot(band(op1,2))} UNDEFINED
(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4) {ne(cond,15)} {ge(op,12)} {eq(op1,1)} UNDEFINED
# F6.1.229 STREX
# A1 ARMv6*, ARMv7
(cond:4)00011000(Rn:4)(Rd:4)(11)111001(Rt:4) {ne(cond,15)} STREX_A1
# F6.1.230 STREXB
# A1 ARMv6K, ARMv7
(cond:4)00011100(Rn:4)(Rd:4)(11)111001(Rt:4) {ne(cond,15)} STREXB_A1
# F6.1.231 STREXD
# A1 ARMv6K, ARMv7
(cond:4)00011010(Rn:4)(Rd:4)(11)111001(Rt:4) {ne(cond,15)} STREXD_A1
# F6.1.232 STREXH
# A1 ARMv6K, ARMv7
(cond:4)00011110(Rn:4)(Rd:4)(11)111001(Rt:4) {ne(cond,15)} STREXH_A1
# F6.1.79 LDREX
# A1 ARMv6*, ARMv7
(cond:4)00011001(Rn:4)(Rt:4)(11)111001(1111) {ne(cond,15)} LDREX_A1
# F6.1.80 LDREXB
# A1 ARMv6K, ARMv7
(cond:4)00011101(Rn:4)(Rt:4)(11)111001(1111) {ne(cond,15)} LDREXB_A1
# F6.1.81 LDREXD
# A1 ARMv6K, ARMv7
(cond:4)00011011(Rn:4)(Rt:4)(11)111001(1111) {ne(cond,15)} LDREXD_A1
# F6.1.82 LDREXH
# A1 ARMv6K, ARMv7
(cond:4)00011111(Rn:4)(Rt:4)(11)111001(1111) {ne(cond,15)} LDREXH_A1
Misc/decgen/encodings/ARMv8_nAArch32 0 → 100644
View file @ c7711b01
# From DDI 0487A.g section J5
# Overlay this with ARMv7 encodings to fill the holes where ARMv8 additions are
# F6.1.54 Load-Aquire
# F6.1.210 Store-Release
# F6.1.56 Load-Aquire Exclusive
# F6.1.212 Store-Release Exclusive
# These alias into the LDREX/STREX family (see below)
# F6.1.50 Halting breakpoint
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,7)} {lnot(op)} UNDEFINED
# F6.1.179 Send event local
(cond:4)001100100000(11110000)00000101 {ne(cond,15)} UNALLOCATED_MEM_HINT
# F6.1.40 CRC
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,4)} UNDEFINED
# Note that [LDR|STR]EX[B|H|D] appear here because previously
# bits 8-11 SBO, but that recommendation has changed because
# ARMv8 has added [LDA|STL]EX[B|H|D] in the same instruction space.
# A8.8.212 in DDI 0406C STREX
# A1 ARMv6*, ARMv7
(cond:4)00011000(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREX_A1
# A8.8.213 in DDI 0406C STREXB
# A1 ARMv6K, ARMv7
(cond:4)00011100(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREXB_A1
# A8.8.214 in DDI 0406C STREXD
# A1 ARMv6K, ARMv7
(cond:4)00011010(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREXD_A1
# A8.8.215 in DDI 0406C STREXH
# A1 ARMv6K, ARMv7
(cond:4)00011110(Rn:4)(Rd:4)(1111)1001(Rt:4) {ne(cond,15)} STREXH_A1
# A8.8.75 in DDI 0406C LDREX
# A1 ARMv6*, ARMv7
(cond:4)00011001(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREX_A1
# A8.8.76 in DDI 0406C LDREXB
# A1 ARMv6K, ARMv7
(cond:4)00011101(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREXB_A1
# A8.8.77 in DDI 0406C LDREXD
# A1 ARMv6K, ARMv7
(cond:4)00011011(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREXD_A1
# A8.8.78 in DDI 0406C LDREXH
# A1 ARMv6K, ARMv7
(cond:4)00011111(Rn:4)(Rt:4)(1111)1001(1111) {ne(cond,15)} LDREXH_A1
VersionNum
View file @ c7711b01
/* (1.87)
/* (1.88)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.87
#define Module_MajorVersion_CMHG 1.88
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 28 May 2016
#define Module_Date_CMHG 11 Nov 2016
#define Module_MajorVersion "1.87"
#define Module_Version 187
#define Module_MajorVersion "1.88"
#define Module_Version 188
#define Module_MinorVersion ""
#define Module_Date "28 May 2016"
#define Module_Date "11 Nov 2016"
#define Module_ApplicationDate "28-May-16"
#define Module_ApplicationDate "11-Nov-16"
#define Module_ComponentName "Library"
#define Module_ComponentPath "mixed/RiscOS/Library"
#define Module_FullVersion "1.87"
#define Module_HelpVersion "1.87 (28 May 2016)"
#define Module_LibraryVersionInfo "1:87"
#define Module_FullVersion "1.88"
#define Module_HelpVersion "1.88 (11 Nov 2016)"
#define Module_LibraryVersionInfo "1:88"
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