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Commit 6eb6ee2a authored by Jeffrey Lee's avatar Jeffrey Lee
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Add ARMops for PL310 L2 cache controller 

Detail:
  Unlike on the Cortex-A8 or Cortex-A15, the L2 cache that's used with the Cortex-A9 isn't hooked up to the standard ARMv7 CP15 cache maintenance ops. Instead, memory-mapped registers must be used to program and maintain the cache.
  Since the PL310 can't be detected automatically, this change adds support for a 'cache controller' HAL device which the HAL can use to advertise the presence of any external caches. If a cache device is registered during HAL_InitDevices the kernel will then check it against a list of known cache types and replace the appropriate ARMop routines with the alternatives for that controller.
  File changes:
  - hdr/PL310 - New header containing PL310 register listing
  - Makefile - Add export for PL310 header. Reorder exports to be alphabetical
  - hdr/HALDevice - Add cache controller device type, PL310 device
  - hdr/KernelWS - Allocate some workspace for storing a pointer to the current cache HAL device
  - s/ARMops - Add code for searching for known cache types, and implementation of PL310-specific ARMops
  - s/GetAll - Get Hdr:PL310
  - s/NewReset - Look for a cache controller after calling HAL_InitDevices
Admin:
  Tested on Pandaboard
  Fixes various assorted instability issues


Version 5.35, 4.79.2.252. Tagged as 'Kernel-5_35-4_79_2_252'
parent 4843ce7e
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Showing with 461 additions and 56 deletions
Makefile
View file @ 6eb6ee2a
......@@ -32,25 +32,26 @@ ASFLAGS = -PD "FreezeDevRel SETL {${FREEZE_DEV_REL}}"
CUSTOMROM = custom
CUSTOMEXP = custom
EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.GPIODevice \
${EXP_HDR}.HALDevice \
${EXP_HDR}.HALEntries \
${EXP_HDR}.ModHand \
${EXP_HDR}.OSEntries \
${EXP_HDR}.OSRSI6 \
${EXP_HDR}.PL310 \
${EXP_HDR}.PublicWS \
${EXP_HDR}.RISCOS \
${EXP_HDR}.Variables \
${EXP_HDR}.VduExt \
${EXP_HDR}.HALEntries \
${EXP_HDR}.HALDevice \
${EXP_HDR}.VideoDevice \
${EXP_HDR}.GPIODevice \
${EXP_HDR}.OSEntries \
${EXP_HDR}.OSRSI6 \
${EXP_HDR}.VIDCList \
${C_EXP_HDR}.ModHand \
${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.HALEntries \
${EXP_HDR}.VideoDevice \
${C_EXP_HDR}.HALDevice \
${C_EXP_HDR}.HALEntries \
${C_EXP_HDR}.ModHand \
${C_EXP_HDR}.OSEntries \
${C_EXP_HDR}.Variables \
${C_EXP_HDR}.OSRSI6 \
${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.Variables \
${C_EXP_HDR}.VduExt \
${C_EXP_HDR}.VIDCList
......@@ -96,9 +97,27 @@ export: ${EXPORTS}
${EXP_HDR}.EnvNumbers: hdr.EnvNumbers
${CP} hdr.EnvNumbers $@ ${CPFLAGS}
${EXP_HDR}.GPIODevice: hdr.GPIODevice
${CP} hdr.GPIODevice $@ ${CPFLAGS}
${EXP_HDR}.HALDevice: hdr.HALDevice
${CP} hdr.HALDevice $@ ${CPFLAGS}
${EXP_HDR}.HALEntries: hdr.HALEntries
${CP} hdr.HALEntries $@ ${CPFLAGS}
${EXP_HDR}.ModHand: hdr.ModHand
${CP} hdr.ModHand $@ ${CPFLAGS}
${EXP_HDR}.OSEntries: hdr.OSEntries
${CP} hdr.OSEntries $@ ${CPFLAGS}
${EXP_HDR}.OSRSI6: hdr.OSRSI6
${CP} hdr.OSRSI6 $@ ${CPFLAGS}
${EXP_HDR}.PL310: hdr.PL310
${CP} hdr.PL310 $@ ${CPFLAGS}
${EXP_HDR}.PublicWS: hdr.PublicWS
${CP} hdr.PublicWS $@ ${CPFLAGS}
......@@ -106,63 +125,48 @@ ${EXP_HDR}.PublicWS: hdr.PublicWS
${EXP_HDR}.RISCOS: hdr.RISCOS
${CP} hdr.RISCOS $@ ${CPFLAGS}
${EXP_HDR}.Variables: hdr.Variables
${CP} hdr.Variables $@ ${CPFLAGS}
${EXP_HDR}.VduExt: hdr.VduExt
${CP} hdr.VduExt $@ ${CPFLAGS}
${EXP_HDR}.Variables: hdr.Variables
${CP} hdr.Variables $@ ${CPFLAGS}
${EXP_HDR}.HALEntries: hdr.HALEntries
${CP} hdr.HALEntries $@ ${CPFLAGS}
${EXP_HDR}.HALDevice: hdr.HALDevice
${CP} hdr.HALDevice $@ ${CPFLAGS}
${EXP_HDR}.OSEntries: hdr.OSEntries
${CP} hdr.OSEntries $@ ${CPFLAGS}
${EXP_HDR}.VIDCList: hdr.VIDCList
${CP} hdr.VIDCList $@ ${CPFLAGS}
${EXP_HDR}.VideoDevice: hdr.VideoDevice
${CP} hdr.VideoDevice $@ ${CPFLAGS}
${EXP_HDR}.GPIODevice: hdr.GPIODevice
${CP} hdr.GPIODevice $@ ${CPFLAGS}
${EXP_HDR}.OSRSI6: hdr.OSRSI6
${CP} hdr.OSRSI6 $@ ${CPFLAGS}
${EXP_HDR}.VIDCList: hdr.VIDCList
${CP} hdr.VIDCList $@ ${CPFLAGS}
${C_EXP_HDR}.HALDevice: Global.h.HALDevice h.HALDevice
${FAPPEND} $@ h.HALDevice Global.h.HALDevice
${C_EXP_HDR}.HALEntries: hdr.HALEntries
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.HALEntries $@
${C_EXP_HDR}.ModHand: hdr.ModHand
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.ModHand $@
${C_EXP_HDR}.RISCOS: hdr.RISCOS
${C_EXP_HDR}.OSEntries: Global.h.OSEntries h.OSEntries
${FAPPEND} $@ h.OSEntries Global.h.OSEntries
${C_EXP_HDR}.OSRSI6: hdr.OSRSI6
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.RISCOS $@
${HDR2H} hdr.OSRSI6 $@
${C_EXP_HDR}.HALEntries: hdr.HALEntries
${C_EXP_HDR}.RISCOS: hdr.RISCOS
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.HALEntries $@
${HDR2H} hdr.RISCOS $@
${C_EXP_HDR}.Variables: hdr.Variables
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.Variables $@
${C_EXP_HDR}.OSRSI6: hdr.OSRSI6
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.OSRSI6 $@
${C_EXP_HDR}.VduExt: hdr.VduExt
${MKDIR} ${C_EXP_HDR}
${HDR2H} hdr.VduExt $@
${C_EXP_HDR}.HALDevice: Global.h.HALDevice h.HALDevice
${FAPPEND} $@ h.HALDevice Global.h.HALDevice
${C_EXP_HDR}.OSEntries: Global.h.OSEntries h.OSEntries
${FAPPEND} $@ h.OSEntries Global.h.OSEntries
${C_EXP_HDR}.VIDCList: Global.h.VIDCList h.VIDCList
${FAPPEND} $@ h.VIDCList Global.h.VIDCList
......
VersionASM
View file @ 6eb6ee2a
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.251"
Module_Date SETS "09 Jan 2015"
Module_ApplicationDate SETS "09-Jan-15"
Module_MinorVersion SETS "4.79.2.252"
Module_Date SETS "11 Jan 2015"
Module_ApplicationDate SETS "11-Jan-15"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.251)"
Module_HelpVersion SETS "5.35 (09 Jan 2015) 4.79.2.251"
Module_FullVersion SETS "5.35 (4.79.2.252)"
Module_HelpVersion SETS "5.35 (11 Jan 2015) 4.79.2.252"
END
VersionNum
View file @ 6eb6ee2a
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.251
#define Module_Date_CMHG 09 Jan 2015
#define Module_MinorVersion_CMHG 4.79.2.252
#define Module_Date_CMHG 11 Jan 2015
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.251"
#define Module_Date "09 Jan 2015"
#define Module_MinorVersion "4.79.2.252"
#define Module_Date "11 Jan 2015"
#define Module_ApplicationDate "09-Jan-15"
#define Module_ApplicationDate "11-Jan-15"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.251)"
#define Module_HelpVersion "5.35 (09 Jan 2015) 4.79.2.251"
#define Module_FullVersion "5.35 (4.79.2.252)"
#define Module_HelpVersion "5.35 (11 Jan 2015) 4.79.2.252"
#define Module_LibraryVersionInfo "5:35"
hdr/HALDevice
View file @ 6eb6ee2a
......@@ -61,6 +61,7 @@ HALDeviceSysPeri_RTC # 1 ; RTCDevice
HALDeviceSysPeri_CPUClk # 1 ; CPU clock generator
HALDeviceSysPeri_BMU # 1 ; Battery management unit
HALDeviceSysPeri_NVRAM # 1 ; Low capacity non volatile storage
HALDeviceSysPeri_CacheC # 1 ; Cache controller
HALDeviceType_Comms * 4 :SHL: 8
^ 1
......@@ -202,6 +203,9 @@ HALDeviceID_Keyboard_Pandora # 1
^ 0
HALDeviceID_AHCI_IMX6 # 1
^ 0
HALDeviceID_CacheC_PL310 # 1
] ; Included_Hdr_HALDevice
OPT OldOpt
......
hdr/KernelWS
View file @ 6eb6ee2a
......@@ -1238,6 +1238,7 @@ Proc_MMU_ChangingUncachedEntries # 4
Cache_Lx_Info # 4 ; Cache level ID register
Cache_Lx_DTable # 4*7 ; Data/unified cache layout for all 7 levels
Cache_Lx_ITable # 4*7 ; Instruction cache layout for all 7 levels
Cache_HALDevice # 4 ; Pointer to any HAL cache device we're using
]
......
hdr/PL310 0 → 100644
View file @ 6eb6ee2a
; Copyright 2015 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; Register layout of the PL310 L2 cache controller
GET hdr:HALDevice
OldOpt SETA {OPT}
OPT OptNoList+OptNoP1List
PL310_REG0_CACHE_ID * &000
PL310_REG0_CACHE_TYPE * &004
PL310_REG1_CONTROL * &100
PL310_REG1_AUX_CONTROL * &104
PL310_REG1_TAG_RAM_CONTROL * &108
PL310_REG1_DATA_RAM_CONTROL * &10C
PL310_REG2_EV_COUNTER_CTRL * &200
PL310_REG2_EV_COUNTER1_CFG * &204
PL310_REG2_EV_COUNTER0_CFG * &208
PL310_REG2_EV_COUNTER1 * &20C
PL310_REG2_EV_COUNTER0 * &210
PL310_REG2_INT_MASK * &214
PL310_REG2_INT_MASK_STATUS * &218
PL310_REG2_INT_RAW_STATUS * &21C
PL310_REG2_INT_CLEAR * &220
PL310_REG7_CACHE_SYNC * &730
PL310_REG7_CACHE_SYNC_753970 * &740 ; Alternate location suggested in errata 753970 workaround
PL310_REG7_INV_PA * &770
PL310_REG7_INV_WAY * &77C
PL310_REG7_CLEAN_PA * &7B0
PL310_REG7_CLEAN_INDEX * &7B8
PL310_REG7_CLEAN_WAY * &7BC
PL310_REG7_CLEAN_INV_PA * &7F0
PL310_REG7_CLEAN_INV_INDEX * &7F8
PL310_REG7_CLEAN_INV_WAY * &7FC
PL310_REG9_D_LOCKDOWN0 * &900
PL310_REG9_I_LOCKDOWN0 * &904
PL310_REG9_D_LOCKDOWN1 * &908
PL310_REG9_I_LOCKDOWN1 * &90C
PL310_REG9_D_LOCKDOWN2 * &910
PL310_REG9_I_LOCKDOWN2 * &914
PL310_REG9_D_LOCKDOWN3 * &918
PL310_REG9_I_LOCKDOWN3 * &91C
PL310_REG9_D_LOCKDOWN4 * &920
PL310_REG9_I_LOCKDOWN4 * &924
PL310_REG9_D_LOCKDOWN5 * &928
PL310_REG9_I_LOCKDOWN5 * &92C
PL310_REG9_D_LOCKDOWN6 * &930
PL310_REG9_I_LOCKDOWN6 * &934
PL310_REG9_D_LOCKDOWN7 * &938
PL310_REG9_I_LOCKDOWN7 * &93C
PL310_REG9_LOCK_LINE_EN * &950
PL310_REG9_UNLOCK_WAY * &954
PL310_REG12_ADDR_FILTERING_START * &C00
PL310_REG12_ADDR_FILTERING_END * &C04
PL310_REG15_DEBUG_CTRL * &F40
PL310_REG15_PREFETCH_CTRL * &F60
PL310_REG15_POWER_CTRL * &F80
; PL310 revisions (low 5 bits of CACHE_ID)
PL310_R0P0 * 0
PL310_R1P0 * 2
PL310_R2P0 * 4
PL310_R3P0 * 5
PL310_R3P1 * 6
PL310_R3P1_50REL0 * 7
PL310_R3P2 * 8
PL310_R3P3 * 9
OPT OldOpt
END
s/ARMops
View file @ 6eb6ee2a
......@@ -2219,10 +2219,320 @@ MMU_ChangingUncachedEntries_WB_CR7_Lx ROUT
myISB ,lr,,y
Pull "a2,pc"
; --------------------------------------------------------------------------
; ----- ARMops for PL310 L2 cache controller--------------------------------
; --------------------------------------------------------------------------
; These are a hybrid of the standard ARMv7 ARMops (WB_CR7_Lx) and the PL310
; cache maintenance ops. Currently they're only used on Cortex-A9 systems, so
; may need modifications to work with other systems.
; Specifically, the code assumes the PL310 is being used in non-exclusive mode.
MACRO
PL310Sync $regs, $temp
; Errata 753970 requires us to write to a different location when
; performing a sync operation for r3p0
LDR $temp, [$regs, #PL310_REG0_CACHE_ID]
AND $temp, $temp, #&3f
TEQ $temp, #PL310_R3P0
MOV $temp, #0
STREQ $temp, [$regs, #PL310_REG7_CACHE_SYNC_753970]
STRNE $temp, [$regs, #PL310_REG7_CACHE_SYNC]
10
LDR $temp, [$regs, #PL310_REG7_CACHE_SYNC]
TST $temp, #1
BNE %BT10
MEND
Cache_CleanInvalidateAll_PL310 ROUT
; Errata 727915 workaround - use CLEAN_INV_INDEX instead of CLEAN_INV_WAY
Entry "a2-a4"
LDR a2, =ZeroPage
LDR a2, [a2, #Cache_HALDevice]
LDR a2, [a2, #HALDevice_Address]
; Clean ARM caches
BL Cache_CleanAll_WB_CR7_Lx
; Determine PL310 way, index count
LDR a1, [a2, #PL310_REG1_AUX_CONTROL]
AND a3, a1, #1<<16
AND a1, a1, #7<<17
MOV a3, a3, LSL #15
MOV a1, a1, LSR #17
LDR a4, =&FF<<5
ORR a3, a3, #7<<28 ; a3 = max way number (inclusive)
ORR a4, a4, a4, LSL a1 ; a4 = max index number (inclusive)
; Ensure no operation currently in progress
05
LDR lr, [a2, #PL310_REG7_CLEAN_INV_INDEX]
TST lr, #1
BNE %BT05
10
ORR a1, a3, a4
20
STR a1, [a2, #PL310_REG7_CLEAN_INV_INDEX]
30
LDR lr, [a2, #PL310_REG7_CLEAN_INV_INDEX]
TST lr, #1
BNE %BT30
SUBS a1, a1, #1<<28 ; next way
BCS %BT20 ; underflow?
SUBS a4, a4, #1<<5 ; next index
BGE %BT10
; Sync PL310
PL310Sync a2, a1
; Clean & invalidate ARM caches
PullEnv
B Cache_CleanInvalidateAll_WB_CR7_Lx
Cache_CleanAll_PL310 ROUT
Entry "a2"
LDR a2, =ZeroPage
LDR a2, [a2, #Cache_HALDevice]
LDR a2, [a2, #HALDevice_Address]
; Clean ARM caches
BL Cache_CleanAll_WB_CR7_Lx
; Clean PL310
LDR a1, [a2, #PL310_REG1_AUX_CONTROL]
TST a1, #1<<16
MOV a1, #&FF
ORRNE a1, a1, #&FF00 ; Mask of all ways
STR a1, [a2, #PL310_REG7_CLEAN_WAY]
10
LDR a1, [a2, #PL310_REG7_CLEAN_WAY]
TEQ a1, #0
BNE %BT10
; Sync PL310
PL310Sync a2, a1
EXIT
Cache_InvalidateAll_PL310 ROUT
Entry "a2"
LDR a2, =ZeroPage
LDR a2, [a2, #Cache_HALDevice]
LDR a2, [a2, #HALDevice_Address]
; Invalidate PL310
LDR a1, [a2, #PL310_REG1_AUX_CONTROL]
TST a1, #1<<16
MOV a1, #&FF
ORRNE a1, a1, #&FF00 ; Mask of all ways
STR a1, [a2, #PL310_REG7_INV_WAY]
10
LDR a1, [a2, #PL310_REG7_INV_WAY]
TEQ a1, #0
BNE %BT10
; Sync PL310
PL310Sync a2, a1
; Invalidate ARM caches
PullEnv
B Cache_InvalidateAll_WB_CR7_Lx
WriteBuffer_Drain_PL310 ROUT
Entry
LDR lr, =ZeroPage
LDR lr, [lr, #Cache_HALDevice]
LDR lr, [lr, #HALDevice_Address]
; Drain ARM write buffer
myDSB ,a1 ; DSB is the new name for write buffer draining
myISB ,a1,,y ; Also do ISB for extra paranoia
; Drain PL310 write buffer
PL310Sync lr, a1
EXIT
MMU_Changing_PL310 ROUT
Entry
myDSB ,a1 ; Ensure the page table write has actually completed
myISB ,a1,,y ; Also required
BL Cache_CleanInvalidateAll_PL310
MOV a1, #0
MCR p15, 0, a1, c8, c7, 0 ; invalidate ITLB and DTLB
myDSB ,a1,,y ; Wait for TLB invalidation to complete
myISB ,a1,,y ; Ensure that the effects are visible
EXIT
; a1 = page affected (page aligned address)
;
MMU_ChangingEntry_PL310 ROUT
Entry "a1-a4"
; MMU_ChangingEntry_WB_CR7_Lx performs a clean & invalidate before invalidating the TLBs.
; This means we must behave in a similar way to the PL310 clean & invalidate:
; * Clean ARM
; * Clean & invalidate PL310
; * Clean & invalidate ARM (i.e. do the MMU changing op)
; Convert logical addr to physical.
; Use the ARMv7 CP15 registers for convenience.
PHPSEI
MCR p15, 0, a1, c7, c8, 0 ; ATS1CPR
myISB ,a4
MRC p15, 0, a4, c7, c4, 0 ; Get result
PLP
TST a4, #1
BNE %FT50 ; Lookup failed - assume this means that the page doesn't need cleaning from the PL310
; Mask out the memory attributes that were returned by the lookup
[ NoARMT2
BIC a4, a4, #&FF
BIC a4, a4, #&F00
|
BFC a4, #0, #12
]
; Clean ARM
myDSB ,lr
myISB ,lr,,y
LDR lr, =ZeroPage
ADD a2, a1, #PageSize ;clean end address (exclusive)
LDRB a3, [lr, #DCache_LineLen] ; log2(line len)-2
MOV lr, #4
MOV a3, lr, LSL a3
10
MCR p15, 0, a1, c7, c10, 1 ; clean DCache entry to PoC
ADD a1, a1, a3
CMP a1, a2
BNE %BT10
myDSB ,a3 ; Wait for clean to complete
; Clean & invalidate PL310
LDR a2, =ZeroPage
LDR a2, [a2, #Cache_HALDevice]
LDR a2, [a2, #HALDevice_Address]
LDR a1, [a2, #PL310_REG1_AUX_CONTROL]
[ NoARMT2
AND a1, a1, #7<<17
MOV a1, a1, LSR #17
|
UBFX a1, a1, #17, #3
]
LDR lr, =&FF<<5
ORR a1, lr, lr, LSL a1 ; a1 = max index number (inclusive)
; Ensure we haven't re-entered an in-progress op
10
LDR lr, [a2, #PL310_REG7_CLEAN_INV_PA]
TST lr, #1
BNE %BT10
; Clean & invalidate each line/index of the page
ADD a1, a4, a1
20
STR a4, [a2, #PL310_REG7_CLEAN_INV_PA]
30
LDR lr, [a2, #PL310_REG7_CLEAN_INV_PA]
TST lr, #1
BNE %BT30
TEQ a4, a1
ADD a4, a4, #1<<5 ; next index
BNE %BT20
; Sync
PL310Sync a2, a1
50
; Clean & invalidate ARM (+ do MMU op)
PullEnv
B MMU_ChangingEntry_WB_CR7_Lx
; a1 = first page affected (page aligned address)
; a2 = number of pages
;
MMU_ChangingEntries_PL310
Entry "a2-a3"
; Keep this one simple and just split it into a series of per-page operations
; This will result in some unnecessary TLB invalidate & PL310 sync thrashing, so in the future a more advanced implementation might be nice.
CMP a2, #1024*1024/PageSize ; Arbitrary threshold for full clean
BHS %FT20
MOV a3, a1
10
MOV a1, a3
BL MMU_ChangingEntry_PL310
SUBS a2, a2, #1
ADD a3, a3, #PageSize
BNE %BT10
EXIT
20
; Full clean required
BL Cache_CleanInvalidateAll_PL310
MOV a1, #0
MCR p15, 0, a1, c8, c7, 0 ; invalidate ITLB and DTLB
myDSB ,a1,,y ; Wait TLB invalidation to complete
myISB ,a1,,y ; Ensure that the effects are visible
EXIT
] ; MEMM_Type = "VMSAv6"
; --------------------------------------------------------------------------
LookForHALCacheController ROUT
Entry "r0-r3,r8,r12"
; Look for any known cache controllers that the HAL has registered, and
; replace our ARMop routines with the appropriate routines for that
; controller
LDR r0, =(0:SHL:16)+HALDeviceType_SysPeri+HALDeviceSysPeri_CacheC
MOV r1, #0
10
MOV r8, #OSHW_DeviceEnumerate
SWI XOS_Hardware
EXIT VS
CMP r1, #-1
EXIT EQ
; Do we recognise this controller?
ASSERT HALDevice_ID = 2
[ NoARMv4
LDR lr, [r2]
MOV lr, lr, LSR #16
|
LDRH lr, [r2, #HALDevice_ID]
]
ADR r8, KnownHALCaches
20
LDR r12, [r8], #8+Proc_MMU_ChangingUncachedEntries-Proc_Cache_CleanInvalidateAll
CMP r12, #-1
BEQ %BT10
CMP lr, r12
BNE %BT20
; Cache recognised. Disable IRQs for safety, and then try enabling it.
Push "r2"
MOV r0, r2
MSR CPSR_c, #SVC32_mode+I32_bit
MOV lr, pc
LDR pc, [r2, #HALDevice_Activate]
CMP r0, #1
Pull "r2"
MSRNE CPSR_c, #SVC32_mode
BNE %BT10
; Cache enabled OK - remember the device pointer and patch our maintenance ops
LDR r0, =ZeroPage
STR r2, [r0, #Cache_HALDevice]
ADD r0, r0, #Proc_Cache_CleanInvalidateAll
MOV r1, #Proc_MMU_ChangingUncachedEntries-Proc_Cache_CleanInvalidateAll
30
LDR r3, [r8, #-4]!
TEQ r3, #0
STRNE r3, [r0, r1]
SUBS r1, r1, #4
BGE %BT30
; It's now safe to restore IRQs
MSR CPSR_c, #SVC32_mode
EXIT
KnownHALCaches ROUT
[ MEMM_Type = "VMSAv6"
DCD HALDeviceID_CacheC_PL310
01
DCD Cache_CleanInvalidateAll_PL310
DCD Cache_CleanAll_PL310
DCD Cache_InvalidateAll_PL310
DCD 0 ; Cache_RangeThreshold - may want to tweak?
DCD 0 ; TLB_InvalidateAll
DCD 0 ; TLB_InvalidateEntry
DCD WriteBuffer_Drain_PL310
DCD 0 ; IMB_Full
DCD 0 ; IMB_Range
DCD MMU_Changing_PL310
DCD MMU_ChangingEntry_PL310
DCD 0 ; MMU_ChangingUncached
DCD 0 ; MMU_ChangingUncachedEntry
DCD MMU_ChangingEntries_PL310
DCD 0 ; MMU_ChangingUncachedEntries
ASSERT . - %BT01 = 4+Proc_MMU_ChangingUncachedEntries-Proc_Cache_CleanInvalidateAll
]
DCD -1
; --------------------------------------------------------------------------
; IMPORT Write0_Translated
......
s/GetAll
View file @ 6eb6ee2a
......@@ -78,6 +78,7 @@
GET Hdr:SerialOp
GET Hdr:Keyboard
GET Hdr:OSRSI6
GET Hdr:PL310
; now the main parts of the MOS
......
s/NewReset
View file @ 6eb6ee2a
......@@ -1541,6 +1541,7 @@ ResetPart1Done ; R0 is reset type
STR R0, [R1, #DeviceTable]
]
CallHAL HAL_InitDevices ; get HAL to register any devices it has
BL LookForHALCacheController
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BL L1L2PTenhancements ; little tricks on cacheability etc for performance
]
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