Fix detection of ARMv7 minimum cache line lengths

Detail:
  s/ARMops - Replace the code to calculate the minimum cache line lengths with something much simpler which reads the values directly from the cache type register.
  The old code was buggy in two ways:
  (a) the cache size identification register stores the line length as log2(num words)-2, whereas the code throughout the kernel was expecting it to be log2(num bytes)-2
  (b) the loop is structured so that it will try and read the details of a non-existent cache level. although it doesn't read anything from CP15, it does result in the minimum cache line length values getting clobbered
  The net result of the above two bugs being that the OS would treat the CPU as if the minimum line length was just 4 bytes (although other than slowing down cache maintenance ops, this shouldn't have had any bad side-effects)
  The cache type register directly contains the minimum line lengths as log2(num bytes)-2, so by switching over to use that everything is now fine.
Admin:
  Tested on BB-xM, Pandaboard
  Fixes issue spotted by Willi Theiss


Version 5.35, 4.79.2.251. Tagged as 'Kernel-5_35-4_79_2_251'

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.250"
-Module_Date             SETS    "21 Dec 2014"
-Module_ApplicationDate  SETS    "21-Dec-14"
+Module_MinorVersion     SETS    "4.79.2.251"
+Module_Date             SETS    "09 Jan 2015"
+Module_ApplicationDate  SETS    "09-Jan-15"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.250)"
-Module_HelpVersion      SETS    "5.35 (21 Dec 2014) 4.79.2.250"
+Module_FullVersion      SETS    "5.35 (4.79.2.251)"
+Module_HelpVersion      SETS    "5.35 (09 Jan 2015) 4.79.2.251"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.250
-#define Module_Date_CMHG                21 Dec 2014
+#define Module_MinorVersion_CMHG        4.79.2.251
+#define Module_Date_CMHG                09 Jan 2015
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.250"
-#define Module_Date                     "21 Dec 2014"
+#define Module_MinorVersion             "4.79.2.251"
+#define Module_Date                     "09 Jan 2015"
 
-#define Module_ApplicationDate          "21-Dec-14"
+#define Module_ApplicationDate          "09-Jan-15"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.250)"
-#define Module_HelpVersion              "5.35 (21 Dec 2014) 4.79.2.250"
+#define Module_FullVersion              "5.35 (4.79.2.251)"
+#define Module_HelpVersion              "5.35 (09 Jan 2015) 4.79.2.251"
 #define Module_LibraryVersionInfo       "5:35"

s/ARMops

@@ -528,32 +528,32 @@ Analyse_WB_CR7_Lx
         TST     v5, #CPUFlag_SplitCache
         BEQ     WeirdARMPanic             ; currently, only support harvard caches here
 
+        ; Read smallest instruction & data/unified cache line length
+        MRC     p15, 0, a1, c0, c0, 1 ; Cache type register
+        MOV     v2, a1, LSR #16
+        AND     a4, a1, #&F
+        AND     v2, v2, #&F
+        STRB    a4, [v6, #ICache_LineLen] ; Store log2(line size)-2
+        STRB    v2, [v6, #DCache_LineLen] ; log2(line size)-2
+
         ; Read the cache info into Cache_Lx_*
         MRC     p15, 1, a1, c0, c0, 1 ; Cache level ID register
         MOV     v2, v6 ; Work around DTable/ITable alignment issues
         STR     a1, [v2, #Cache_Lx_Info]!
         ADD     a2, v2, #Cache_Lx_DTable-Cache_Lx_Info
         MOV     a3, #0
-        MOV     a4, #256 ; Smallest instruction cache line length
-        MOV     v2, #256 ; Smallest data/unified cache line length (although atm we only need this to be the smallest data cache line length)
 10
         ANDS    v1, a1, #6 ; Data or unified cache at this level?
         MCRNE   p15, 2, a3, c0, c0, 0 ; Program cache size selection register
         myISB   ,v1
         MRCNE   p15, 1, v1, c0, c0, 0 ; Get size info (data/unified)
         STR     v1, [a2]
-        AND     v1, v1, #7 ; Get line size
-        CMP     v1, v2
-        MOVLT   v2, v1
         ADD     a3, a3, #1
         ANDS    v1, a1, #1 ; Instruction cache at this level?
         MCRNE   p15, 2, a3, c0, c0, 0 ; Program cache size selection register
         myISB   ,v1
         MRCNE   p15, 1, v1, c0, c0, 0 ; Get size info (instruction)
         STR     v1, [a2, #Cache_Lx_ITable-Cache_Lx_DTable]
-        AND     v1, v1, #7 ; Get line size
-        CMP     v1, a4
-        MOVLT   a4, v1
         ; Shift the cache level ID register along to get the type of the next
         ; cache level
         ; However, we need to stop once we reach the first blank entry, because
@@ -569,8 +569,6 @@ Analyse_WB_CR7_Lx
         CMP     a3, #14 ; Stop after level 7 (even though an 8th level might exist on some CPUs?)
         ADD     a2, a2, #4
         BLT     %BT10
-        STRB    a4, [v6, #ICache_LineLen] ; Store log2(line size)-2
-        STRB    v2, [v6, #DCache_LineLen] ; log2(line size)-2
 
         ; Calculate DCache_RangeThreshold
         MOV     a1, #128*1024 ; Arbitrary-ish