Commit 1bd9c9e0 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Update Cortex branch of kernel to support HALSize env variable. Export C version of hdr.OSEntries.

Detail:
  Makefile - Now exports a C version of hdr.OSEntries, for use by the new HAL USB drivers
  s/GetAll, s/Kernel - The HALSize env variable is now used in place of hard-coded values for the HAL size
  s/HAL - Reset_IRQ_Handler now switches to SVC mode before calling HAL_KbdScanInterrupt, to allow the HAL USB drivers to re-enable interrupts if they wish.
  s/VMSAv6 - Deleted some obsolete definitions
Admin:
  Tested on rev C2 BB, A2 BB-xM, C1 TouchBook
  Needs latest BuildSys, Env, HdrSrc


Version 5.35, 4.79.2.98.2.37. Tagged as 'Kernel-5_35-4_79_2_98_2_37'
parent 2f8b5459
...@@ -69,7 +69,8 @@ EXPORTS = ${EXP_HDR}.EnvNumbers \ ...@@ -69,7 +69,8 @@ EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.OSEntries \ ${EXP_HDR}.OSEntries \
${C_EXP_HDR}.RISCOS \ ${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.HALEntries \ ${C_EXP_HDR}.HALEntries \
${C_EXP_HDR}.HALDevice ${C_EXP_HDR}.HALDevice \
${C_EXP_HDR}.OSEntries
# #
# Generic rules: # Generic rules:
...@@ -186,6 +187,10 @@ ${C_EXP_HDR}.HALDevice: o.Global.h.HALDevice h.HALDevice ...@@ -186,6 +187,10 @@ ${C_EXP_HDR}.HALDevice: o.Global.h.HALDevice h.HALDevice
${CP} h.HALDevice $@ ${CPFLAGS} ${CP} h.HALDevice $@ ${CPFLAGS}
print o.Global.h.HALDevice { >> $@ } print o.Global.h.HALDevice { >> $@ }
${C_EXP_HDR}.OSEntries: hdr.OSEntries
${MKDIR} ${C_EXP_HDR}
perl Build:Hdr2H hdr.OSEntries $@
o.Global.h.HALDevice: hdr.HALDevice o.Global.h.HALDevice: hdr.HALDevice
${MKDIR} o.Global.h ${MKDIR} o.Global.h
dir o dir o
......
...@@ -13,11 +13,11 @@ ...@@ -13,11 +13,11 @@
GBLS Module_ComponentPath GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35" Module_MajorVersion SETS "5.35"
Module_Version SETA 535 Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.36" Module_MinorVersion SETS "4.79.2.98.2.37"
Module_Date SETS "19 Mar 2011" Module_Date SETS "22 May 2011"
Module_ApplicationDate SETS "19-Mar-11" Module_ApplicationDate SETS "22-May-11"
Module_ComponentName SETS "Kernel" Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel" Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.36)" Module_FullVersion SETS "5.35 (4.79.2.98.2.37)"
Module_HelpVersion SETS "5.35 (19 Mar 2011) 4.79.2.98.2.36" Module_HelpVersion SETS "5.35 (22 May 2011) 4.79.2.98.2.37"
END END
...@@ -5,19 +5,19 @@ ...@@ -5,19 +5,19 @@
* *
*/ */
#define Module_MajorVersion_CMHG 5.35 #define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.36 #define Module_MinorVersion_CMHG 4.79.2.98.2.37
#define Module_Date_CMHG 19 Mar 2011 #define Module_Date_CMHG 22 May 2011
#define Module_MajorVersion "5.35" #define Module_MajorVersion "5.35"
#define Module_Version 535 #define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.36" #define Module_MinorVersion "4.79.2.98.2.37"
#define Module_Date "19 Mar 2011" #define Module_Date "22 May 2011"
#define Module_ApplicationDate "19-Mar-11" #define Module_ApplicationDate "22-May-11"
#define Module_ComponentName "Kernel" #define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel" #define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.36)" #define Module_FullVersion "5.35 (4.79.2.98.2.37)"
#define Module_HelpVersion "5.35 (19 Mar 2011) 4.79.2.98.2.36" #define Module_HelpVersion "5.35 (22 May 2011) 4.79.2.98.2.37"
#define Module_LibraryVersionInfo "5:35" #define Module_LibraryVersionInfo "5:35"
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
GET Hdr:System GET Hdr:System
GET Hdr:CPU.Arch GET Hdr:CPU.Arch
GET Hdr:Machine.<Machine> GET Hdr:Machine.<Machine>
GET Hdr:HALSize.<HALSize>
GET Hdr:ImageSize.<ImageSize> GET Hdr:ImageSize.<ImageSize>
GET Hdr:UserIF.<UserIF> GET Hdr:UserIF.<UserIF>
$GetCPU $GetCPU
......
...@@ -2384,8 +2384,11 @@ DebugHALPrint ...@@ -2384,8 +2384,11 @@ DebugHALPrint
Reset_IRQ_Handler Reset_IRQ_Handler
SUB lr, lr, #4 SUB lr, lr, #4
Push "a1-a4,v1-v2,sb,ip,lr" Push "a1-a4,v1-v2,sb,ip,lr"
MRS lr, SPSR MRS a1, SPSR
Push "lr" MRS a2, CPSR
ORR a3, a2, #SVC32_mode
MSR CPSR_c, a3
Push "a1-a2,lr"
MOV v2, #0 MOV v2, #0
AddressHAL v2 AddressHAL v2
MOV v1, #IICBus_Base MOV v1, #IICBus_Base
...@@ -2402,8 +2405,9 @@ Reset_IRQ_Handler ...@@ -2402,8 +2405,9 @@ Reset_IRQ_Handler
LDRB a1, [a1, #KbdScanActive] LDRB a1, [a1, #KbdScanActive]
TEQ a1, #0 TEQ a1, #0
CallHAL HAL_KbdScanInterrupt,NE CallHAL HAL_KbdScanInterrupt,NE
Pull "lr" Pull "a1-a2,lr"
MSR SPSR_cxsf, lr MSR CPSR_c, a2
MSR SPSR_cxsf, a1
Pull "a1-a4,v1-v2,sb,ip,pc",,^ Pull "a1-a4,v1-v2,sb,ip,pc",,^
END END
......
...@@ -320,7 +320,7 @@ CBack_VectorReq * 4 ...@@ -320,7 +320,7 @@ CBack_VectorReq * 4
OPT 4 OPT 4
[ HAL [ HAL
ORG ROM + 64*1024 ORG ROM + OSROM_HALSize
| |
ORG ROM ORG ROM
] ]
...@@ -337,7 +337,7 @@ KernelBase ...@@ -337,7 +337,7 @@ KernelBase
; ***************************************************************************** ; *****************************************************************************
[ HAL [ HAL
; ORG ROM + 64*1024 ; ORG ROM + OSROM_HALSize
| |
; ORG ROM ; ORG ROM
] ]
...@@ -354,7 +354,7 @@ DoTestThings SETS "" ...@@ -354,7 +354,7 @@ DoTestThings SETS ""
RISCOS_Header RISCOS_Header
= "OSIm" = "OSIm"
DCD 0 DCD 0
DCD OSROM_ImageSize*1024 - 64*1024 DCD OSROM_ImageSize*1024 - OSROM_HALSize
DCD RISCOS_Entries - RISCOS_Header DCD RISCOS_Entries - RISCOS_Header
DCD (RISCOS_Entries_End - RISCOS_Entries) / 4 DCD (RISCOS_Entries_End - RISCOS_Entries) / 4
......
...@@ -29,29 +29,6 @@ DebugAborts SETL {FALSE} ...@@ -29,29 +29,6 @@ DebugAborts SETL {FALSE}
ASSERT :LNOT: ECC ASSERT :LNOT: ECC
ASSERT :LNOT: ARM6support ASSERT :LNOT: ARM6support
; Fixed page allocation is as follows
^ 0
; Undefined stack memory (size 8K) starts immediately after end of L2PT (which is variable size)
; Soft CAM map (variable size) starts immediately after end of UndStack
StaticPagesSize * @
; Logical addresses are as follows
FixedAreasL2Size * 96*1024 ; amount of L2 to cover fixed areas, excluding free pool
UndStackSoftCamChunk * &01E00000
UndStackSize * 8*1024
CamEntriesForVicky * UndStackSoftCamChunk + UndStackSize
; - address for virtual area for StrongARM data cache cleaning (32k, for two 16k areas)
; - the two areas are used in strict rotation for each full clean, so that we can do a full
; clean (and not flush) with interrupts on
; - the address must be aligned such that EOR with 16*1024 flipflops between the two addresses
ARMA_Cleaners_address * &01F10000
OneMByte EQU (1024*1024) OneMByte EQU (1024*1024)
SixteenMByte EQU (1024*1024 * 16) SixteenMByte EQU (1024*1024 * 16)
......
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